CN209946731U - Power supply circuit and electric equipment - Google Patents
Power supply circuit and electric equipment Download PDFInfo
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- CN209946731U CN209946731U CN201920747871.8U CN201920747871U CN209946731U CN 209946731 U CN209946731 U CN 209946731U CN 201920747871 U CN201920747871 U CN 201920747871U CN 209946731 U CN209946731 U CN 209946731U
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Abstract
The utility model discloses a power supply circuit and consumer. Wherein, power supply circuit includes: the current copying circuit comprises a current input circuit and a current output circuit, wherein the current input circuit is used for generating a first reference current, and the current output circuit is used for copying and outputting a second reference current; wherein the second reference current is proportional to the first reference current; two adjustable resistance circuits, each adjustable resistance circuit comprising a resistance circuit and a control circuit, the control circuit being arranged to adjust the resistance of the resistance circuit according to an input voltage difference so that the input voltage difference is within a preset range; the resistance circuit of the first adjustable resistance circuit and the current input circuit are connected in series between the first power supply end and the grounding end; and the resistance circuit of the second adjustable resistance circuit is connected between the current output circuit and the output end of the power supply circuit.
Description
Technical Field
The utility model relates to a power technical field especially relates to a power supply circuit and consumer.
Background
With the development of scientific technology, electrical equipment is generally applied to various fields, such as daily life or scientific research. Meanwhile, a power circuit for supplying power to an electric device is also widely used.
Currently, a common power circuit is shown in fig. 1. The working principle of the power supply circuit is as follows: the band-gap reference voltage Vbg output by the band-gap reference voltage source is applied to a reference resistor R by using a feedback loop of the amplifier to generate a reference current. The reference current (shown by a MOS current mirror circuit in fig. 1) is copied by a MOS current mirror circuit or a BJT current mirror circuit, and an output current Iout output to the load is obtained. However, due to the channel length modulation effect of the transistor in the MOS-type current mirror circuit or the base width modulation effect of the transistor in the BJT-type current mirror circuit, the output current may be affected by the load and the power supply voltage that supplies power to the current mirror circuit, that is, the accuracy of the output current may be degraded. While the swing of the output voltage is limited. For example, in one extreme case, there is a tens of times change in output current when the load is shorted.
Therefore, a power supply circuit capable of suppressing the channel length modulation effect of a transistor in a MOS-type current mirror circuit or the base width modulation effect of a transistor in a BJT-type current mirror circuit is desired to be proposed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a new power supply circuit scheme.
According to the utility model discloses an aspect provides a power supply circuit, include:
the current copying circuit comprises a current input circuit and a current output circuit, wherein the current input circuit is used for generating a first reference current, and the current output circuit is used for copying and outputting a second reference current; wherein the second reference current is proportional to the first reference current;
two adjustable resistance circuits, each adjustable resistance circuit comprising a resistance circuit and a control circuit, the control circuit being arranged to adjust the resistance of the resistance circuit in dependence on an input voltage difference, such that the input voltage difference is within a predetermined range;
the resistance circuit of the first adjustable resistance circuit and the current input circuit are connected in series between a first power supply end and a ground end, and the voltage difference corresponding to the input of the first adjustable resistance circuit is as follows: a voltage difference between a voltage of a node of the current input circuit generating the first reference current and a preset bias voltage;
the resistance circuit of the second adjustable resistance circuit and the current output circuit are connected in series between the first power supply end and the output end of the power supply circuit, and the voltage difference corresponding to the input of the second adjustable resistance circuit is as follows: a voltage difference between a voltage of a node of the current output circuit that outputs the second reference current and the bias voltage.
Optionally, the power supply circuit further includes a current sampling circuit, a reference voltage source for providing a reference voltage, and a first amplifier;
the current sampling circuit is connected in series with the current input circuit and a resistor circuit of the first adjustable resistor circuit, and is configured to collect the first reference current and convert the first reference current into a feedback voltage;
the inverting input end of the first amplifier is connected with the reference voltage, the non-inverting input end of the first amplifier is connected with the feedback voltage, the output end of the first amplifier is connected with the control end of the current input circuit, and the first amplifier is arranged to control the current input circuit to adjust the generated first reference current according to the voltage difference between the reference voltage and the feedback voltage.
Optionally, the control circuit is a second amplifier;
the non-inverting input end of the second amplifier is connected with the bias voltage, and the output end of the second amplifier is connected with the control end of the resistance circuit;
in the first adjustable resistance circuit, the inverting input end of the second amplifier is connected with the voltage of a node of the current input circuit, which generates the first reference current;
in the second adjustable resistance circuit, the inverting input terminal of the second amplifier is connected to the voltage of the node of the current output circuit that outputs the second reference current.
Optionally, the control circuit includes a first PMOS transistor and a bias current source;
the source electrode of the first PMOS tube is connected with the bias voltage, the drain electrode of the first PMOS tube is respectively connected with the anode of the bias current source and the control end of the resistance circuit, and the cathode of the bias current source is grounded;
in the first adjustable resistance circuit, the grid electrode of the first PMOS tube is connected with the voltage of a node of the current input circuit, which generates the first reference current;
in the second adjustable resistance circuit, the gate of the first PMOS transistor is connected to the voltage of the node of the current output circuit, which outputs the second reference current.
Optionally, the resistor circuit is a second PMOS transistor, and a gate of the second PMOS transistor is set as a control end of the resistor circuit;
in the first adjustable resistance circuit, the source electrode of the second PMOS tube is connected with the node of the current input circuit, which generates the first reference current; the drain electrode of the second PMOS tube is connected with the current sampling circuit;
in the second adjustable resistance circuit, a source of the second PMOS transistor is connected to a node of the current output circuit, where the second reference current is output, and a drain of the second PMOS transistor is used as an output terminal of the power supply circuit.
Optionally, the adjustable resistance circuit further includes a bias voltage source for providing the bias voltage, and the bias voltage source includes: a Zener diode, a resistor;
the cathode of the Zener diode is connected with the second power supply end; the anode of the Zener diode is connected with one end of the resistor; the other end of the resistor is grounded; and an output end of the bias voltage source for outputting the bias voltage is led out between the anode of the Zener diode and one end of the resistor.
Optionally, the bias voltage is provided by the first power supply terminal.
Optionally, the current replica circuit is a cascode gate mirror circuit.
Optionally, the cascode current mirror circuit includes K third PMOS transistors and J fourth PMOS transistors;
the source electrodes of the K third PMOS tubes are connected to the first power supply end, the grid electrodes of the K third MOS tubes are used as the control ends of the current input circuit, and the drain electrodes of the K third PMOS tubes are used as nodes of the current input circuit for generating the first reference current;
the source electrodes of the J fourth PMOS tubes are connected to the first power supply end, the grid electrodes of the J fourth PMOS tubes are connected with the control end of the current input circuit, and the drain electrodes of the J fourth PMOS tubes are used as nodes of the current output circuit for outputting the second reference current;
k-1 logic switches are arranged between the source electrodes of any K-1 third PMOS tubes and the first power supply end, and the K-1 logic switches are respectively arranged to control the connection states of the source electrodes of the third PMOS tubes and the first power supply end according to the on-off states of the logic switches;
j-1 logic switches are arranged between the source electrodes of any J-1 fourth PMOS tubes and the first power supply end, and the J-1 logic switches are respectively arranged to control the connection states of the source electrodes of the fourth PMOS tubes and the first power supply end according to the on-off states of the logic switches;
j and K are integers larger than 1, and the width-to-length ratio of the third PMOS tube to the fourth PMOS tube is the same.
Optionally, the cascode current mirror circuit includes X first NMOS transistors and Y second NMOS transistors;
the source electrodes of the X first NMOS tubes are grounded, the grid electrodes of the X first NMOS tubes are used as the control ends of the current input circuit, and the drain electrodes of the X first NMOS tubes are used as the nodes of the current input circuit for generating the first reference current;
the source electrodes of the Y second NMOS tubes are grounded, the grid electrodes of the Y second NMOS tubes are connected with the control end of the current input circuit, and the drain electrodes of the Y second NMOS tubes are used as nodes of the current output circuit for outputting the second reference current;
the X-1 logic switches are arranged between the source electrode and the grounding terminal of any X-1 first NMOS tube, and the X-1 logic switches are respectively arranged to control the connection state of the source electrode and the grounding terminal of the first NMOS tube according to the on-off state of the logic switches;
y-1 logic switches are arranged between the source electrode and the grounding terminal of any Y-1 second NMOS tubes, and the Y-1 logic switches are respectively arranged to control the connection state of the source electrode and the grounding terminal of the second NMOS tubes according to the on-off state of the logic switches;
y and X are integers larger than 1, and the width-to-length ratio of the first NMOS tube to the second NMOS tube is the same.
Optionally, the power circuit further includes a current-to-voltage circuit;
the current-to-voltage circuit is configured to: receiving the second reference current and outputting a voltage proportional to the second reference current.
Optionally, the current-to-voltage circuit converts the second reference current into a voltage output through a zero temperature coefficient resistor.
According to a second aspect of the present invention, there is provided an electric consumer comprising a power supply circuit as defined in the first aspect.
The embodiment of the utility model provides a power supply circuit can make the voltage that current input circuit produced the node of first reference current the same with the voltage of the node that current output circuit output second reference current, promptly when the current replica circuit is MOS type current mirror circuit, can make the channel length modulation effect in the current replica circuit suppressed, when the current replica circuit is BJT type current mirror circuit, can make the base region width modulation effect in the current replica circuit suppressed. Furthermore, the second reference current is prevented from being influenced by the load and the power supply voltage for providing power supply for the current copy circuit, so that the current precision of the power supply circuit is improved, and the swing of the output voltage is increased.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the invention and are therefore not to be considered limiting of its scope. For a person skilled in the art, it is possible to derive other relevant figures from these figures without inventive effort.
Fig. 1 is a schematic diagram of a conventional power circuit in the prior art;
fig. 2 is a first schematic structural diagram of a power circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram ii of a power circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram three of a power supply circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a power supply circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a power circuit according to an embodiment of the present invention;
fig. 7 is a sixth schematic structural diagram of a power supply circuit according to an embodiment of the present invention;
fig. 8 is a seventh schematic structural diagram of a power supply circuit according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless specifically stated otherwise, the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
< Power supply Circuit >
Referring to fig. 2 and 3, a power supply circuit of the present invention is explained. The power supply circuit includes: a current replica circuit and two adjustable resistance circuits. Wherein:
and the current copying circuit comprises a current input circuit and a current output circuit, wherein the current input circuit is used for generating a first reference current, and the current output circuit is used for copying and outputting a second reference current. Wherein the second reference current is proportional to the first reference current.
In one embodiment, the current replica circuit may be a MOS-type current mirror circuit, and the current replica circuit may also be a BJT-type current mirror.
The voltage regulator comprises two adjustable resistance circuits, wherein each adjustable resistance circuit comprises a resistance circuit and a control circuit, and the control circuit is set to adjust the resistance value of the resistance circuit according to the input voltage difference so as to enable the input voltage difference to be within a preset range.
The resistance circuit of the first adjustable resistance circuit and the current input circuit are connected in series between the first power supply end and the grounding end, and the voltage difference corresponding to the input of the first adjustable resistance circuit is as follows: the voltage difference between the voltage of a node of the current input circuit generating the first reference current and a preset bias voltage.
The resistance circuit and the current output circuit of the second adjustable resistance circuit are connected in series between the first power supply end and the output end of the power supply circuit, and the voltage difference corresponding to the input of the second adjustable resistance circuit is as follows: and a voltage difference between a voltage of a node of the current output circuit outputting the second reference current and the bias voltage.
It should be noted that, when the specific connection mode that the resistance circuit of the first adjustable resistance circuit and the current input circuit are connected in series between the first power supply terminal and the ground terminal is as shown in fig. 2, the power supply circuit provided by the present invention is an output power supply circuit. When the specific connection mode of the resistance circuit of the first adjustable resistance circuit and the current input circuit series connection between the first power supply terminal and the grounding terminal is as shown in fig. 3, the utility model provides a power supply circuit is an input type power supply circuit.
In one embodiment, the first reference current generated by the current input circuit is a reference current generated by a reference current source circuit connected to the current replica circuit.
In another embodiment, the first reference current source generated in the current input circuit is generated based on the current sampling circuit, the reference voltage source for providing the reference voltage, the first amplifier, the current input circuit, and the resistance circuit in the first adjustable resistance circuit, as shown in fig. 4 on the basis of fig. 2 described above, or as shown in fig. 5 on the basis of fig. 3 described above. That is, in this embodiment, the present invention provides a power supply circuit further including: the current sampling circuit, a reference voltage source for providing reference voltage and a first amplifier; wherein:
the current sampling circuit is connected in series with the current input circuit and the resistance circuit of the first adjustable resistance circuit, and the current sampling circuit is set to collect a first reference current and convert the first reference current into a feedback voltage. The inverting input end of the first amplifier is connected with a reference voltage, the non-inverting input end of the first amplifier is connected between the resistance circuit and the current sampling circuit so as to be connected with a feedback voltage, the output end of the first amplifier is connected with the control end of the current input circuit, and the first amplifier is arranged to control the current input circuit to adjust the generated first reference current according to the voltage difference between the reference voltage and the feedback voltage.
In this embodiment, the first amplifier, the current input circuit, the resistance circuit in the first adjustable resistance circuit, and the current sampling circuit constitute a negative feedback circuit. The first amplifier can control the current input circuit to adjust the generated first reference current according to the voltage difference between the reference voltage and the feedback voltage, so that the value of the first reference current is constant as the ratio of the reference voltage to the resistance value corresponding to the current sampling circuit.
In one example, the current sampling circuit may be a resistor with a fixed resistance value, or a resistor network with a function of logically adjusting the resistance value, or a resistor and a resistor network with a specific temperature coefficient, or a circuit structure with a specific equivalent resistance value and a specific temperature coefficient.
In one example, as shown in fig. 6, the reference voltage source includes: third amplifier, first resistance, second resistance, third resistance, first diode, second diode. The output end of the third amplifier is respectively connected with one end of the first resistor and one end of the second resistor, and the output end of the third amplifier is used as the output end of the reference voltage source for outputting the reference voltage; the non-inverting input end of the third amplifier is respectively connected with the other end of the first resistor and the anode of the first diode; the inverting input end of the third amplifier is respectively connected with the other end of the second resistor and one end of a third resistor, and the other end of the third resistor is connected with the anode of the second diode; the cathode of the first diode and the cathode of the second diode are grounded.
The reference voltage source may be a voltage source having a specific positive temperature coefficient or negative temperature coefficient, which is based on the bandgap reference concept. Therefore, the present invention is not limited herein.
In one embodiment, as shown in FIG. 6, the control circuit is a second amplifier; the non-inverting input end of the second amplifier is connected with a bias voltage, and the output end of the second amplifier is connected with the control end of the resistance circuit; in the first adjustable resistance circuit, the inverting input terminal of the second amplifier is connected to the voltage of the node of the current input circuit that generates the first reference current. In the second adjustable resistance circuit, the inverting input terminal of the second amplifier is connected to the voltage of the node of the current output circuit that outputs the second reference current.
In this embodiment, the control circuit is arranged to adjust the difference of the resistance circuits in accordance with the input voltage difference so that the input voltage difference is 0.
In another embodiment, based on the embodiment shown in fig. 4, as shown in fig. 7, the control circuit includes a first PMOS transistor and a bias current source. The source electrode of the first PMOS tube is connected with bias voltage, the drain electrode of the first PMOS tube is connected with the anode of the bias current source and the control end of the resistance circuit, and the cathode of the bias current source is grounded. In the first adjustable resistance circuit, the grid electrode of the first PMOS tube is connected with the voltage of a node of the current input circuit, which generates the first reference current. In the second adjustable resistance circuit, the grid electrode of the first PMOS tube is connected with the voltage of a node of the current output circuit, which outputs the second reference current.
In this embodiment, the control circuit is configured to adjust the difference of the resistor circuit according to the input voltage difference, so that the input voltage difference is the turn-on voltage of the first PMOS transistor.
In one embodiment, as shown in FIG. 6, the bias voltage described above may be provided by a bias voltage source. That is to say, the embodiment of the present invention provides an adjustable resistance circuit further including a bias voltage source for providing a bias voltage. Specifically, the bias voltage source includes: zener diode, resistance. Wherein, the cathode of the Zener diode is connected with the second power supply end; the anode of the Zener diode is connected with one end of the resistor; the other end of the resistor is grounded; an output end of the bias voltage source for outputting the bias voltage is led out between the anode of the Zener diode and one end of the resistor.
It should be noted that the bias voltage source shown in fig. 6 may be replaced by another voltage regulator device or a voltage regulator circuit. The embodiment of the present invention is not limited thereto. In addition, the second power supply terminal may be the first power supply terminal.
It should be noted that, in practical use, for the output power circuit, the bias voltage output by the bias voltage source may be designed to be proportional to the first power supply terminal. For an input-type power supply circuit, the bias voltage may be designed to be stable to ground. In addition, the bias voltage source in the first adjustable resistance circuit and the bias voltage source in the second adjustable resistance circuit may be one voltage source.
In another embodiment, as shown in fig. 7, the bias voltage may also be provided by the first power supply terminal. In this embodiment, the circuit configuration corresponding to the power supply circuit is relatively simple.
In the above implementation manner of the bias voltage, a difference between the bias voltage and the first power supply terminal for supplying power to the current replica circuit is a constant difference, so that a voltage of a node at which the current input circuit generates the first reference current is the same as and constant as a voltage of a node at which the current output circuit outputs the second reference current, and further, a channel length modulation effect of a transistor in the MOS-type current mirror circuit or a base width modulation effect of a transistor in the BJT-type current mirror circuit can be further suppressed.
Based on the contents of fig. 2 or fig. 4, in an embodiment, as shown in fig. 6, the resistor circuit is a second PMOS transistor, and a gate of the second PMOS transistor is set as a control terminal of the resistor circuit; in the first adjustable resistance circuit, the source electrode of the second PMOS tube is connected with a node of the current input circuit, which generates the first reference current; the drain electrode of the second PMOS tube is connected with the current sampling circuit; in the second adjustable resistance circuit, the source electrode of the second PMOS tube is connected with the node of the current output circuit, which outputs the second reference current, and the drain electrode of the second PMOS tube is used as the output end of the power supply circuit.
It should be noted that the resistor circuit may also be other P-type transistor devices, such as PNP transistor and PDMOS transistor. The resistor circuit may be designed as another circuit having the same function as the P-type transistor device.
In another embodiment, when the power circuit provided by the embodiment of the present invention is the input power circuit shown in fig. 3 or fig. 5, the resistor circuit is an N-type transistor device, such as an NMOS transistor, an NPN transistor, or an NDMOS transistor. The resistor circuit may be designed as another circuit having the same function as the N-type transistor device.
In one embodiment, the current replica circuit is a cascode gate mirror circuit. Of course, the current replica circuit may have other configurations. The present invention is not limited herein.
In one example, when the current replica circuit is a cascode current mirror circuit, the sources of all MOS transistors in the cascode current mirror circuit are connected to the first power supply terminal for supplying power to the MOS transistors on the basis of the embodiment shown in fig. 2 or 4. Based on this, as shown in fig. 6, the cascode current mirror circuit includes K third PMOS transistors and J fourth PMOS transistors; the source electrodes of the K third PMOS tubes are connected to the first power supply end, the grid electrodes of the K third PMOS tubes are used as the control end of the current input circuit, and the drain electrodes of the K third PMOS tubes are used as nodes of the current input circuit for generating first reference current; the source electrodes of the J fourth PMOS tubes are connected to the first power supply end, the grid electrodes of the J fourth PMOS tubes are connected with the control end of the current input circuit, and the drain electrodes of the J fourth PMOS tubes are used as nodes of the current output circuit for outputting second reference current; k-1 logic switches are arranged between the source electrodes of any K-1 third PMOS tubes and the first power supply end, and the K-1 logic switches are respectively arranged to control the connection state of the source electrodes of the third PMOS tubes and the first power supply end according to the on-off state of the logic switches; j-1 logic switches are arranged between the source electrodes of any J-1 fourth PMOS tubes and the first power supply end, and the J-1 logic switches are respectively arranged to control the connection states of the source electrodes of the fourth PMOS tubes and the first power supply end according to the on-off states of the logic switches; j and K are integers larger than 1, and the width-to-length ratio of the third PMOS tube to the fourth PMOS tube is the same.
In this example, the first supply terminal is used to provide a supply voltage for the cascode current mirror circuit. In this example, the ratio of the first reference current to the second reference current is a ratio between the number of logic switches in the on state among the K logic switches and the number of logic switches in the on state among the J logic switches.
It should be noted that, on the basis of the third PMOS transistor and the fourth PMOS transistor, the logic switch may be replaced by a logic switch pair. Specifically, the method comprises the following steps: and a pair of logic switches are respectively arranged between the grid electrode of the third PMOS tube and the first power supply end and between the grid electrode of the third PMOS tube and the output end of the first amplifier. When the logic switch between the grid electrode of the third PMOS tube and the output end of the first amplifier is switched on and the logic switch between the grid electrode of the third PMOS tube and the first power supply end is switched off, the third PMOS tube is connected into the cascode current mirror circuit. According to the setting mode, the number of the third PMOS tubes connected into the cascode current mirror circuit is controlled by setting K-1 pairs of logic switches. In addition, when the logic switch between the grid electrode of the third PMOS tube and the output end of the first amplifier is switched off, and the logic switch between the grid electrode of the third PMOS tube and the first power supply end is switched on, the third PMOS tube is not connected into the cascode current mirror circuit.
Correspondingly, a pair of logic switches is respectively arranged between the grid electrode of the fourth PMOS tube and the first power supply end, and between the grid electrode of the fourth PMOS tube and the output end of the first amplifier. When the logic switch between the grid electrode of the fourth PMOS tube and the output end of the first amplifier is switched on and the logic switch between the grid electrode of the fourth PMOS tube and the first power supply end is switched off, the fourth PMOS tube is connected into the cascode current mirror circuit. According to the arrangement mode, the number of the fourth PMOS tubes connected into the cascode gate current mirror circuit can be controlled by arranging the J-1 pairs of logic switches. In addition, when the logic switch between the grid electrode of the fourth PMOS tube and the output end of the first amplifier is turned off, and the logic switch between the grid electrode of the fourth PMOS tube and the first power supply end is turned on, the fourth PMOS tube is not connected into the cascode current mirror circuit.
In view of the above arrangement, the ratio of the first reference current to the second reference current is a ratio between the number of logic switches in a conducting state between the gate of the third PMOS transistor and the output terminal of the first amplifier and the number of logic switches in a conducting state between the gate of the fourth PMOS transistor and the output terminal of the first amplifier.
It should be further noted that the two logic switches in each pair of logic switches cannot be turned on simultaneously or turned off simultaneously. Furthermore, the utility model discloses among the power supply circuit, do not restrict the position of setting up of logic switch.
In another example, when the current replica circuit is a cascode current mirror circuit, the sources of all MOS transistors in the cascode current mirror circuit are grounded based on the embodiment shown in fig. 3 or 5. Based on this, the cascode current mirror circuit may include X first NMOS transistors and Y second NMOS transistors. Wherein: the source electrodes of the X first NMOS tubes are grounded, the grid electrodes of the X first NMOS tubes are used as the control ends of the current input circuit, and the drain electrodes of the X first NMOS tubes are used as nodes of the current input circuit for generating first reference current. The source electrodes of the Y second NMOS tubes are grounded, the grid electrodes of the Y second NMOS tubes are connected with the control end of the current input circuit, and the drain electrodes of the Y second NMOS tubes are used as nodes of the current output circuit for outputting second reference current; the X-1 logic switches are arranged between the source electrode of any X-1 first NMOS tube and the grounding end, and the X-1 logic switches are respectively arranged to control the connection state of the source electrode of the first NMOS tube and the grounding end according to the on-off state of the logic switches. Y-1 logic switches are arranged between the source electrode of any Y-1 second NMOS tube and the grounding end, and the Y-1 logic switches are respectively arranged to control the connection state of the source electrode of the second NMOS tube and the grounding end according to the on-off state of the logic switches. Y and X are integers larger than 1, and the width-to-length ratio of the first NMOS tube to the second NMOS tube is the same.
In this example, the logic switch may be one logic switch. In addition, the ratio of the first reference current to the second reference current is a ratio between the number of logic switches in the on state among the X logic switches and the number of logic switches in the on state among the Y logic switches.
It should be noted that, on the basis of the first NMOS transistor and the second NMOS transistor, the logic switch may be replaced by a logic switch pair. Specifically, the method comprises the following steps: and the pair of logic switches are respectively arranged between the grid electrode of the first NMOS tube and the grounding end and between the grid electrode of the first NMOS tube and the output end of the first amplifier. When the logic switch between the grid electrode of the first NMOS tube and the output end of the first amplifier is conducted and the logic switch between the grid electrode of the first NMOS tube and the grounding end is disconnected, the first NMOS tube is connected into the cascode current mirror circuit. According to the arrangement mode, the number of the first NMOS tubes connected into the cascode current mirror circuit is controlled by arranging X-1 pairs of logic switches. In addition, when the logic switch between the grid electrode of the first NMOS and the output end of the first amplifier is turned off, and the logic switch between the grid electrode of the first NMOS tube and the grounding end is turned on, the first NMOS tube is not connected into the cascode current mirror circuit.
Correspondingly, a pair of logic switches are respectively arranged between the grid electrode of the second NMOS tube and the grounding end, and between the grid electrode of the second NMOS tube and the output end of the first amplifier. When the logic switch between the grid electrode of the second NMOS tube and the output end of the first amplifier is conducted and the logic switch between the grid electrode of the second NMOS tube and the grounding end is disconnected, the second NMOS tube is connected into the cascode current mirror circuit. According to the arrangement mode, the number of the second NMOS tubes connected into the cascode current mirror circuit can be controlled by arranging Y-1 pairs of logic switches. In addition, when the logic switch between the grid electrode of the second NMOS tube and the output end of the first amplifier is turned off, and the logic switch between the grid electrode of the second NMOS tube and the grounding end is turned on, the second NMOS tube is not connected into the cascode current mirror circuit.
In view of the above arrangement, the ratio of the first reference current to the second reference current is a ratio between the number of logic switches in a conducting state between the gate of the first NMOS transistor and the output terminal of the first amplifier and the number of logic switches in a conducting state between the gate of the second NMOS transistor and the output terminal of the first amplifier.
It should be further noted that the two logic switches in each pair of logic switches cannot be turned on simultaneously or turned off simultaneously. Furthermore, the utility model discloses among the power supply circuit, do not restrict the position of setting up of logic switch.
Based on the current copy circuit provided by the above embodiment, the power supply circuit provided by the present invention can realize the second reference currents of different magnitudes, i.e. the wide-range current output. And the magnitude of the second reference current can be easily adjusted.
It should be noted that, for fig. 6, the minimum operating voltage difference of the power circuit provided in the embodiment of the present invention is: vDP＝VGSMP3-VTHMP3+minVDSMP2。
Wherein, VDPShowing the minimum working voltage difference, minVDS, of the power circuit provided by the embodiment of the utility modelMP2The second PMOS transistor is shown to operate in a linear region, and when the second PMOS transistor is equivalent to a resistor, the product of the resistor equivalent to the second PMOS transistor and the minimum current provided by the power circuit provided by the embodiment of the present invention is obtained. VGSMP3Showing the gate-source voltage, VTH, of the third PMOS tubeMP3The threshold voltage of the third PMOS transistor is shown.
Correspondingly, for fig. 7, the embodiment of the present invention provides a minimum working pressure difference V of a power circuitDPComprises the following steps: vDP＝VTHMP1+minVDSMP2
Wherein VTHMP1Indicating the threshold voltage of the first PMOS tube, minVDSMP2The second PMOS tube works in a linear region, and when the second PMOS tube is equivalent to a resistor, the resistor equivalent to the second PMOS tube is equal to that provided by the embodiment of the inventionThe product of the minimum currents that the power supply circuit can supply.
It should be noted that, referring to fig. 6 and 7, the first resistor is denoted as R1, the second resistor is denoted as R2, the third resistor is denoted as R3, the first diode is denoted as D1, the second diode is denoted as D2, the third amplifier is denoted as OPA3, the reference voltage provided by the reference voltage source is denoted as Vref, the first amplifier is denoted as OPA1, the zener diode is denoted as Z11, the resistor in the bias voltage source is denoted as R11, the resistor corresponding to the current transfer voltage circuit is denoted as Rf, the second amplifier is denoted as OPA2, the voltage of the node where the current input circuit generates the first reference current is denoted as Vs1, the voltage of the node where the current output circuit outputs the second reference current is denoted as Vs2, the second power supply terminal is denoted as Vdd2, the first PMOS terminal is denoted as Vdd1, the bias current source Ib, the second reference current is denoted as Iout, the first PMOS transistor is denoted as MP1, the second PMOS transistor MP 8, and K third PMOS transistors are denoted as MP31, MP K, the J fourth PMOS tubes are respectively marked as MP41 and MP42 … … MP4J, the X first NMOS tubes are respectively marked as MN11 and MN12 … … MP1X, and the Y second NMOS tubes are respectively marked as MN21 and MN22 … … MP 2Y.
In the power supply circuit provided by the embodiment of the present invention, because the channel length modulation effect of the transistor in the MOS-type current mirror circuit in the current replica circuit or the base width modulation effect of the transistor in the BJT-type current mirror circuit causes the voltage at the load or the first power supply terminal to change, and the voltage at the node where the current input circuit generates the first reference current and/or the voltage at the node where the current output circuit outputs the second reference current to change, further the voltage difference at the input of the first adjustable resistance circuit and/or the second adjustable resistance circuit is not within the preset range, the control circuit in the first adjustable resistance circuit can adjust the on-resistance of the corresponding resistance circuit according to the voltage difference at the input of the first adjustable resistance circuit, so that the voltage at the node where the current input circuit generates the first reference current is the same as the preset bias voltage, and the control circuit in the second adjustable resistance circuit can adjust the on-resistance of the corresponding resistance circuit according to the voltage difference input by the second adjustable resistance circuit, so that the voltage of the node of the current output circuit outputting the second reference current is the same as the same bias voltage. That is to say, the power supply circuit according to the embodiment of the present invention can make the voltage of the node where the current input circuit generates the first reference current be the same as the voltage of the node where the current output circuit outputs the second reference current, that is, when the current replica circuit is a MOS-type current mirror circuit, the channel length modulation effect in the current replica circuit can be suppressed, and when the current replica circuit is a BJT-type current mirror circuit, the base width modulation effect in the current replica circuit can be suppressed. Furthermore, the second reference current is prevented from being influenced by the load and the power supply voltage for providing power supply for the current copy circuit, so that the current precision of the power supply circuit is improved, and the swing of the output voltage is increased.
In an embodiment, the present invention further provides a power circuit as shown in fig. 8, wherein the power circuit further includes a current-to-voltage circuit. The current-to-voltage circuit is configured to: receiving the second reference current and outputting a voltage proportional to the second reference current.
In one embodiment, the current to voltage circuit converts the second reference current to a voltage output through a zero temperature coefficient resistance.
In another embodiment, the current-to-voltage circuit may further be a resistor network having a logic adjustable resistance function, or a resistor and a resistor network having a specific temperature coefficient, or a circuit structure having a specific equivalent resistance and a specific temperature coefficient, for converting the second reference current into a voltage output.
< electric device >
The embodiment of the utility model provides a still provide an electric equipment, this electric equipment includes any one power supply circuit in the above-mentioned embodiment.
While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.
Claims (13)
1. A power supply circuit, comprising:
the current copying circuit comprises a current input circuit and a current output circuit, wherein the current input circuit is used for generating a first reference current, and the current output circuit is used for copying and outputting a second reference current; wherein the second reference current is proportional to the first reference current;
two adjustable resistance circuits, each adjustable resistance circuit comprising a resistance circuit and a control circuit, the control circuit being arranged to adjust the resistance of the resistance circuit in dependence on an input voltage difference, such that the input voltage difference is within a predetermined range;
the resistance circuit of the first adjustable resistance circuit and the current input circuit are connected in series between a first power supply end and a ground end, and the voltage difference corresponding to the input of the first adjustable resistance circuit is as follows: a voltage difference between a voltage of a node of the current input circuit generating the first reference current and a preset bias voltage;
the resistance circuit of the second adjustable resistance circuit and the current output circuit are connected in series between the first power supply end and the output end of the power supply circuit, and the voltage difference corresponding to the input of the second adjustable resistance circuit is as follows: a voltage difference between a voltage of a node of the current output circuit that outputs the second reference current and the bias voltage.
2. The power supply circuit according to claim 1, further comprising a current sampling circuit, a reference voltage source for supplying a reference voltage, and a first amplifier;
the current sampling circuit is connected in series with the current input circuit and a resistor circuit of the first adjustable resistor circuit, and is configured to collect the first reference current and convert the first reference current into a feedback voltage;
the inverting input end of the first amplifier is connected with the reference voltage, the non-inverting input end of the first amplifier is connected with the feedback voltage, the output end of the first amplifier is connected with the control end of the current input circuit, and the first amplifier is arranged to control the current input circuit to adjust the generated first reference current according to the voltage difference between the reference voltage and the feedback voltage.
3. The power supply circuit according to claim 1, wherein the control circuit is a second amplifier;
the non-inverting input end of the second amplifier is connected with the bias voltage, and the output end of the second amplifier is connected with the control end of the resistance circuit;
in the first adjustable resistance circuit, the inverting input end of the second amplifier is connected with the voltage of a node of the current input circuit, which generates the first reference current;
in the second adjustable resistance circuit, the inverting input terminal of the second amplifier is connected to the voltage of the node of the current output circuit that outputs the second reference current.
4. The power supply circuit of claim 1, wherein the control circuit comprises a first PMOS transistor and a bias current source;
the source electrode of the first PMOS tube is connected with the bias voltage, the drain electrode of the first PMOS tube is respectively connected with the anode of the bias current source and the control end of the resistance circuit, and the cathode of the bias current source is grounded;
in the first adjustable resistance circuit, the grid electrode of the first PMOS tube is connected with the voltage of a node of the current input circuit, which generates the first reference current;
in the second adjustable resistance circuit, the gate of the first PMOS transistor is connected to the voltage of the node of the current output circuit, which outputs the second reference current.
5. The power supply circuit according to claim 2, wherein the resistor circuit is a second PMOS transistor, a gate of the second PMOS transistor being set as a control terminal of the resistor circuit;
in the first adjustable resistance circuit, the source electrode of the second PMOS tube is connected with the node of the current input circuit, which generates the first reference current; the drain electrode of the second PMOS tube is connected with the current sampling circuit;
in the second adjustable resistance circuit, a source of the second PMOS transistor is connected to a node of the current output circuit, where the second reference current is output, and a drain of the second PMOS transistor is used as an output terminal of the power supply circuit.
6. The power supply circuit of claim 1, wherein the adjustable resistance circuit further comprises a bias voltage source that provides the bias voltage, the bias voltage source comprising: a Zener diode, a resistor;
the cathode of the Zener diode is connected with the second power supply end; the anode of the Zener diode is connected with one end of the resistor; the other end of the resistor is grounded; and an output end of the bias voltage source for outputting the bias voltage is led out between the anode of the Zener diode and one end of the resistor.
7. The power supply circuit of claim 1, wherein the bias voltage is provided by the first supply terminal.
8. The power supply circuit of claim 1, wherein the current replica circuit is a cascode current mirror circuit.
9. The power supply circuit according to claim 8, wherein the cascode gate mirror circuit includes K third PMOS transistors, J fourth PMOS transistors;
the source electrodes of the K third PMOS tubes are connected to the first power supply end, the grid electrodes of the K third PMOS tubes are used as the control ends of the current input circuit, and the drain electrodes of the K third PMOS tubes are used as nodes of the current input circuit for generating the first reference current;
the source electrodes of the J fourth PMOS tubes are connected to the first power supply end, the grid electrodes of the J fourth PMOS tubes are connected with the control end of the current input circuit, and the drain electrodes of the J fourth PMOS tubes are used as nodes of the current output circuit for outputting the second reference current;
k-1 logic switches are arranged between the source electrodes of any K-1 third PMOS tubes and the first power supply end, and the K-1 logic switches are respectively arranged to control the connection states of the source electrodes of the third PMOS tubes and the first power supply end according to the on-off states of the logic switches;
j-1 logic switches are arranged between the source electrodes of any J-1 fourth PMOS tubes and the first power supply end, and the J-1 logic switches are respectively arranged to control the connection states of the source electrodes of the fourth PMOS tubes and the first power supply end according to the on-off states of the logic switches;
j and K are integers larger than 1, and the width-to-length ratio of the third PMOS tube to the fourth PMOS tube is the same.
10. The power supply circuit according to claim 8, wherein the cascode gate current mirror circuit includes X first NMOS transistors and Y second NMOS transistors;
the source electrodes of the X first NMOS tubes are grounded, the grid electrodes of the X first NMOS tubes are used as the control ends of the current input circuit, and the drain electrodes of the X first NMOS tubes are used as the nodes of the current input circuit for generating the first reference current;
the source electrodes of the Y second NMOS tubes are grounded, the grid electrodes of the Y second NMOS tubes are connected with the control end of the current input circuit, and the drain electrodes of the Y second NMOS tubes are used as nodes of the current output circuit for outputting the second reference current;
the X-1 logic switches are arranged between the source electrode and the grounding terminal of any X-1 first NMOS tube, and the X-1 logic switches are respectively arranged to control the connection state of the source electrode and the grounding terminal of the first NMOS tube according to the on-off state of the logic switches;
y-1 logic switches are arranged between the source electrode and the grounding terminal of any Y-1 second NMOS tubes, and the Y-1 logic switches are respectively arranged to control the connection state of the source electrode and the grounding terminal of the second NMOS tubes according to the on-off state of the logic switches;
y and X are integers larger than 1, and the width-to-length ratio of the first NMOS tube to the second NMOS tube is the same.
11. The power supply circuit according to any one of claims 1 to 10, wherein the power supply circuit further comprises a current-to-voltage circuit;
the current-to-voltage circuit is configured to: receiving the second reference current and outputting a voltage proportional to the second reference current.
12. The power supply circuit of claim 11, wherein the current to voltage circuit converts the second reference current to a voltage output through a zero temperature coefficient resistance.
13. An electrical consumer, characterized in that the electrical consumer comprises a power supply circuit according to any one of claims 1-12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920747871.8U CN209946731U (en) | 2019-05-22 | 2019-05-22 | Power supply circuit and electric equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920747871.8U CN209946731U (en) | 2019-05-22 | 2019-05-22 | Power supply circuit and electric equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209946731U true CN209946731U (en) | 2020-01-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920747871.8U Active CN209946731U (en) | 2019-05-22 | 2019-05-22 | Power supply circuit and electric equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209946731U (en) |
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2019
- 2019-05-22 CN CN201920747871.8U patent/CN209946731U/en active Active
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