CN209790000U - Surgical system based on electrode recognition - Google Patents
Surgical system based on electrode recognition Download PDFInfo
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- CN209790000U CN209790000U CN201920027443.8U CN201920027443U CN209790000U CN 209790000 U CN209790000 U CN 209790000U CN 201920027443 U CN201920027443 U CN 201920027443U CN 209790000 U CN209790000 U CN 209790000U
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Abstract
The utility model discloses an operation system based on electrode identification, which comprises a host, a connector and an electrode, wherein the electrode comprises an electrode tip and a storage chip which are not directly electrically connected and are respectively isolated from the ground; the electrode tip and the storage chip are respectively connected with the host through the connector; the host reads the data of the electrode tip prestored in the memory chip, so that the relevant information of the electrode tip is identified. The utility model discloses a separately set up the electrode tip with the memory chip of storage electrode tip data, make not have direct electrical connection between electrode tip and the memory chip, and keep apart to ground separately to can guarantee that electrode and memory chip can not influence each other on the problem of keeping apart to ground, improve the security performance.
Description
Technical Field
The utility model relates to an electricity field, concretely relates to operation system based on electrode discernment.
background
The operation electrode is an electric surgical instrument for replacing a mechanical scalpel to cut tissues, when the electric surgical instrument works, the operation electrode is connected with a high-frequency power signal generating device of a system host, the high-frequency power signal generating device controls the operation electrode by applying a high-frequency signal to the operation electrode, specifically, a controller of the system host sends a signal to the high-frequency power signal generating device, the high-frequency power signal generating device controls the operation electrode according to the signal sent by the controller, and under the control of the high-frequency power signal generating device, the high-frequency high-voltage current generated by the tip of an effective electrode heats the tissues when contacting with the body of an operation object, so that the separation and solidification of the body tissues are realized, and the purposes of cutting and hemostasis are achieved. A high-frequency operation system aims at different operation objects or operations with different purposes, and needs to be matched with electrodes with different models, the models of the electrodes are different, and needed high-frequency power signals are different, so that the operation system needs to identify the models of the electrodes before the operation, and then the operation electrodes are accurately controlled according to related information of the electrodes.
In the existing operation electrode system, an electrode tip of an electrode is directly connected with a storage chip of a storage electrode tip model, once the ground isolation of the storage chip is in trouble, the ground isolation of the electrode tip is in trouble, and the electrode tip is in direct contact with an operation object, so that the structure has potential safety hazard.
SUMMERY OF THE UTILITY MODEL
In view of this, the present application provides an electrode recognition-based surgical system, which solves the problem of potential safety hazard caused by the direct connection between a memory chip and an electrode head in the prior art. This application sets up through separately the storage chip with electrode tip and storage electrode tip data, makes not have direct electrical connection between electrode tip and the storage chip, and keeps apart to ground separately to can guarantee that electrode and storage chip can not influence each other on the problem of keeping apart to ground, improve the security performance. The scheme is realized by the following technical means:
The surgical system based on the electrode identification comprises a host machine, a connector and an electrode, wherein the electrode comprises an electrode head and a memory chip which are not directly electrically connected and are respectively isolated to the ground; the electrode tip and the storage chip are respectively connected with the host through the connector; the host reads the data of the electrode tip prestored in the memory chip, so that the relevant information of the electrode tip is identified.
Further, the memory chip is a serial data communication memory chip.
Furthermore, the host comprises an interface isolation circuit, a power isolation circuit and a high-frequency power signal generation device, wherein the interface isolation circuit and the power isolation circuit are connected with each other; the interface isolation circuit, the power isolation circuit and the high-frequency power signal generating device are simultaneously connected with the connector; the interface isolation circuit and the high-frequency power signal generating device are respectively connected to the controller I/O port of the host.
Further, memory chip is two line bus memory chips of four-wire port, two line bus memory chips of four-wire port include data transmission line port, synchronous clock signal line port, power cord port and ground wire port, data transmission line port and synchronous clock signal line port pass through respectively the connector with interface isolation circuit connects, power cord port and ground wire port pass through respectively the connector with power isolation circuit connects.
Further, the interface isolation circuit comprises an isolation chip with the model of Si8602, a first pin and a seventh pin of the isolation chip are grounded, the third pin of the isolation chip is connected with a first external power supply, the fifth pin and the sixth pin of the isolation chip are respectively connected with the first external power supply through a first resistor and a second resistor, the fifth pin and the sixth pin of the isolation chip are respectively used as a data end and a clock signal end to be connected with the controller I/O port of the host, the twelfth pin and the eleventh pin of the isolation chip are respectively used as a data terminal and a clock signal terminal to be connected with the memory chip through the connector, the twelfth pin and the eleventh pin of the isolation chip are respectively connected with the power output end of the power isolation circuit through a fifth resistor and a fourth resistor, and the ninth pin and the sixteenth pin of the isolation chip are both connected with an isolation grounding end of the power isolation circuit.
Furthermore, a third pin of the isolation chip is grounded through a first capacitor, and one end of the fifth resistor, which is connected with the power isolation circuit, is grounded through a second capacitor.
Further, a fourteenth pin of the isolation chip is connected to the power output terminal of the power isolation circuit through a third resistor.
Furthermore, an eleventh pin of the isolation chip is connected with an isolation ground terminal of the power isolation circuit through a first diode and a third capacitor which are connected in parallel, and a twelfth pin of the isolation chip is connected with the isolation ground terminal of the power isolation circuit through a second diode and a fourth capacitor which are connected in parallel.
Furthermore, the power isolation circuit is a DC-DC power isolation circuit, the DC-DC power isolation circuit includes a power input terminal, a power output terminal, a ground terminal and an isolation ground terminal, the power input terminal is connected to a second external power source, the isolation ground terminal is a ground terminal electrically isolated from the ground terminal, and the power output terminal and the isolation ground terminal are both connected to the memory chip through the connector.
Compared with the prior art, the beneficial effects of the utility model are as follows:
1. The utility model provides an operation system based on electrode discernment separately sets up through the memory chip with electrode tip and storage electrode tip information, makes not have direct electrical connection between electrode tip and the memory chip, and keeps apart to ground separately to can guarantee that electrode and memory chip can not influence each other on the problem of keeping apart to ground, improve the security performance.
2. The utility model discloses an adopt above-mentioned scheme to divide into the entire system M part (mainly constitute by interface buffer circuit, power buffer circuit and memory chip part) and N part (mainly constitute by high frequency power signal generation device and electrode head part), because M part and N part do not have lug connection together, this embodiment can promote the motor head to keep apart with the electrode head to host computer input (220V electric wire netting) keep apart with ground.
3. The utility model discloses to keep apart chip U1's fourteenth pin through third resistance R3 with power isolation circuit's power output end connects, can effectively restrain the latch and vibrate, avoids keeping apart the chip and vibrate and burn out because the latch.
4. The utility model discloses to keep apart chip U1's eleventh pin through parallelly connected first diode D1 and third electric capacity C3 with power isolator circuit's isolation earthing terminal is connected, keep apart chip U1's twelfth pin through parallelly connected second diode D2 and fourth electric capacity C4 with power isolator circuit's isolation earthing terminal is connected, can effectively restrain the interference.
Drawings
Fig. 1 is a block diagram illustrating an electrode recognition based surgical system configuration according to an exemplary embodiment.
fig. 2 is a schematic diagram illustrating a connector structure according to an exemplary embodiment.
Fig. 3 is a schematic diagram illustrating an interface isolation circuit according to an exemplary embodiment.
Fig. 4 is a schematic diagram illustrating a power isolation circuit according to an exemplary embodiment.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.
Examples
As shown in fig. 1, the present embodiment provides an electrode recognition-based surgical system, including a host, a connector, and an electrode, wherein the electrode includes an electrode head and a memory chip, which are not directly electrically connected and are respectively isolated from the ground; the electrode tip and the storage chip are respectively connected with the host through the connector; the host reads the data of the electrode tip prestored in the memory chip, so that the relevant information of the electrode tip is identified.
In this embodiment, because there is not direct electrical connection and each to ground isolation between electrode tip and the memory chip, in this embodiment during operation, the control parameter that the host computer accurately controlled and exerted on the electrode tip through reading the electrode tip data (including the electrode tip model) that prestores in the memory chip, in the whole process, through prestoring electrode tip information in the memory chip, and make electrode tip and memory chip do not have direct electrical connection, consequently, the earthing terminal of electrode tip and the earthing terminal of memory chip also do not have electrical connection, electrode tip and memory chip can not influence each other on the ground problem, the electrode tip is whether to the isolation of ground or to the isolation of host computer all can improve greatly, thereby the operation security performance of this embodiment has been improved. Here, the term isolated from ground means isolated ground, which is ground electrically isolated from direct ground.
Preferably, the host in this embodiment may include an interface isolation circuit, a power isolation circuit, and a high-frequency power signal generation device, where the interface isolation circuit and the power isolation circuit are connected to each other; the interface isolation circuit, the power isolation circuit and the high-frequency power signal generating device are simultaneously connected with the connector; the interface isolation circuit and the high-frequency power signal generating device are respectively connected to the controller I/O port of the host.
Here, the I/O port of the host controller may include a plurality of interfaces, and may be connected according to the functional purpose of the interfaces when connected. In addition, when the embodiment works, the host controller reads the data of the electrode tip in the memory chip through the interface isolation circuit and sets the operation parameters of the high-frequency power signal generation device according to the data of the electrode tip, so that the electrode tip is accurately controlled.
It should be noted that, as shown in fig. 1, the present embodiment is divided into an M part (mainly composed of an interface isolation circuit, a power isolation circuit, and a memory chip part) and an N part (mainly composed of a high-frequency power signal generation device and an electrode head part), and since the M part and the N part are not directly connected together, the present embodiment can improve the isolation of the motor head to the ground and the isolation of the electrode head to the host input (220V power grid):
(1) Electrode head-to-ground isolation: if M and N parts are directly connected, the electrode head-to-ground isolation is weakened by the incorporation of M part;
(2) Isolation of electrode head to host input (220V grid): if M and N parts are directly connected, the isolation of the electrode head to the host input (220V grid) is weakened by the incorporation of M part.
In the embodiment, as shown in fig. 2, the connector in the embodiment may include an a terminal and a B terminal; the A end of the connector is provided with an A1 connection channel unit, an A2 connection channel unit and an A3 connection channel unit, and the B end of the connector is provided with a B1 connection channel unit, a B2 connection channel unit and a B3 connection channel unit; the interface isolation circuit, the power isolation circuit and the high-frequency power signal generation device are respectively connected with the A1 connection channel unit, the A2 connection channel unit and the A3 connection channel unit of the A end, the memory chip is simultaneously connected with the B1 connection channel unit and the B2 connection channel unit of the B end, and the electrode head is connected with the B3 connection channel unit of the B end; wherein, each connecting channel in the A1 connecting channel unit, the A2 connecting channel unit and the A3 connecting channel unit of the A end is matched with each connecting channel in the B1 connecting channel unit, the B2 connecting channel unit and the B3 connecting channel unit of the B end respectively.
It should be noted that, the a end of the connector in this embodiment may be a socket and is mounted on the panel of the host; the end B can be a plug, the memory chip is arranged in the plug, and the plug is connected with the electrode head through a cable. The a terminal of the connector in this embodiment may include a plurality of connection channel units, the B terminal includes the same number of connection channel units as the a terminal, each connection channel unit may include one or more connection channels independent of each other, in short, the a terminal may include a plurality of connection channels, and the B terminal may include the same number of connection channels as the a terminal, and the embodiment describes the a terminal connection channels corresponding to the interface isolation circuit, the power isolation circuit, and the high-frequency power signal generation device as the a1 connection channel unit, the a2 connection channel unit, and the A3 connection channel unit, correspondingly, the B terminal also comprises a corresponding B1 connecting channel unit, a B2 connecting channel unit and a B3 connecting channel unit, in addition, the connection channel unit, the terminal a of which is connected to the high-frequency power signal generating device, can be regarded as the output terminal of the high-frequency power signal generating device. The electrode in this embodiment may be a bipolar electrode, the IO terminal and the ground return terminal of the electrode are respectively connected to the first connection channel and the second connection channel connected to the B3 connection channel unit at the B terminal of the connector, the output terminal of the high-frequency power signal generator is connected to the first connection channel of the A3 connection channel unit at the a terminal of the connector, and the second connection channel of the A3 connection channel unit at the a terminal of the connector and the second connection channel of the B3 connection channel unit at the B terminal of the connector are grounded terminals.
Preferably, in order to reduce the number of connections, the memory chip in this embodiment may be a memory chip for serial data communication, specifically, the memory chip may be a four-wire port two-wire bus memory chip, or may also be a two-wire port one-wire bus memory chip, and if the number of connections is not limited, the memory chip in this embodiment may also be a memory chip for parallel data communication.
To better explain the present embodiment, when the memory chip is a two-wire bus memory chip having a four-wire port, the four-wire port includes a data transmission line port, a synchronous clock line port, a power line port and a ground line port, the data transmission line port and the synchronous clock line port are respectively connected to the first connection channel and the second connection channel in the B1 connection channel unit of the B-end, and the power line port and the ground line port are respectively connected to the first connection channel and the second connection channel of the B2 connection channel unit of the B-end.
It should be noted here that, the memory chip in this embodiment is provided with a synchronous clock signal line port, which can constantly keep clock synchronization with the system host, enhance the anti-interference capability, separately set the data transmission line port and the power line port, and ensure the smoothness of data transmission while enhancing the anti-interference capability, thereby improving the working efficiency and stability of the system.
Preferably, as shown in fig. 3, the interface isolation circuit includes an isolation chip U1 with a model of Si8602, a first pin and a seventh pin of the isolation chip U1 are grounded, a third pin of the isolation chip U1 is connected to a first external power source V1, a fifth pin and a sixth pin of the isolation chip U1 are respectively connected to the first external power source V1 through a first resistor R1 and a second resistor R2, a fifth pin and a sixth pin of the isolation chip U1 are respectively connected to a controller I/O port of a host as a data terminal and a clock signal terminal, a twelfth pin and an eleventh pin of the isolation chip U1 are respectively connected to a first connection channel and a second connection channel of the a1 connection channel unit of the a terminal as a data terminal and a clock signal terminal, a twelfth pin and an eleventh pin of the isolation chip U1 are respectively connected to a power output terminal of the power isolation circuit through a fifth resistor R5 and a fourth resistor R4, and the ninth pin and the sixteenth pin of the isolation chip U1 are both connected with an isolation grounding end of the power isolation circuit.
it should be noted here that the interface isolation circuit in this embodiment may be formed by other isolation chips having the same function and corresponding peripheral circuits, and is not limited to the isolation chip with the model number Si 8602.
Preferably, in this embodiment, the third pin of the isolation chip U1 may be grounded through a first capacitor C1, and one end of the fifth resistor R5 connected to the power isolation circuit may be grounded through a second capacitor C2. The first capacitor C1 and the second capacitor C2 are provided for the purpose of power decoupling in the present embodiment.
Preferably, in this embodiment, the fourteenth pin of the isolation chip U1 may be connected to the power output terminal of the power isolation circuit through a third resistor R3. The third resistor R3 provided in this embodiment can effectively suppress latch oscillation, thereby preventing the isolated chip from being burned out due to latch oscillation.
Preferably, the eleventh pin of the isolation chip U1 is connected to the isolation ground of the power isolation circuit through a first diode D1 and a third capacitor C3 connected in parallel, and the twelfth pin of the isolation chip U1 is connected to the isolation ground of the power isolation circuit through a second diode D2 and a fourth capacitor C4 connected in parallel. In this embodiment, the anodes of the first diode D1 and the second diode D2 are connected to the isolation ground of the power isolation circuit, and since interference is easily generated when there is an output from the electrodes, the first diode D1 and the second diode D2 provided in this embodiment both serve as protection diodes, and the third capacitor C3 and the fourth capacitor C4 provided in this embodiment can perform noise filtering.
Preferably, the power isolation circuit is a DC-DC power isolation circuit, and provides an isolated floating power supply for the output sides of the memory chip and the isolation chip, the DC-DC power isolation circuit includes a power input terminal, a power output terminal, a ground terminal and an isolation ground terminal, the power input terminal is connected to a second external power supply V2, the isolation ground terminal is an electrically isolated ground terminal relative to the ground terminal, the isolation ground terminal is connected to the second connection channel of the a2 connection unit at the a terminal of the connector, and the power output terminal is connected to the first connection channel of the a2 connection channel unit at the a terminal of the connector.
As shown in fig. 4, in the present embodiment, the power isolation circuit may include a DC-DC isolated power chip U2 of model H0505S-1WR2, the second pin of the isolation power chip U2 is grounded, the second pin and the first pin of the isolation power chip U2 are grounded through a fifth capacitor C5 and a sixth capacitor C6 which are connected in parallel, a first pin of the isolation power chip U2 is connected with a second external power supply V2 as a power input end, the seventh pin of the isolated power chip U2 is connected to one end of the seventh capacitor C7 and the eighth capacitor C8 at the same time, the other ends of the seventh capacitor C7 and the eighth capacitor C8 are shorted with each other to serve as an isolated ground of the second pin ground of the isolated power chip U2, the fifth pin of the isolated power chip U2 is connected to one end of the seventh capacitor C7 connected to the eighth capacitor C8, and the seventh pin of the isolated power chip U2 serves as a power output terminal.
Preferably, the isolation voltage of the interface isolation circuit of the present embodiment may be 5000VRMS, and the isolation voltage of the power isolation circuit may be 6000 VDC.
The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various modifications and enhancements can be made without departing from the spirit and scope of the invention, and such modifications and enhancements are intended to be within the scope of the invention.
Claims (9)
1. The electrode identification-based surgical system comprises a host machine, a connector and an electrode, and is characterized in that the electrode comprises an electrode head and a memory chip which are not directly electrically connected and are respectively isolated to the ground; the electrode tip and the storage chip are respectively connected with the host through the connector; the host reads the data of the electrode tip prestored in the memory chip, so that the relevant information of the electrode tip is identified.
2. The electrode identification based surgical system of claim 1, wherein the memory chip is a serial data communication memory chip.
3. The electrode recognition-based surgical system according to claim 1, wherein the host includes an interface isolation circuit, a power isolation circuit and a high-frequency power signal generation device, the interface isolation circuit and the power isolation circuit being connected to each other; the interface isolation circuit, the power isolation circuit and the high-frequency power signal generating device are simultaneously connected with the connector; the interface isolation circuit and the high-frequency power signal generating device are respectively connected to the controller I/O port of the host.
4. The electrode identification based surgical system according to claim 3, wherein the memory chip is a four-wire port two-wire bus memory chip, the four-wire port two-wire bus memory chip includes a data transmission line port, a synchronous clock line port, a power line port and a ground line port, the data transmission line port and the synchronous clock line port are respectively connected with the interface isolation circuit through the connectors, and the power line port and the ground line port are respectively connected with the power isolation circuit through the connectors.
5. The electrode recognition-based surgical system according to claim 3, wherein the interface isolation circuit comprises an isolation chip (U1) with a model of Si8602, the first pin and the seventh pin of the isolation chip (U1) are grounded, the third pin of the isolation chip (U1) is connected with a first external power supply (V1), the fifth pin and the sixth pin of the isolation chip (U1) are respectively connected with the first external power supply (V1) through a first resistor (R1) and a second resistor (R2), the fifth pin and the sixth pin of the isolation chip (U1) are respectively connected with a controller I/O port of the host computer as a data terminal and a clock signal terminal, the twelfth pin and the eleventh pin of the isolation chip (U1) are respectively connected with the memory chip through the connector as a data terminal and a clock signal terminal, and the twelfth pin and the eleventh pin of the isolation chip (U1) are respectively connected with a fifth resistor (R5) and an eleventh pin (R3552) through the connector, respectively The four resistors (R4) are connected with the power supply output end of the power supply isolation circuit, and the ninth pin and the sixteenth pin of the isolation chip (U1) are both connected with the isolation grounding end of the power supply isolation circuit.
6. The electrode recognition based surgical system of claim 5, wherein the third pin of the isolation chip (U1) is grounded through a first capacitor (C1), and the fifth resistor (R5) is connected to one end of the power isolation circuit and grounded through a second capacitor (C2).
7. The electrode recognition based surgical system of claim 5, wherein a fourteenth pin of the isolation chip (U1) is connected to a power output of the power isolation circuit through a third resistor (R3).
8. The electrode recognition based surgical system according to claim 5, wherein the eleventh pin of the isolation chip (U1) is connected to the isolated ground of the power isolation circuit through a first diode (D1) and a third capacitor (C3) connected in parallel, and the twelfth pin of the isolation chip (U1) is connected to the isolated ground of the power isolation circuit through a second diode (D2) and a fourth capacitor (C4) connected in parallel.
9. The electrode identification based surgical system according to any one of claims 3-8, wherein the power isolation circuit is a DC-DC power isolation circuit, the DC-DC power isolation circuit comprises a power input terminal, a power output terminal, a ground terminal and an isolation ground terminal, the power input terminal is connected with a second external power supply (V2), the isolation ground terminal is a ground terminal electrically isolated from the ground terminal, and the power output terminal and the isolation ground terminal are both connected with the memory chip through the connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920027443.8U CN209790000U (en) | 2019-01-08 | 2019-01-08 | Surgical system based on electrode recognition |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920027443.8U CN209790000U (en) | 2019-01-08 | 2019-01-08 | Surgical system based on electrode recognition |
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| CN209790000U true CN209790000U (en) | 2019-12-17 |
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| CN201920027443.8U Active CN209790000U (en) | 2019-01-08 | 2019-01-08 | Surgical system based on electrode recognition |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112535517A (en) * | 2020-11-12 | 2021-03-23 | 嘉善飞阔医疗科技有限公司 | Two-wire system ultrasonic scalpel system with multiple control inputs |
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2019
- 2019-01-08 CN CN201920027443.8U patent/CN209790000U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112535517A (en) * | 2020-11-12 | 2021-03-23 | 嘉善飞阔医疗科技有限公司 | Two-wire system ultrasonic scalpel system with multiple control inputs |
| CN112535517B (en) * | 2020-11-12 | 2023-09-08 | 嘉善飞阔医疗科技有限公司 | Two-wire ultrasonic scalpel system with multiple control inputs |
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