CN209785375U - general operational amplification experimental circuit - Google Patents
general operational amplification experimental circuit Download PDFInfo
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- CN209785375U CN209785375U CN201821787424.7U CN201821787424U CN209785375U CN 209785375 U CN209785375 U CN 209785375U CN 201821787424 U CN201821787424 U CN 201821787424U CN 209785375 U CN209785375 U CN 209785375U
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Abstract
The utility model relates to a general operational amplification experimental circuit. The intelligent amplifier comprises input ends V1-V4, resistors R1-R7, capacitors C1-C5, switches S1-S11, an operational amplifier U1A and an output end VOUT, seven most commonly used amplifying circuits can be realized on the same operational amplifier by selecting the on-off of the switches, a user can select corresponding circuits according to different application targets, and the intelligent amplifier is convenient and quick, can better save data and is high in flexibility.
Description
Technical Field
The utility model relates to an experiment teaching equipment especially relates to a general operational amplification experimental circuit.
Background
The AC-DC reverse amplifying circuit, the AC-DC same-direction amplifying circuit, the differential amplifying circuit, the reverse-phase summation operation circuit, the in-phase summation operation circuit, the integral operation circuit and the differential operation circuit are common teaching circuits in the existing operational amplification experimental circuit, and currently, for the convenience of teaching, each circuit is provided with an independent circuit board so as to directly correspond to the content of teaching materials. However, this is wasteful of experimental materials, and students cannot clearly analyze the differences of the respective circuits during learning.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, an object of the utility model is to provide a general operational amplification experimental circuit has realized seven kinds of amplifier circuits most commonly used on same piece fortune is put, and the user can select corresponding circuit according to the different application target of oneself, convenient and fast, saving data that can be better, and the flexibility is high.
in order to achieve the above purpose, the utility model adopts the following technical scheme:
A general operational amplification experimental circuit is characterized by comprising input ends V1-V4, resistors R1-R7, capacitors C1-C5, switches S1-S11, an operational amplifier U1A and an output end VOUT; wherein, the input terminals V1-V4 refer to input terminals V1, V2, V3 and V4, the resistors R1-R7 refer to resistors R1, R2, R3, R4, R5, R6 and R7, the capacitors C1-C5 refer to capacitors C1, C2, C3, C4 and C5, and the switches S1-S11 refer to switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10 and S11; signals are input from input terminals V1-V4 and output from an output terminal VOUT.
The capacitor C1 is connected in parallel with the switch S2, the input end V1 is connected in series with one end of the capacitor C1 and one end of the switch S2, the resistor R2 is connected in series with the other end of the capacitor C1 and the switch S2, when the S2 is disconnected, the input end V1 is connected to the resistor R2 through the capacitor C1, after the S2 is closed, the input end V1 is directly connected to the resistor R2, and the other end of the R2 is connected to the pin 1 of the operational amplifier U1A through the switch S1;
the capacitor C2 is connected in parallel with the switch S5, the input end V2 is connected in series with one end of the capacitor C2 and one end of the switch S5, the resistor R3 is connected in series with the other end of the capacitor C2 and the switch S5, when the S3 is disconnected, the input end V2 is connected to the resistor R3 through the capacitor C2, after the S3 is closed, the input end V2 is directly connected to the resistor R3, and the other end of the R3 is connected to the pin 1 of the operational amplifier U1A through the switch S4;
The capacitor C3 is connected in parallel with the switch S7, the input end V3 is connected in series with one end of the capacitor C3 and one end of the switch S7, the resistor R4 is connected in series with the other end of the capacitor C3 and the switch S7, when the S7 is disconnected, the input end V3 is connected to the resistor R4 through the capacitor C3, after the S7 is closed, the input end V3 is directly connected to the resistor R4, and the other end of the R4 is connected to the 2 pin of the operational amplifier U1A through the switch S6;
the capacitor C5 is connected in parallel with the switch S9, the input end V4 is connected in series with one end of the capacitor C5 and one end of the switch S9, the resistor R5 is connected in series with the other end of the capacitor C5 and the switch S9, when the S9 is disconnected, the input end V4 is connected to the resistor R5 through the capacitor C5, after the S9 is closed, the input end V4 is directly connected to the resistor R5, and the other end of the R4 is connected to the 2 pin of the operational amplifier U1A through the switch S6;
The pin 3 of the operational amplifier U1A is also connected with one end of a switch S3, the other end of S3 is connected with one end of a resistor R1, and the other end of the resistor R1 is grounded; the 2 pin of the operational amplifier U1A is also connected with one end of a switch S11, the other end of the switch S11 is connected with one end of a resistor R7, and the other end of the resistor R7 is grounded; the 2 pin of the operational amplifier U1A is also connected with one end of a resistor R6, a capacitor C4 is connected with a switch S10 in parallel, the other end of the resistor R6 is connected with one end of a capacitor C4 and one end of a switch S10 in series, the other ends of the capacitor C4 and the switch S10 are connected with the 1 pin of the operational amplifier U1A, and the 1 pin of the operational amplifier U1A is connected with an output terminal VOUT.
The utility model discloses a general operational amplification experimental circuit, S3, S8, S9, S10 are closed, and other S1, S2, S4, S5, S6, S7, S11 break off can realize the reverse amplification experimental circuit of alternating current-direct current; s3, S8 and S10 are closed, and the rest of S1, S2, S4, S5, S6, S7, S9 and S11 are opened to realize an alternating current reverse amplification experimental circuit; s4, S5, S10 and S11 are closed, and the rest of S1, S2, S3, S6, S7, S8 and S9 are disconnected to realize an AC-DC equidirectional amplification experimental circuit; s4, S10 and S11 are closed, and the rest of S1, S2, S3, S5, S6, S7, S8 and S9 are opened to realize an alternating current equidirectional amplification experimental circuit; s3, S4, S5, S8, S9 and S10 are closed, and the rest S1, S2, S6, S7 and S11 are opened to realize a differential amplification experimental circuit; s3, S6, S7, S8, S9 and S10 are closed, and the rest S1, S2 and S11 are opened to realize an inverse summation amplification experimental circuit; s1, S2, S3, S4, S5, S10 and S11 are closed, and the rest S6, S7, S8 and S9 are opened to realize a homodromous summing amplification experimental circuit; s3, S8 and S9 are closed, S1, S2, S4, S5, S6, S7, S10 and S11 are opened, so that an integration experiment circuit can be realized; s3, S8 and S10 are closed, and S1, S2, S4, S5, S6, S7, S9 and S11 are opened to realize a differential experiment circuit. As mentioned above, the present invention can realize the above different circuits on one board by selecting the on or off of the switches S1-S11, so that the material prepared for teaching is less, the data can be saved better, and the flexibility is high. And by the arrangement, visual contrast among the circuits can be provided for a user.
Drawings
Fig. 1 is a schematic structural diagram of the present invention.
fig. 2 is a circuit diagram of an ac/dc reverse amplifying circuit combined by the circuit of the present invention.
fig. 3 is a circuit diagram of an ac reverse amplifier circuit combined by the circuit of the present invention.
Fig. 4 is a circuit diagram of the ac/dc forward amplifying circuit combined by the circuit of the present invention.
Fig. 5 is a circuit diagram of an ac forward amplifier circuit combined by the circuit of the present invention.
Fig. 6 is a circuit diagram of a differential amplifier circuit combined with the circuit of the present invention.
Fig. 7 is a circuit diagram of the inverse summation operation combined by the circuit of the present invention.
fig. 8 is a circuit diagram of the in-phase summation operation combined by the circuit of the present invention.
Fig. 9 is a circuit diagram of an integral operation circuit combined by the circuit of the present invention.
Fig. 10 is a differential operation circuit diagram combined with the circuit of the present invention.
Detailed Description
Preferred embodiments of this patent are described in further detail below with reference to the accompanying drawings.
As shown in FIG. 1, a general operational amplifier experimental circuit comprises input terminals V1-V4, resistors R1-R7, capacitors C1-C5, switches S1-S11, an operational amplifier U1A and an output terminal VOUT; the input ends V1-V4 refer to input ends V1, V2, V3 and V4, the resistors R1-R7 refer to resistors R1, R2, R3, R4, R5, R6 and R7, the capacitors C1-C5 refer to capacitors C1, C2, C3, C4 and C5, and the switches S1-S11 refer to switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10 and S11.
The capacitor C1 is connected in parallel with the switch S2, the input end V1 is connected in series with one end of the capacitor C1 and one end of the switch S2, the resistor R2 is connected in series with the other end of the capacitor C1 and the switch S2, when the S2 is disconnected, the input end V1 is connected to the resistor R2 through the capacitor C1, after the S2 is closed, the input end V1 is directly connected to the resistor R2, and the other end of the R2 is connected to the pin 1 of the operational amplifier U1A through the switch S1;
The capacitor C2 is connected in parallel with the switch S5, the input end V2 is connected in series with one end of the capacitor C2 and one end of the switch S5, the resistor R3 is connected in series with the other end of the capacitor C2 and the switch S5, when the S3 is disconnected, the input end V2 is connected to the resistor R3 through the capacitor C2, after the S3 is closed, the input end V2 is directly connected to the resistor R3, and the other end of the R3 is connected to the pin 1 of the operational amplifier U1A through the switch S4;
the capacitor C3 is connected in parallel with the switch S7, the input end V3 is connected in series with one end of the capacitor C3 and one end of the switch S7, the resistor R4 is connected in series with the other end of the capacitor C3 and the switch S7, when the S7 is disconnected, the input end V3 is connected to the resistor R4 through the capacitor C3, after the S7 is closed, the input end V3 is directly connected to the resistor R4, and the other end of the R4 is connected to the 2 pin of the operational amplifier U1A through the switch S6;
The capacitor C5 is connected in parallel with the switch S9, the input end V4 is connected in series with one end of the capacitor C5 and one end of the switch S9, the resistor R5 is connected in series with the other end of the capacitor C5 and the switch S9, when the S9 is disconnected, the input end V4 is connected to the resistor R5 through the capacitor C5, after the S9 is closed, the input end V4 is directly connected to the resistor R5, and the other end of the R4 is connected to the 2 pin of the operational amplifier U1A through the switch S6;
The pin 3 of the operational amplifier U1A is also connected with one end of a switch S3, the other end of S3 is connected with one end of a resistor R1, and the other end of the resistor R1 is grounded; the 2 pin of the operational amplifier U1A is also connected with one end of a switch S11, the other end of the switch S11 is connected with one end of a resistor R7, and the other end of the resistor R7 is grounded; the 2 pin of the operational amplifier U1A is also connected with one end of a resistor R6, a capacitor C4 is connected with a switch S10 in parallel, the other end of the resistor R6 is connected with one end of a capacitor C4 and one end of a switch S10 in series, the other ends of the capacitor C4 and the switch S10 are connected with the 1 pin of the operational amplifier U1A, and the 1 pin of the operational amplifier U1A is connected with an output terminal VOUT.
as shown in FIG. 2, the AC/DC reverse amplification experimental circuit can be realized by closing S3, S8, S9 and S10 and opening the rest of S1, S2, S4, S5, S6, S7 and S11. The working principle of the device is that an input signal V4 is connected with one end of C5, the other end of C5 is connected with R5, one end of C5 connected with V4 is connected with one end of S9, the other end of S9 is connected with the end of C5 intersected with R5, the other end of R5 is connected with S8, the other end of S8 is connected with a pin 2 of an operational amplifier U1A, one end of R6 of the pin 2 is connected with the other end of R6 is connected with C4, the other end of C4 is connected with an end of S10, the other end of C4 is connected with a pin 1 of an operational amplifier U1A, and the other end of S10 is connected with a. The pin 1 of U1A is connected to one end of S3, the other end of S3 is connected to R1, and the other end of R1 is grounded. The circuit is a typical AC-DC reverse amplifying circuit.
As shown in fig. 3, S3, S8, S10 are closed, and the rest of S1, S2, S4, S5, S6, S7, S9, S11 are opened to realize an alternating current reverse amplification experimental circuit; the working principle of the circuit is that an input signal V4 is connected with one end of C5, the other end of C5 is connected with R5, the other end of R5 is connected with S8, the other end of S8 is connected with a pin 2 of an operational amplifier U1A, one end of R6 of the pin 2 is connected with the other end of R6 is connected with C4, and is simultaneously connected with one end of S10, the other end of C4 is connected with a pin 1 of an operational amplifier U1A, and the other end of S10 is connected with a pin 1 of U1A. The pin 1 of U1A is connected to one end of S3, the other end of S3 is connected to R1, and the other end of R1 is grounded. This circuit is a typical dc inverting amplifier circuit.
as shown in FIG. 4, S4, S5, S10 and S11 are closed, and the rest of S1, S2, S3, S6, S7, S8 and S9 are opened, so that an alternating current and direct current equidirectional amplification experimental circuit can be realized. The working principle of the amplifier is that an input signal V2 is connected with one end of a C2, the other end of the C2 is connected with an R3, meanwhile, one end of the C2 connected with a V2 is connected with one end of an S5, the other end of the S5 is connected with one end of a C2 intersected with an R3, the other end of the R3 is connected with an S4, and the other end of the S4 is connected with 3 pins of an operational amplifier U1A. The 2 pin of the operational amplifier U1A is connected with one end of the S11, the other end of the S11 is connected with the R7, the other end of the R7 is grounded, one end of the R6 and the other end of the R6 of the 2 pin are connected with the C4 and the S10, the other end of the C4 is connected with the 1 pin of the operational amplifier U1A, and the other end of the S10 is connected with the 1 pin of the U1A. The circuit is a typical AC-DC equidirectional amplifying circuit.
As shown in fig. 5, S4, S10, S11 are closed, and the remaining S1, S2, S3, S5, S6, S7, S8, S9 are opened to realize an ac equidirectional amplification experimental circuit. The working principle is that an input signal V2 is connected with one end of a C2, the other end of the C2 is connected with an R3, the other end of the R3 is connected with an S4, and the other end of the S4 is connected with a pin 3 of an operational amplifier U1A. The 2 pin of the operational amplifier U1A is connected with one end of the S11, the other end of the S11 is connected with the R7, the other end of the R7 is grounded, one end of the R6 and the other end of the R6 of the 2 pin are connected with the C4 and the S10, the other end of the C4 is connected with the 1 pin of the operational amplifier U1A, and the other end of the S10 is connected with the 1 pin of the U1A. The circuit is a typical DC equidirectional amplifying circuit.
As shown in FIG. 6, S3, S4, S5, S8, S9 and S10 are closed, and the rest of S1, S2, S6, S7 and S11 are opened to realize a differential amplification experimental circuit, wherein the working principle of the differential amplification experimental circuit is that an input signal V2 is connected with one end of C2, the other end of C2 is connected with R3, one end of C2 connected with V2 is connected with one end of S5, the other end of S5 is connected with the end where C2 and R3 intersect, the other end of R3 is connected with S4, and the other end of S4 is connected with 3 pins of U1A. The 3 pin of U1A is connected to one end of S3, the other end of S3 is connected to R1, and the other end of R1 is grounded. The input signal V4 is connected with one end of C5, the other end of C5 is connected with R5, one end of C5 connected with V4 is connected with one end of S9, the other end of S9 is connected with the end where C5 intersects with R5, the other end of R5 is connected with S8, the other end of S8 is connected with 2 pins of operational amplifier U1A, one end of R6 of 2 pins, the other end of R6 is connected with C4, the other end of S10 is connected with the other end of C4 is connected with 1 pin of operational amplifier U1A, and the other end of S10 is connected with 1 pin of U1A. The circuit is a typical differential amplification experimental circuit.
As shown in fig. 7, S3, S6, S7, S8, S9, S10 are closed, and the remaining S1, S2, S11 are opened to implement an inverse summation amplification experimental circuit, the working principle is that an input signal V4 is connected with one end of a C5, the other end of the C5 is connected with an R5, one end of the C5 connected with a V4 is connected with one end of an S9, the other end of the S9 is connected with one end of the C5 intersected with an R5, the other end of the R5 is connected with an S8, the other end of the S8 is connected with a pin 2 of an operational amplifier U1A, meanwhile, the 2 pin is connected with one end of S11, the other end of S11 is connected with R7, the other end of R7 is grounded, one end of R6 and the other end of R6 of the 2 pin are connected with C4, meanwhile, the other end of the S10 is connected with the pin 1 of the operational amplifier U1A of the C4, the other end of the S10 is connected with the pin 1 of the U1A, the input signal V3 is connected with one end of the C3, the other end of the C3 is connected with the R4, meanwhile, one end of the C3 connected with the V3 is connected with one end of the S7, the other end of the S7 is connected with one end of the C3 intersected with the R4, the other end of the R4 is connected with the S6, and the other end of the S6 is connected with the 2 feet of the operational amplifier U1A. The 3-pin of the operational amplifier U1A is connected with one end of an S3, the other end of the S3 is connected with an R1, and the other end of the R1 is grounded. This circuit is a typical inverse sum amplification experimental circuit.
as shown in FIG. 8, S1, S2, S3, S4, S5, S10 and S11 are closed, and the rest of S6, S7, S8 and S9 are opened to realize a homodromous summing amplification experimental circuit, wherein the working principle of the circuit is that an input signal V2 is connected with one end of C2, the other end of C2 is connected with R3, meanwhile, one end of C2 connected with V2 is connected with one end of S5, the other end of S5 is connected with the end where C2 intersects with R3, the other end of R3 is connected with S4, and the other end of S4 is connected with 3 pins of U1A. An input signal V1 is connected with one end of a C1, the other end of the C1 is connected with an R2, one end of the C1 connected with a V1 is connected with one end of an S2, the other end of the S2 is connected with one end of the C1 intersected with an R2, the other end of the R2 is connected with an S1, the other end of the S1 is connected with a pin 3 of an operational amplifier U1A, the pin 3 is connected with one end of the S3, the other end of the S3 is connected with an R1, and the other end of the R1. The 2 pin of the operational amplifier U1A is connected with one end of the S11, the other end of the S11 is connected with the R7, the other end of the R7 is grounded, one end of the R6 and the other end of the R6 of the 2 pin are connected with the C4 and the S10, the other end of the C4 is connected with the 1 pin of the operational amplifier U1A, and the other end of the S10 is connected with the 1 pin of the U1A. This circuit is a typical forward summing and amplifying experimental circuit.
as shown in fig. 9, S3, S8, S9 are closed, S1, S2, S4, S5, S6, S7, S10, S11 are opened to realize an integration experiment circuit; the principle is that an input signal V4 is connected with one end of C5, the other end of C5 is connected with R5, one end of C5 connected with V4 is connected with one end of S9, the other end of S9 is connected with the end of C5 intersected with R5, the other end of R5 is connected with S8, the other end of S8 is connected with pin 2 of operational amplifier U1A, the other end of pin 2 is connected with one end of R6, the other end of R6 is connected with C4 and is connected with one end of S10, the other end of C4 is connected with pin 1 of operational amplifier U1A, and the other end of S10 is connected with pin 1 of U1A. The pin 3 of U1A is connected to one end of S3, the other end of S3 is connected to R1, and the other end of R1 is grounded. This circuit is a typical integration experiment circuit.
as shown in fig. 10, S3, S8, S10 are closed, and S1, S2, S4, S5, S6, S7, S9, S11 are opened to realize a differential experiment circuit, which has the principle that an input signal V4 is connected to one end of C5, the other end of C5 is connected to R5, the other end of R5 is connected to S8, the other end of S8 is connected to the 2 pin of op-amp U1A, while the 2 pin is connected to one end of R6, the other end of R6 is connected to C4, while the other end of S10 is connected, the other end of C4 is connected to the 1 pin of op-amp U1A, and the other end of S10 is connected to the 1 pin of U1A. The pin 3 of U1A is connected to one end of S3, the other end of S3 is connected to R1, and the other end of R1 is grounded. This circuit is a typical differential experiment circuit.
the utility model discloses a general operational amplification circuit, the commonality is strong, conveniently records the life, to the preparation work load of teaching, can conveniently realize the target in a flexible way to the student.
Claims (1)
1. A general operational amplification experimental circuit is characterized by comprising input ends V1-V4, resistors R1-R7, capacitors C1-C5, switches S1-S11, an operational amplifier U1A and an output end VOUT;
The capacitor C1 is connected in parallel with the switch S2, the input end V1 is connected in series with one end of the capacitor C1 and one end of the switch S2, the resistor R2 is connected in series with the other end of the capacitor C1 and the switch S2, when the S2 is opened, the input end V1 is connected to the resistor R2 through the capacitor C1, after the S2 is closed, the input end V1 is directly connected to the resistor R2, and the other end of the R2 is connected to the pin 1 of the operational amplifier U1A through the switch S1;
The capacitor C2 is connected in parallel with the switch S5, the input end V2 is connected in series with one end of the capacitor C2 and one end of the switch S5, the resistor R3 is connected in series with the other end of the capacitor C2 and the switch S5, when the S3 is opened, the input end V2 is connected to the resistor R3 through the capacitor C2, after the S3 is closed, the input end V2 is directly connected to the resistor R3, and the other end of the R3 is connected to the pin 1 of the operational amplifier U1A through the switch S4;
The capacitor C3 is connected in parallel with the switch S7, the input end V3 is connected in series with one end of the capacitor C3 and one end of the switch S7, the resistor R4 is connected in series with the other end of the capacitor C3 and the switch S7, when the S7 is opened, the input end V3 is connected to the resistor R4 through the capacitor C3, after the S7 is closed, the input end V3 is directly connected to the resistor R4, and the other end of the R4 is connected to the 2 pin of the operational amplifier U1A through the switch S6;
The capacitor C5 is connected in parallel with the switch S9, the input end V4 is connected in series with one end of the capacitor C5 and one end of the switch S9, the resistor R5 is connected in series with the other end of the capacitor C5 and the switch S9, when the S9 is opened, the input end V4 is connected to the resistor R5 through the capacitor C5, after the S9 is closed, the input end V4 is directly connected to the resistor R5, and the other end of the R5 is connected to the 2 pin of the operational amplifier U1A through the switch S8;
The pin 3 of the operational amplifier U1A is also connected with one end of a switch S3, the other end of S3 is connected with one end of a resistor R1, and the other end of the resistor R1 is grounded; the 2 pin of the operational amplifier U1A is also connected with one end of a switch S11, the other end of the switch S11 is connected with one end of a resistor R7, and the other end of the resistor R7 is grounded; the 2 pin of the operational amplifier U1A is also connected with one end of a resistor R6, a capacitor C4 is connected with a switch S10 in parallel, the other end of the resistor R6 is connected with one end of a capacitor C4 and one end of a switch S10 in series, the other ends of the capacitor C4 and the switch S10 are connected with the 1 pin of the operational amplifier U1A, and the 1 pin of the operational amplifier U1A is connected with an output terminal VOUT.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821787424.7U CN209785375U (en) | 2018-10-31 | 2018-10-31 | general operational amplification experimental circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821787424.7U CN209785375U (en) | 2018-10-31 | 2018-10-31 | general operational amplification experimental circuit |
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| CN209785375U true CN209785375U (en) | 2019-12-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111179709A (en) * | 2020-03-13 | 2020-05-19 | 安徽工业大学 | Digital multifunctional power electronic technology teaching experiment platform |
| CN111243406A (en) * | 2020-03-13 | 2020-06-05 | 安徽工业大学 | Digital multifunctional power electronic technology experiment method |
-
2018
- 2018-10-31 CN CN201821787424.7U patent/CN209785375U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111179709A (en) * | 2020-03-13 | 2020-05-19 | 安徽工业大学 | Digital multifunctional power electronic technology teaching experiment platform |
| CN111243406A (en) * | 2020-03-13 | 2020-06-05 | 安徽工业大学 | Digital multifunctional power electronic technology experiment method |
| CN111179709B (en) * | 2020-03-13 | 2022-03-08 | 安徽工业大学 | Digital multifunctional power electronic technology teaching experiment platform |
| CN111243406B (en) * | 2020-03-13 | 2022-03-08 | 安徽工业大学 | Digital multifunctional power electronic technology experiment method |
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