CN209765481U

CN209765481U - Processor chip capable of decoding dot matrix word stock

Info

Publication number: CN209765481U
Application number: CN201822048763.XU
Authority: CN
Inventors: 张�林; 崔瀚之
Original assignee: Shenzhen Gaotong Semiconductor Co Ltd
Current assignee: Shenzhen Gaotong Semiconductor Co Ltd
Priority date: 2018-12-06
Filing date: 2018-12-06
Publication date: 2019-12-10
Anticipated expiration: 2028-12-06

Abstract

The utility model discloses a but treater chip of dot matrix word stock decodes, include: the system comprises an algorithm processor, a register group, a character information memory group, a program memory and a data cache region unit, wherein the register group, the character information memory group, the program memory and the data cache region unit are in communication connection with the algorithm processor. The utility model discloses a but treater chip of decoding dot matrix word stock has with low costs and the strong advantage of suitability, and the user need not purchase or customize appointed word stock chip, uses this chip can generate the ideal word stock that is fit for oneself very simply to when the product has the demand, can conveniently change the upgrading. And the anti-piracy capability of the word stock is enhanced.

Description

Processor chip capable of decoding dot matrix word stock

Technical Field

The utility model relates to a word stock chip technical field especially relates to a but processor chip of decoding word stock.

Background

At present, most of electronic equipment without an operating system needs to store a word stock in a memory to realize word display. The Chinese character library is a second largest language used in the world and has the largest character quantity. English and most Latin letters only use dozens of letters, and the data volume of the foreign language database is small and is generally stored in the main control MCU. The minimum standard of the Chinese character library is 6763 Chinese characters, and the maximum standard of the Chinese character library is 7 ten thousand Chinese characters, so the Chinese character library is required to be stored in a special memory, namely a character library chip.

Conventional word library chips are typically stored in a general purpose memory such as a norflash or a mask. The disadvantage of such products is that a large amount of work is required to complete a word stock file, so that it is inconvenient to modify too much, and the flexibility of the existing word stock chip is not sufficient. And the stored word stock information is easy to copy, and the confidentiality difficulty and the cost are higher.

Accordingly, the prior art is deficient and needs improvement.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming the not enough of prior art, provide a but the treater chip of decoding dot matrix word stock.

The technical scheme of the utility model as follows: the utility model provides a but treater chip of dot matrix word stock decodes, include: the arithmetic processor is in communication connection with the register group, the character information memory group, the program memory and the data cache region unit;

The character information memory group comprises a plurality of character information memory units, the character information memory group is mainly used for storing Chinese and foreign language lattice font data and a coding table, the program memory is used for storing a basic character calling algorithm and a transcoding algorithm, the register group comprises a plurality of registers and is mainly used for setting parameters of coding type, coding, lattice size, font type, width information, output special effect and the like of output characters, and the data cache region unit is mainly used for storing data processed by the algorithm processor.

Further, the register set includes: the system comprises an encoding type register, an encoding register, a dot matrix size register, a font type register, a width information register and an output special effect register.

Furthermore, the encoding type register, the encoding register, the dot matrix size register, the font type register, the width information register and the output special effect register are all 16-bit registers.

further, the character information memory group includes: code table storage unit, GBK Chinese character storage unit, Japanese character storage unit, Korean character storage unit and foreign language character storage unit.

Adopt above-mentioned scheme, the utility model discloses a but treater chip of decoding dot matrix word stock has with low costs and the strong advantage of suitability, and the user need not purchase or customize appointed word stock chip, uses this chip can generate the ideal word stock that is fit for oneself very simply to when the product has the demand, can conveniently change the upgrading. And the anti-piracy capability of the word stock is enhanced.

Drawings

FIG. 1 is a block diagram of a structural connection of a processor chip that can decode a lattice word library.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

Referring to fig. 1, the present invention provides a processor chip capable of decoding a dot matrix word library, including: the arithmetic processor 1 comprises a register group 4, a character information memory group 3, a program memory 2 and a data buffer area unit 5 which are connected with the arithmetic processor 1 in a communication way.

The character information memory group 3 comprises a plurality of character information memory units, the character information memory group 3 is mainly used for storing Chinese and foreign language lattice font data and a coding table, the program memory 2 is used for storing basic character calling algorithms and transcoding algorithms, the register group 4 comprises a plurality of registers and is mainly used for setting parameters of coding types, codes, lattice sizes, font types, width information, output special effects and the like of output characters, and the data cache region unit 5 is mainly used for storing data processed by the algorithm processor 1.

With continued reference to fig. 1, the register bank 4 includes: an encoding type register, an encoding register, a lattice size register, a font type register, a width information register, and an output special effect register (which do not correspond to the names in the drawings) (all are not labeled). The coding type register, the coding register, the dot matrix size register, the font type register, the width information register and the output special effect register are all 16-bit registers. The encoding type register is mainly used for setting encoding types, such as GBK, UNICODE encoding and the like. The encoding register is mainly used for encoding information corresponding to input characters, such as an o word in GBK encoding, and encoding the o word into 0xB0A 1. The lattice size register is mainly used for setting the lattice size of the input character, for example, 1616 represents the size of 16 × 16. The font type register is mainly used for setting fonts such as black bodies, Song bodies, round corners, line types and the like. The width information register is used for setting width information, such as equal width, unequal width and the like. The output special effect register is mainly used for setting special effects of output fonts, such as reversed white, italics, drawn lines and the like.

The character information memory group 3 includes: the code table storage unit, the GBK Chinese character storage unit, the Japanese character storage unit, the Korean character storage unit, the foreign character storage unit (all not labeled) and the like are respectively used for storing different character library data.

The program memory 2 is an OTP (one time programmable) area, can not be repeatedly programmed, and has a separate program programming interface. And the word library algorithm program in the program memory 2 is written by the program burning interface. The font data of the character information memory group 3 is written in through a font burning interface. And the data cache region unit 5 is communicated with the MCU of the user host through the SPI interface.

To sum up, the utility model discloses a treater chip of dot matrix word stock that can decode has with low costs and the strong advantage of suitability, and the user need not purchase or customize appointed word stock chip, uses this chip can generate the ideal word stock that is fit for oneself very simply to when the product has the demand, can conveniently change the upgrading. And the anti-piracy capability of the word stock is enhanced.

The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A processor chip capable of decoding a lattice word library, comprising: the arithmetic processor is in communication connection with the register group, the character information memory group, the program memory and the data cache region unit;

The character information memory group comprises a plurality of character information memory units, the character information memory group is mainly used for storing Chinese and foreign language lattice font data and a coding table, the program memory is used for storing a basic character calling algorithm and a transcoding algorithm, the register group comprises a plurality of registers and is mainly used for setting coding types, codes, lattice sizes, font types, width information and output special effect parameters of output characters, and the data cache region unit is mainly used for storing data processed by the algorithm processor.

2. The processor chip of a decodable lattice word stock of claim 1, wherein the set of registers comprises: the system comprises an encoding type register, an encoding register, a dot matrix size register, a font type register, a width information register and an output special effect register.

3. The processor chip of a decodable lattice word stock of claim 2, wherein the encoding type register, the encoding register, the lattice size register, the glyph type register, the width information register, and the output special effects register are 16-bit registers.

4. The processor chip of a decodable lattice word stock of claim 1, wherein the set of character information memories comprises: code table storage unit, GBK Chinese character storage unit, Japanese character storage unit, Korean character storage unit and foreign language character storage unit.