CN109358901B - Processor chip capable of decoding dot matrix word stock and implementation method - Google Patents
Processor chip capable of decoding dot matrix word stock and implementation method Download PDFInfo
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- CN109358901B CN109358901B CN201811487778.4A CN201811487778A CN109358901B CN 109358901 B CN109358901 B CN 109358901B CN 201811487778 A CN201811487778 A CN 201811487778A CN 109358901 B CN109358901 B CN 109358901B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F40/00—Handling natural language data
- G06F40/10—Text processing
- G06F40/12—Use of codes for handling textual entities
- G06F40/126—Character encoding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a processor chip capable of decoding a dot matrix word stock and an implementation method, wherein the processor chip comprises: and the algorithm processor is in communication with the register group, the character information memory group, the program memory and the data cache area unit. The processor chip of the decodable dot matrix word stock has the advantages of low cost and strong applicability, and a user does not need to purchase or customize a designated word stock chip, so that the chip can be used for generating an ideal word stock suitable for the user very simply, and the processor chip can be replaced and upgraded conveniently when the product is in need. And enhances the anti-piracy capability of the word stock.
Description
Technical Field
The invention relates to the technical field of word stock chips, in particular to a processor chip capable of decoding a word stock and an implementation method.
Background
Currently, most electronic devices that are not operating systems need word stock to be stored in a memory to realize word display. The Chinese character library is the language with the second largest global use amount and the largest character amount. English and most Latin letters only need tens of letters, and the data volume of the external text library is very small and is generally stored in the main control MCU. The minimum standard of the Chinese character library is 6763 Chinese characters, and the maximum standard is 7 Chinese characters, so that the Chinese character library needs to be stored in a special memory, namely a character library chip.
Conventional word stock chips are typically stored in a general memory such as a norflash or maskrom. The defects of the product are that a large amount of work is needed for completing a word stock file, so that excessive modification is inconvenient, the flexibility of the existing word stock chip is insufficient, the stored word stock information is easy to copy, and the confidentiality difficulty and the cost are high.
Accordingly, the prior art has drawbacks and needs improvement.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a processor chip capable of decoding a dot matrix word stock and an implementation method.
The technical scheme of the invention is as follows: the invention provides a processor chip of a decodable dot matrix word stock, comprising: an algorithm processor, a register group, a character information memory group, a program memory and a data cache unit which are connected with the algorithm processor in a communication way;
the character information memory group comprises a plurality of character information storage units, the character information memory group is mainly used for storing Chinese and foreign language lattice font data and an encoding table, the program memory is used for storing basic character calling algorithm and transcoding algorithm, the register group comprises a plurality of registers which are mainly used for setting parameters such as encoding type, encoding, lattice size, font type, width information, output special effects and the like of output characters, and the data buffer area unit is mainly used for storing data processed by the algorithm processor.
Further, the register set includes: the system comprises a coding type register, a coding register, a dot matrix size register, a font type register, a width information register and an output special effect register.
Further, the coding type register, the coding register, the dot matrix size register, the font type register, the width information register and the output special effect register are all 16-bit registers.
Further, the character information memory group includes: code table memory cell, GBK Chinese character memory cell, japanese character memory cell, korean character memory cell and foreign character memory cell.
The invention also provides a realization method of the processor chip capable of decoding the dot matrix word stock, which comprises the following steps:
step 1: providing an upper computer, wherein the upper computer generates word stock data and word stock algorithm data, and the word stock data is encrypted;
step 2: providing a user host, wherein the user host comprises a processor chip capable of decoding a dot matrix word stock, writing word stock data into a character information memory group of the processor chip, and writing word stock algorithm data into a program memory of the processor chip;
step 3: the MCU of the user host sends coding type parameters, character coding parameters, word size parameters, font type parameters and width information parameters to the processor chip;
step 4: the algorithm processor in the processor chip calls the word stock data in the character information memory group according to the word stock algorithm data in the program memory, and sends the generated font data to the MCU of the user host, wherein the algorithm processor decrypts the word stock data when the algorithm processor calls the word stock data;
step 5: and the user host MCU receives the font data of the processor chip and sends the font data to a display module of the user.
Further, the encryption method of the word stock data is an out-of-order encryption method, and comprises the following steps:
step 11: establishing a single Chinese character disorder table;
step 12: the single Chinese character data are scrambled according to the single Chinese character scrambling list;
step 13: establishing a disorder list of each area of the Chinese characters;
step 14: the Chinese character areas are disordered according to the disorder list of the Chinese character areas;
step 15: and regenerating the data of the single Chinese character into the database data according to the sequence of the disordered region.
Further, in the step 2, the word stock data is written into the character information memory through a word stock writing interface of the processor chip, and the word stock algorithm data is written into the program memory through a processor unit writing interface of the processor chip of the decodable word stock.
Further, the decrypting the word stock data in the step 4 includes the following steps:
step 41: calculating a Chinese character address according to the Chinese character coding and the disorder list;
step 42: calling out disordered word data;
step 43: and combining the single Chinese character disorder list to restore the called data.
By adopting the scheme, the processor chip of the decodable dot matrix word stock has the advantages of low cost and strong applicability, and a user does not need to purchase or customize a designated word stock chip, so that the chip can be used for generating an ideal word stock suitable for the user, and the processor chip can be replaced and upgraded conveniently when the product is in need. And enhances the anti-piracy capability of the word stock.
Drawings
FIG. 1 is a block diagram of a processor chip architecture connection for a decodable dot matrix word stock.
FIG. 2 is a flow chart of an implementation method of a processor chip capable of decoding a dot matrix word stock.
Fig. 3 is a flow chart of the encryption method in step 1 of the implementation method of the processor chip of the decodable dot matrix word library.
Fig. 4 is a flowchart of the decryption method in step 4 of the implementation method of the processor chip of the decodable dot matrix word library.
Detailed Description
The invention will be described in detail below with reference to the drawings and the specific embodiments.
Referring to fig. 1, the present invention provides a processor chip capable of decoding a dot matrix word stock, comprising: the algorithm processor 1 is in communication with the register set 4, the character information memory set 3, the program memory 2 and the data buffer unit 5 of the algorithm processor 1.
The character information memory group 3 comprises a plurality of character information storage units, the character information memory group 3 is mainly used for storing context lattice font data and encoding tables, the program memory 2 is used for storing basic character calling algorithms and transcoding algorithms, the register group 4 comprises a plurality of registers and is mainly used for setting parameters such as encoding types, encoding, lattice sizes, font types, width information, output special effects and the like of output characters, and the data buffer area unit 5 is mainly used for storing data processed by the algorithm processor 1.
With continued reference to fig. 1, the register set 4 includes: coding type register, coding register, dot matrix size register, font type register, width information register, and output special effect register (not corresponding to the name in the drawing) (none of them is labeled). The coding type register, the coding register, the dot matrix size register, the font type register, the width information register and the output special effect register are all 16-bit registers. The code type register is mainly used for setting the code type, such as GBK, UNICODE codes and the like. The coding register is mainly used for inputting information codes corresponding to characters, such as an 'o' word in GBK codes, and the codes are 0xB0A1. The dot size register is mainly used for setting the dot size of the input character, and 1616 represents the size of 16×16. The font type register is mainly used for setting fonts such as bold fonts, song Ti fonts, round fonts, linear fonts and the like. The width information register is used for setting width information such as equal width, unequal width and the like. The output special effect register is mainly used for setting the special effect of the output font, such as reversed white, italic, lower drawing line and the like.
The character information memory group 3 includes: code table storage unit, GBK Chinese character storage unit, japanese character storage unit, korean character storage unit, foreign character storage unit (all are not labeled), etc. are used for storing different word stock data respectively.
The program memory 2 is an OTP (one time programmable) area, is not rewritable, and has a separate program programming interface. The word stock algorithm program in the program memory 2 is written by the program burning interface. The word stock data of the character information memory group 3 is written through a word stock burning interface. The data buffer area unit 5 communicates with the MCU of the user host through an SPI interface. When the word stock chip is used, the word stock data are stored into the corresponding storage units in the character information storage group 3 through the word stock burning interface, the word stock algorithm program is written into the program storage 2 through the program burning interface, the algorithm processor 1 can execute the word stock algorithm program in the program storage 2, call the word stock data, and then can communicate and transmit data with the MCU of the user host through the SPI interface. Compared with the common word stock chip with only a memory, the hardware of the word stock chip can support encryption and data processing of the word stock data, and can flexibly write the required word stock data according to the needs, so that the applicability is good.
The processor chip of the decodable dot matrix word stock has the advantages of low cost and strong applicability, and a user does not need to purchase or customize a designated word stock chip, so that the chip can be used for generating an ideal word stock suitable for the user very simply, and the processor chip can be replaced and upgraded conveniently when the product is in need. And enhances the anti-piracy capability of the word stock.
Referring to fig. 2 and 4, a method for implementing a processor chip capable of decoding a dot matrix word stock is provided, which includes the following steps:
step 1: and providing an upper computer, wherein the upper computer generates word stock data and word stock algorithm data, and the word stock data is encrypted.
The encryption method of the word stock data is an out-of-order encryption method, and comprises the following steps:
step 11: establishing a single Chinese character disorder table; step 12: the single Chinese character data are scrambled according to the single Chinese character scrambling list; step 13: establishing a disorder list of each area of the Chinese characters; step 14: the Chinese character areas are disordered according to the disorder list of the Chinese character areas; step 15: and regenerating the data of the single Chinese character into the database data according to the sequence of the disordered region.
Step 2: providing a user host, wherein the user host comprises a processor chip capable of decoding a dot matrix word stock, writing word stock data into a character information memory group of the processor chip, and writing word stock algorithm data into a program memory of the processor chip.
The word stock data is written into the character information memory through a word stock burning interface of the processor chip, and the word stock algorithm data is written into the program memory through a processor unit burning interface of the processor chip of the decodable word stock.
Step 3: the MCU of the user host sends coding type parameters, character coding parameters, font size parameters, font type parameters and width information parameters to the processor chip;
step 4: and an algorithm processor in the processor chip calls the word stock data in the character information memory group according to the word stock algorithm data in the program memory, and sends the generated font data to the MCU of the user host, wherein the algorithm processor decrypts the word stock data when calling the word stock data.
In this step, the decryption of the word stock data includes the steps of: step 41: calculating a Chinese character address according to the Chinese character coding and the disorder list; step 42: calling out disordered word data; step 43: and combining the single Chinese character disorder list to restore the called data.
Step 5: and the user host MCU receives the font data of the processor chip and sends the font data to a display module of the user.
Because the word stock data is generated by encryption of an upper computer, even if the word stock is copied, the word stock data is normally displayed by an intuitive means, and can be effectively prevented from being pirated.
In summary, the processor chip of the decodable dot matrix word stock has the advantages of low cost and strong applicability, and users do not need to purchase or customize the designated word stock chip, so that the chip can be used for generating the ideal word stock suitable for the users very simply, and the replacement and the upgrading can be conveniently carried out when the products are in need. And enhances the anti-piracy capability of the word stock.
The foregoing description of the preferred embodiment of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (5)
1. A processor chip for a decodable library of lattice words, comprising: an algorithm processor, a register group, a character information memory group, a program memory and a data cache unit which are connected with the algorithm processor in a communication way;
the character information memory group comprises a plurality of character information storage units, the character information memory group is mainly used for storing Chinese and foreign language lattice font data and an encoding table, the program memory is used for storing basic character calling algorithm and transcoding algorithm, the register group comprises a plurality of registers, the registers are mainly used for setting encoding types, encoding, lattice sizes, font types, width information and output special effect parameters of output characters, and the data buffer area unit is mainly used for storing data processed by the algorithm processor; the register set includes: the system comprises a coding type register, a coding register, a dot matrix size register, a font type register, a width information register and an output special effect register; the character information memory group includes: code table memory cell, GBK Chinese character memory cell, japanese character memory cell, korean character memory cell and foreign character memory cell.
2. The processor chip of claim 1, wherein the encoding type register, encoding register, dot size register, glyph type register, width information register, and output special effect register are all 16-bit registers.
3. A method for implementing a processor chip capable of decoding a lattice word stock, comprising the steps of:
step 1: providing an upper computer, wherein the upper computer generates word stock data and word stock algorithm data, and the word stock data is encrypted;
step 2: providing a user host, wherein the user host comprises a processor chip capable of decoding a dot matrix word stock, writing word stock data into a character information memory group of the processor chip, and writing word stock algorithm data into a program memory of the processor chip;
step 3: the MCU of the user host sends coding type parameters, character coding parameters, font size parameters, font type parameters and width information parameters to the processor chip;
step 4: the algorithm processor in the processor chip calls the word stock data in the character information memory group according to the word stock algorithm data in the program memory, and sends the generated font data to the MCU of the user host, wherein the algorithm processor decrypts the word stock data when the algorithm processor calls the word stock data;
step 5: the user host MCU receives the font data of the processor chip and sends the font data to a display module of a user; the encryption method of the word stock data is an out-of-order encryption method, and comprises the following steps:
step 11: establishing a single Chinese character disorder table;
step 12: the single Chinese character data are scrambled according to the single Chinese character scrambling list;
step 13: establishing a disorder list of each area of the Chinese characters;
step 14: the Chinese character areas are disordered according to the disorder list of the Chinese character areas;
step 15: and regenerating the data of the single Chinese character into the database data according to the sequence of the disordered region.
4. The method according to claim 3, wherein in the step 2, the word stock data is written into the character information memory through a word stock programming interface of the processor chip, and the word stock algorithm data is written into the program memory through a processor unit programming interface of the processor chip.
5. A method of implementing a processor chip for a decodable dot matrix word stock according to claim 3, wherein the decrypting of the word stock data in step 4 comprises the steps of:
step 41: calculating a Chinese character address according to the Chinese character coding and the disorder list;
step 42: calling out disordered word data;
step 43: and combining the single Chinese character disorder list to restore the called data.
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| CN109992221B (en) * | 2019-04-12 | 2022-11-18 | 深圳高通半导体有限公司 | Method for realizing processor chip for vector font operation |
| CN112565245B (en) * | 2020-12-02 | 2023-04-18 | 深圳市汇顶科技股份有限公司 | Data transmission method, production line end tool, chip, server and storage medium |
| CN112559751A (en) * | 2020-12-23 | 2021-03-26 | 西南交通大学 | Dynamic word stock optimization method based on single chip microcomputer |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1037601A (en) * | 1988-01-06 | 1989-11-29 | 北京大学 | Terminal machine of the common Chinese and western language |
| US4890230A (en) * | 1986-12-19 | 1989-12-26 | Electric Industry Co., Ltd. | Electronic dictionary |
| CN1070057A (en) * | 1992-09-01 | 1993-03-17 | 上海高通电脑有限责任公司 | Universal character formula Chinese character display method and the Chinese Card that designs by this method |
| CN1105762A (en) * | 1994-04-15 | 1995-07-26 | 曾冬初 | Multistage structure Chinese character base technique and its Chinese language computer operating system design |
| CN2779484Y (en) * | 2005-04-21 | 2006-05-10 | 上海集通数码科技有限责任公司 | A universal compressed Chinese character library chip |
| CN101625848A (en) * | 2009-07-28 | 2010-01-13 | 宁波新然电子信息科技发展有限公司 | Realization method of vector font library oriented to embedded platform |
| CN102426565A (en) * | 2011-11-03 | 2012-04-25 | 北京华大智宝电子系统有限公司 | SOC (System on Chip) chip with font processing function |
| CN105620060A (en) * | 2015-12-17 | 2016-06-01 | 长安大学 | Printer control circuit |
| CN209765481U (en) * | 2018-12-06 | 2019-12-10 | 深圳高通半导体有限公司 | Processor chip capable of decoding dot matrix word stock |
-
2018
- 2018-12-06 CN CN201811487778.4A patent/CN109358901B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4890230A (en) * | 1986-12-19 | 1989-12-26 | Electric Industry Co., Ltd. | Electronic dictionary |
| CN1037601A (en) * | 1988-01-06 | 1989-11-29 | 北京大学 | Terminal machine of the common Chinese and western language |
| CN1070057A (en) * | 1992-09-01 | 1993-03-17 | 上海高通电脑有限责任公司 | Universal character formula Chinese character display method and the Chinese Card that designs by this method |
| CN1105762A (en) * | 1994-04-15 | 1995-07-26 | 曾冬初 | Multistage structure Chinese character base technique and its Chinese language computer operating system design |
| CN2779484Y (en) * | 2005-04-21 | 2006-05-10 | 上海集通数码科技有限责任公司 | A universal compressed Chinese character library chip |
| CN101625848A (en) * | 2009-07-28 | 2010-01-13 | 宁波新然电子信息科技发展有限公司 | Realization method of vector font library oriented to embedded platform |
| CN102426565A (en) * | 2011-11-03 | 2012-04-25 | 北京华大智宝电子系统有限公司 | SOC (System on Chip) chip with font processing function |
| CN105620060A (en) * | 2015-12-17 | 2016-06-01 | 长安大学 | Printer control circuit |
| CN209765481U (en) * | 2018-12-06 | 2019-12-10 | 深圳高通半导体有限公司 | Processor chip capable of decoding dot matrix word stock |
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