CN209691744U - A kind of QFN/DFN superposing type chip - Google Patents
A kind of QFN/DFN superposing type chip Download PDFInfo
- Publication number
- CN209691744U CN209691744U CN201920856021.1U CN201920856021U CN209691744U CN 209691744 U CN209691744 U CN 209691744U CN 201920856021 U CN201920856021 U CN 201920856021U CN 209691744 U CN209691744 U CN 209691744U
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- CN
- China
- Prior art keywords
- chip
- bonding wire
- soldered ball
- pin
- silver slurry
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
The utility model discloses a kind of QFN/DFN superposing type chips, including frame, pin, silver slurry layer, first chip, adhesive layer, second chip, first soldered ball, first bonding wire, second soldered ball, second bonding wire, first chip is fixed using silver slurry layer with frame, and the second chip is fixed using the adhesive layer substitution 0.05mm silver slurry layer with a thickness of 0.025mm, whole height can be effectively reduced, by the way that the first soldered ball is arranged on the second chip, first bonding wire can be drawn from the side of the first soldered ball, and first bonding wire use 0.025mm annealed copper wire, therefore, first bonding wire can obtain more gentle transition, avoid unexpected bending, it effectively prevent the first bonding wire that desoldering occurs bad, whole height is effectively reduced simultaneously.The second soldered ball is set on the more abundant pin in space, is connect the first chip with pin by the second bonding wire, realizes the output of the first chip.The apparatus structure is simple, is designed by superposing type, realizes the encapsulation of multi-chip, and whole height is lower, meets requirement.
Description
Technical field
The utility model relates to a kind of chip more particularly to a kind of QFN/DFN superposing type chips.
Background technique
With the development of IC chip industry, the miniature trend of electronic product, the requirement to encapsulating products is higher and higher, and product is thick
Degree slimming, volume miniaturization, function many types ofization have become mainstream.QFN/DFN product is exactly to meet requirements above, but common
IC or 2 single IC chip of most of product or more small IC chips put packing forms in one plane simultaneously.
If multiple IC must be assembled in inside a product, multifunctionality is carried out, but chip area has been more than product base plane
Or when very close, the packing forms in plane cannot meet requirement.In view of the above drawbacks, it is really necessary to design one
Kind QFN/DFN superposing type chip.
Utility model content
The purpose of this utility model is to provide a kind of QFN/DFN superposing type chip, which passes through
The superposition encapsulation of multi-chip is realized in superposing type design, and whole height is lower, meets requirement.
In order to solve the above technical problems, the utility model provides a kind of QFN/DFN superposing type chip, including frame, pin,
Silver slurry layer, the first chip, adhesive layer, the second chip, the first soldered ball, the first bonding wire, the second soldered ball, the second bonding wire, the frame
It is provided with pin, the pin is integrally connected with frame, and the silver slurry layer is located at frame roof, the silver slurry layer and frame
Frame is weldingly connected, and first chip is located at the top of silver slurry layer, and first chip is weldingly connected with silver slurry layer, described
Adhesive layer is located at the top of the first chip, and the adhesive layer is connected with the first die bonding, and second chip is located at bonding
Layer top, second chip is Nian Jie with adhesive layer to be connected, and second chip is equipped with the first soldered ball, first weldering
Ball is weldingly connected with the second chip, and first bonding wire is weldingly connected with the first soldered ball and the first chip respectively, and described
Two soldered balls are located at pin upper end, and second soldered ball is weldingly connected with pin, second bonding wire respectively with the second soldered ball
It is weldingly connected with the first chip.
The utility model further improves as follows:
Further, silver paste layer with a thickness of 0.05mm.
Further, the adhesive layer with a thickness of 0.025mm.
Further, the material of first bonding wire is red copper, and the diameter of first bonding wire is 0.02mm.
Further, the material of second bonding wire is red copper, and the diameter of second bonding wire is 0.025mm.
Compared with prior art, the QFN/DFN superposing type chip, the first chip is fixed using silver slurry layer with frame, and is made
The second chip is fixed with the adhesive layer substitution 0.05mm silver slurry layer with a thickness of 0.025mm, whole height can be effectively reduced,
By the way that the first soldered ball is arranged on the second chip, the first bonding wire can be drawn from the side of the first soldered ball, and the first bonding wire uses
The annealed copper wire of 0.025mm, therefore, the first bonding wire can obtain more gentle transition, avoid unexpected bending, effectively prevent first
It is bad that desoldering occurs for bonding wire, while whole height is effectively reduced.The second soldered ball is set on the more abundant pin in space, passes through
First chip is connect by two bonding wires with pin, realizes the output of the first chip.The apparatus structure is simple, is designed by superposing type,
Realize the encapsulation of multi-chip, and whole height is lower, meets requirement.
Detailed description of the invention
Fig. 1 shows the utility model structure diagram
In figure: frame 1, pin 2, silver slurry layer 3, the first chip 4, adhesive layer 5, the second chip 6, the weldering of the first soldered ball 7, first
Line 8, the second soldered ball 9, the second bonding wire 10.
Specific embodiment
As shown in Figure 1, a kind of QFN/DFN superposing type chip, including it is frame 1, pin 2, silver slurry layer 3, the first chip 4, viscous
Layer 5, the second chip 6, the first soldered ball 7, the first bonding wire 8, the second soldered ball 9, the second bonding wire 10 are connect, the frame 1 is equipped with pin
2, the pin 2 is integrally connected with frame 1, and the silver slurry layer 3 is located at 1 top of frame, the silver slurry layer 3 and frame 1
It is weldingly connected, first chip 4 is located at 3 top of silver slurry layer, and first chip 4 is weldingly connected with silver slurry layer 3, described
Adhesive layer 5 be located at the top of the first chip 4, the adhesive layer 5 connected, described the second chip 6 Nian Jie with the first chip 4
In 5 top of adhesive layer, second chip 6 is Nian Jie with adhesive layer 5 to be connected, and second chip 6 is equipped with the first soldered ball 7,
First soldered ball 7 is weldingly connected with the second chip 6, first bonding wire 8 respectively with the first soldered ball 9 and the first chip 4
It being weldingly connected, second soldered ball 9 is located at 2 upper end of pin, and second soldered ball 9 is weldingly connected with pin 2, and described
Two bonding wires 10 are weldingly connected with the second soldered ball 9 and the first chip 6 respectively, silver paste layer 3 with a thickness of 0.05mm, the bonding
Layer 5 with a thickness of 0.025mm, the material of first bonding wire 8 is red copper, and the diameter of first bonding wire 8 is 0.02mm, described
The material of second bonding wire 10 is red copper, and the diameter of second bonding wire 10 is 0.025mm, the QFN/DFN superposing type chip, first
Chip 4 is fixed using silver slurry layer 3 and frame 1, and substitutes 3 pairs of 0.05mm silver slurry layer using with a thickness of the adhesive layer 5 of 0.025mm
Second chip 6 is fixed, whole height can be effectively reduced, by the way that the first soldered ball 7 is arranged on the second chip 6, the first bonding wire 8 can
From the side of the first soldered ball 7 draw, and the first bonding wire 8 using 0.025mm annealed copper wire, therefore, the first bonding wire 8 can obtain compared with
For gentle transition, unexpected bending is avoided, effectively prevent the first bonding wire 8 that desoldering occurs bad, while whole height is effectively reduced.
The second soldered ball 9 is set on the more abundant pin 2 in space, is connect the first chip 4 with pin by the second bonding wire 10, realizes the
The output of one chip 4.The apparatus structure is simple, is designed by superposing type, realizes the encapsulation of multi-chip, and whole height is lower,
Meet requirement.
The utility model is not limited to above-mentioned specific embodiment, and those skilled in the art visualize from above-mentioned
Hair, without creative labor, the various transformation made are all fallen within the protection scope of the utility model.
Claims (5)
1. a kind of QFN/DFN superposing type chip, it is characterised in that including frame, pin, silver slurry layer, the first chip, adhesive layer,
Two chips, the first soldered ball, the first bonding wire, the second soldered ball, the second bonding wire, the frame are equipped with pin, the pin and frame
Frame is integrally connected, and the silver slurry layer is located at frame roof, and the silver slurry layer is connected with frame welding, first chip
At the top of silver slurry layer, first chip is weldingly connected with silver slurry layer, and the adhesive layer is located at the top of the first chip, institute
The adhesive layer stated is connected with the first die bonding, and second chip is located at the top of adhesive layer, second chip and viscous
It connects layer bonding to be connected, second chip is equipped with the first soldered ball, and first soldered ball is weldingly connected with the second chip, described
The first bonding wire be weldingly connected respectively with the first soldered ball and the first chip, second soldered ball is located at pin upper end, described
Second soldered ball is weldingly connected with pin, and second bonding wire is weldingly connected with the second soldered ball and the first chip respectively.
2. QFN/DFN superposing type chip as described in claim 1, it is characterised in that silver paste layer with a thickness of 0.05mm.
3. QFN/DFN superposing type chip as described in claim 1, it is characterised in that the adhesive layer with a thickness of 0.025mm.
4. QFN/DFN superposing type chip as described in claim 1, it is characterised in that the material of first bonding wire is red copper,
The diameter of first bonding wire is 0.02mm.
5. QFN/DFN superposing type chip as described in claim 1, it is characterised in that the material of second bonding wire is red copper,
The diameter of second bonding wire is 0.025mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920856021.1U CN209691744U (en) | 2019-06-10 | 2019-06-10 | A kind of QFN/DFN superposing type chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920856021.1U CN209691744U (en) | 2019-06-10 | 2019-06-10 | A kind of QFN/DFN superposing type chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209691744U true CN209691744U (en) | 2019-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201920856021.1U Active CN209691744U (en) | 2019-06-10 | 2019-06-10 | A kind of QFN/DFN superposing type chip |
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| CN (1) | CN209691744U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111162066A (en) * | 2020-01-24 | 2020-05-15 | 昆山泓冠光电科技有限公司 | Backlight light source |
-
2019
- 2019-06-10 CN CN201920856021.1U patent/CN209691744U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111162066A (en) * | 2020-01-24 | 2020-05-15 | 昆山泓冠光电科技有限公司 | Backlight light source |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 247100 Electronic Information Industrial Park 10, Chizhou economic and Technological Development Zone, Anhui Patentee after: Chizhou Huayu Electronic Technology Co.,Ltd. Address before: 247100 Electronic Information Industrial Park 10, Chizhou economic and Technological Development Zone, Anhui Patentee before: CHIZHOU HISEMI ELECTRONIC TECHNOLOGY Co.,Ltd. |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A QFN/DFN stacked chip Effective date of registration: 20220916 Granted publication date: 20191126 Pledgee: China Co. truction Bank Corp Chizhou branch Pledgor: Chizhou Huayu Electronic Technology Co.,Ltd. Registration number: Y2022980015312 |