CN209624668U - A kind of current transformer self correcting system - Google Patents

Abstract

The utility model provides a kind of current transformer self correcting system, which includes power control circuit, data input circuit, data processing circuit, data output circuit, key control circuit；Wherein data input circuit includes filter circuit and signal acquisition circuit；Data output circuit includes signal output apparatus and signal display circuit；Data processing circuit includes FPGA and ARM two parts and data buffer circuit and data storage circuitry；FPGA portion includes analog-to-digital conversion interface unit, programmable logic cells, phase locked-loop unit, in-line memory, reset unit；The part ARM includes DDR₃The expanding element of SDRAM, LTC2 × 7, reset unit, Bus Interface Unit；The system can carry out real time correction processing to the nonlinear problem of current transformer, to improve the measurement accuracy of electric current.

Description

A kind of current transformer self correcting system

Technical field

The utility model relates to Current Mutual Inductance fields, and in particular to a kind of current transformer self correcting system.

Background technique

Power network development was more and more intelligent in recent years, and current transformer plays in terms of relay protection and electric-power metering Very important effect, intelligentized current transformer can be improved the accuracy of whole system with reliably, accelerate entire power transformation The number and IT application process stood, and cause the major transformation of Automation of Electric Systems device and protected mode；But in reality Current transformer in but has nonlinear object, causes final measurement result there are error, therefore circuit The design sense of mutual inductor self correcting system is great；There are the automatic correcting method of many current transformers, such as neural network at present, loses The method of propagation algorithm etc.；Automatic correcting method is the important means of processing system nonlinear problem using relatively broad.

Summary of the invention

The purpose of this utility model is: a kind of current transformer self correcting system is provided, to current data During reason, by FPGA processor in such a way that arm processor combines, the correction to current signal nonlinear object is realized.

The technical solution of the utility model is: a kind of current transformer self correcting system of the utility model, including power supply Control circuit, data input circuit, data processing circuit, data output circuit, key control circuit；Wherein data input circuit Including filter circuit and signal acquisition circuit；Data output circuit includes signal output apparatus and signal display circuit；At data Managing circuit includes FPGA and ARM two parts and data buffer circuit and data storage circuitry.Its design feature is:

Power control circuit is powered using DC-DC power source 3.3V, power supply needed for system is provided, for ensuring whole system It operates normally, with data input circuit, data processing circuit, data output circuit is connected.

Filter circuit uses FIR low pass filter, for filtering interference and noise in current signal, with signal acquisition electricity Road is connected.

Signal acquisition circuit is completed by A/D converter, using AD7893 chip, for realizing current-mode analog quantity to digital quantity Conversion, be connected with filter circuit and FPGA portion.

Data buffer circuit is to use DDR SDRAM as memory, using AS4C32M16D1 chip, for temporarily storing Data are connected as the buffering of data with FPGA portion.

The SoC fpga chip that the part FPGA and ARM uses Altera to embed Cortex-A9 hard nucleus management device forms, Altera is seamlessly connected based on the hard nucleus management device system of ARM by high broadband interconnection and FPGA hardware part, including FPGA and ARM two parts；Wherein FPGA portion uses the EPCQ256 chip of CycloneV series, the realization for logic function With the processing of digital signal, it is connected with signal acquisition circuit, data buffer circuit；The part ARM uses 800MHZ double-core ARM Cortex-A9 MPCore realizes self-correcting as processor, for being embedded in Self-Tuning Algorithm, deposits with signal output apparatus, data Storage road is connected.

Signal output apparatus is completed by D/A converter, using DAC7615 chip, for realizing ARM treated electric current number Conversion of the word amount to analog quantity is connected with the part ARM and signal display circuit.

Signal display circuit uses the oscillograph of DS1102E model, for showing and the current wave after measuring system correction Shape is connected with signal output apparatus.

Data storage circuitry is to use FLASH as memory, using the S29GL512P chip of Nor FLASH, for depositing The data and program in arm processor are put, when carrying out power on operation, arm processor can read configuration number from FLASH automatically According to, with ARM part be connected.

Key control circuit is connected for the restarting to system with data processing circuit using reset key.

Further embodiment is: the FPGA portion includes analog-to-digital conversion interface unit, programmable logic cells, locking phase Ring element, in-line memory, reset unit；The above-mentioned part ARM includes DDR₃The expanding element of SDRAM, LTC2 × 7 resets Unit, Bus Interface Unit.

Further embodiment is: the A/D converter is using the AD7893 chip produced by ADI company, is a kind of The hybrid technique technology that accurate bipolar circuit and Low-Power CMOS are joined logically together, shares 12 ADC, resolution ratio For 12bit, a built-in 6 μ s gradual approaching A/D converters carry out data using the serial interface port of a high speed Output, Lai Shixian analog-to-digital conversion.Relevant pins description: CS: chip selection signal input terminal；SCLK: input end of clock；DI0 ~ DI11: 12 bit digital quantity output ends；CONVST: conversion starting input signal；RESET: the RESET input.A/D converter analog-to-digital conversion mistake Journey: (1) obtaining reset instruction from the processing of FPGA portion internal logic first, and A/D converter, which starts to execute to reset, to be operated and open Beginning work；(2) secondly A/D converter starts the analog quantity that current signal is obtained from filter circuit；(3) A/D converter is to even The current analog signal of continuous variation takes fixed time instant to be sampled a series of, then the sampling value with corresponding two into Number processed shows；(4) data encoded are input in FPGA, under the processing of FPGA portion internal logic, carry out lower step Data processing operation.

The DDR SDRAM memory uses AS4C32M16D1 chip, and address is A0 ~ A11, total storage of the chip Capacity is 512Mbits, provides sufficient memory for whole system to store data；Comprising only in FPGA portion processor piece Vertical SDRAM refresh control logic, can directly with DDR SDRAM carry out interface, there is no need to host interface signals；Phase The Pin description of pass: CS: chip selection signal；CKE: clock enable signal；SADDR:12 bit address line, A0 ~ A11 are operated in reading and writing When, address wire time-sharing multiplex is row address and column address；BA: page address, BA0, BA1；DQ: bidirectional data line, DQ0 ~ DQ15； RAS, CAS, WE: command-control signal；DQM:SDRAM data mask；RESET: the RESET input.The read-write of DDR SDRAM is grasped Make process: (1) by sending initialization directive inside FPGA processor, DDR SDRAM starts to be initialized；(2) it initially enters Write operation state, writing line effective order, write operation order and address signal are simultaneously emitted by, the electric current that A/D converter is acquired Digital signal is transmitted in FPGA portion, is handled and is transferred data in DDR SDRAM memory again by FPGA internal logic； (3) by sending initialization directive inside FPGA portion processor, DDR SDRAM starts to be initialized；(4) reading behaviour is initially entered Make state, read in row effective order, read operation order and address signal are simultaneously emitted by, and the processing of FPGA portion internal logic is read The data stored in DDR SDRAM.

The FLASH memory uses the S29GL512P chip of Nor FLASH, and the total memory capacity of the chip is 512Mbits is equipped with write buffer in inside, in one operation most so that system has sufficient space to carry out data storage The programmed algorithm of 64 byte of plurality of programmable and standard is compared, and the effective programming used time is shorter；Relevant pins description: CE#: Piece selects enable end；CKE: clock enable signal；SADDR:26 bit address line, A0 ~ A25；DQ: bidirectional data line, DQ0 ~ DQ15； RY/BY#: the pending datas such as offer；WP#/ACC: accelerate program speed input terminal；OE#: data export enable end；WE#: control is write Operating side；BYTE#: mode selection terminal；RESET#: hardware reset input terminal.The read-write operation process of FLASH: (1) by the portion ARM Initialization command adapted thereto is sent inside point processor, FLASH starts to be initialized, before carrying out write operation firstly the need of Erasing operation is executed, position all in object block is all written as 0；(2) write operation state is initially entered, writing line is gone all out to do one's duty regardless of personal danger It enables, write operation order and address signal are simultaneously emitted by, after ARM segment processor receives dependent instruction, store data into In FLASH；(3) by sending initialization directive inside ARM segment processor, FLASH starts to be initialized；(4) for reading Operation is controlled by #CE and #OE, when being both low level, directly can read data from appropriate address.

The D/A converter be using Texas Instrument (TI) production DAC7615 chip, four road serial inputs, 12 Voltage output digital analog converter, resolution ratio 12bit；Relevant pins description: CS: chip selection signal input terminal；SCLK: clock input End；DT0 ~ DT11:12 bit digital quantity input terminal；V_REF: reference voltage input；RESET: the RESET input；D/A converter mould Number conversion process: (1) obtaining reset instruction from ARM partial interior processor first, and D/A converter, which starts to execute, resets operation And it starts to work；(2) input register of D/A converter is connected by the part ARM drive control, when the input in DAC7615 is posted When the data of conversion being written in storage, it can be transported to by DAC register in D/A converter and complete corresponding conversion；(3) will The binary code of digital signal is converted into corresponding analog quantity, and transformation result is exported by output end；(4) it send into oscillograph Show current signal.

The utility model has the effect of positive: (1) a kind of current transformer self correcting system of the utility model, hard Use ARM for hard nucleus management device system, the self-correcting of Lai Shixian current transformer as data acquisition unit using FPGA on part Processing；(2) a kind of current transformer self correcting system of the utility model is asked for solving non-linear caused phase error Topic, correcting mode is simple, and effect is obvious；(3) a kind of current transformer self correcting system of the utility model, can be according to specific For requirement of experiment by relevant Self-Tuning Algorithm insertion arm processor, bearing calibration is unrestricted, flexible in application.

Detailed description of the invention:

Fig. 1 is the structural schematic diagram of the self correcting system of the utility model；

Fig. 2 is the correction portion circuit connection diagram of the utility model.

Specific embodiment:

The utility model is described in further detail with reference to the accompanying drawings and detailed description.

(embodiment 1) is shown in Fig. 1, and current transformer self correcting system includes power control circuit, data input circuit, data Processing circuit, data output circuit, key control circuit；Wherein data input circuit includes filter circuit and signal acquisition electricity Road；Data output circuit includes signal output apparatus and signal display circuit；Data processing circuit includes FPGA and ARM two parts And data buffer circuit and data storage circuitry.

The SoC fpga chip that the part FPGA and ARM uses Altera to embed Cortex-A9 hard nucleus management device forms, Altera is seamlessly connected based on the hard nucleus management device system of ARM by high broadband interconnection and FPGA hardware part, including FPGA and ARM two parts；Wherein FPGA portion uses the EPCQ256 chip of CycloneV series, including analog-to-digital conversion interface list Member, programmable logic cells, phase locked-loop unit, in-line memory, reset unit, realization and number letter for logic function Number processing, be connected with signal acquisition circuit, data buffer circuit；The part ARM uses 800MHZ double-core ARM Cortex-A9 MPCore is as processor, including DDR₃The expanding element of SDRAM, LTC2 × 7, reset unit, Bus Interface Unit, for embedding Enter Self-Tuning Algorithm and realize self-correcting, is connected with signal output apparatus, data storage circuitry.

See that Fig. 2, A/D converter are using the AD7893 chip produced by ADI company, is a kind of by accurate bipolarity electricity The hybrid technique technology that road and Low-Power CMOS are joined logically together, shares 12 ADC, resolution ratio 12bit, and built-in one 6 μ s gradual approaching A/D converters, the output of data is carried out using the serial interface port of a high speed, and Lai Shixian modulus turns It changes；A/D converter analog-digital conversion process: (1) reset instruction RESET, A/D are obtained first from FPGA portion internal logic processing Converter, which starts to execute to reset, to be operated and starts to work；(2) secondly after chip selection signal end CS acquisition significant level, A/D conversion Device starts to obtain signal analog from filter circuit；(3) A/D converter is at the clock instruction SCLK of FPGA to consecutive variations Current-mode analog quantity take fixed time instant to be sampled a series of, then the sampling value is come out with binary number representation； (4) the data DI0 ~ DI11 encoded is input in FPGA under the action of the coherent signals such as CONVST, in FPGA portion Under portion's logical process, lower step data processing operation is carried out.

DDR SDRAM memory uses AS4C32M16D1 chip, and address is A0 ~ A11, and the total memory capacity of the chip is 512Mbits provides sufficient memory for whole system to store data；Comprising independent in FPGA portion processor piece SDRAM refresh control logic, can directly with DDR SDRAM carry out interface, there is no need to host interface signals；DDR The read-write operation process of SDRAM: (1) by sending CKE instruction and initialization directive, DDR SDRAM inside FPGA portion processor Start to be initialized；(2) secondly after chip selection signal end CS acquisition significant level, DDR SDRAM memory, which initially enters, to be write Mode of operation, writing line effective order, write operation order and address signal are simultaneously emitted by, in coherent signals such as RAS, CAS, WE The current signal digital quantity that A/D converter acquires is transmitted in FPGA portion under effect, is handled again by FPGA internal logic Data DQ0 ~ DQ15 is transmitted in DDR SDRAM memory；(3) by sending CKE instruction and initialization inside FPGA processor Instruction, DDR SDRAM start to be initialized；(4) secondly after chip selection signal end CS acquisition significant level, DDR SDRAM is deposited Reservoir initially enters read operation state, reads in row effective order, and read operation order and address signal are simultaneously emitted by, RAS, CAS, The data stored in DDR SDRAM are read in the processing of FPGA internal logic under the action of the coherent signals such as WE.

FLASH memory uses the S29GL512P chip of Nor FLASH, and the total memory capacity of the chip is 512Mbits, So that system has sufficient space to carry out data storage, it is equipped with write buffer in inside, it is at most programmable in one operation The programmed algorithm of 64 bytes and standard is compared, and the effective programming used time is shorter.The read-write operation process of FLASH: (1) by ARM partial interior sends CKE instruction and RESET# instruction, and FLASH starts to be initialized, before carrying out write operation first Erasing operation is needed to be implemented, position all in object block is all written as 0；(2) effectively electricity secondly is obtained from chip selection signal end CE# After flat, FLASH memory initially enters write operation state, writing line effective order, and write operation order and address signal are sent out simultaneously Out, after ARM is partially received command adapted thereto, by data under the action of the coherent signals such as RY/BY#, WP#/ACC, WE#, BYTE# DQ0 ~ DQ15 is stored into FLASH；(3) CKE instruction is sent by ARM partial interior and RESET# is instructed, FLASH starts to carry out Initialization；(4) it for read operation, is controlled by #CE and #OE, when being both low level, can directly be read from appropriate address Data DQ0 ~ DQ15.

D/A converter is using the DAC7615 chip of Texas Instrument (TI) production, four road serial inputs, and 12 voltages are defeated Digital analog converter out, resolution ratio 12bit；D/A converter analog-digital conversion process: (1) first from ARM internal processor pass through The end RESET obtains reset instruction, and D/A converter, which starts to execute to reset, to be operated and start to work；(2) secondly from chip selection signal end CS Significant level is obtained, the input register of D/A converter is connected by ARM drive control at the clock instruction SCLK of the part ARM, When data DT0 ~ DT11 of conversion is written in the input register in DAC7615, D/A conversion can be sent by DAC register Start to convert in device；(3) binary code of digital signal is converted into current signal analog, transformation result passes through output end Output；(4) it send and shows current signal into oscillograph.

In conclusion a kind of current transformer self correcting system of the present embodiment, the process of system self-correcting are right first Whole device carries out initialization process, when current signal is input to signal acquisition electricity after filter circuit filters out interference and noise The conversion of mould electricity is carried out in road, digital current signal is input in FPGA portion after converting, and completes the place to digital signal Reason, then treated data transmission is partially completed algorithm process, FLASH storage circuit and DDR SDRAM storage circuit to ARM For storing related data and variable, then analog current signal is exported by signal output apparatus again, is finally sent to oscillography Current signal is shown in device, completes the self-calibration process of system.

Claims (2)

1. current transformer self correcting system, which includes power control circuit, data input circuit, data processing circuit, Data output circuit, key control circuit；Wherein data input circuit includes filter circuit and signal acquisition circuit；Data output Circuit includes signal output apparatus and signal display circuit；Data processing circuit includes that FPGA and ARM two parts and data are slow Rush circuit and data storage circuitry, it is characterised in that:

Power control circuit is powered using DC-DC power source 3.3V, power supply needed for system is provided, for ensuring the normal of whole system Operation, with data input circuit, data processing circuit, data output circuit is connected；

Filter circuit uses FIR low pass filter, for filtering interference and noise in current signal, with signal acquisition circuit phase Even；

Signal acquisition circuit is completed by A/D converter, using AD7893 chip, for realizing current-mode analog quantity turning to digital quantity It changes, is connected with filter circuit and FPGA portion；

Data buffer circuit is to use DDR SDRAM as memory, using AS4C32M16D1 chip, for temporarily storing data, As the buffering of data, it is connected with FPGA portion；

The SoC fpga chip that the part FPGA and ARM uses Altera to embed Cortex-A9 hard nucleus management device forms, Altera base It is seamlessly connected in the hard nucleus management device system of ARM by high broadband interconnection and FPGA hardware part, including FPGA and ARM two Part；Wherein FPGA portion uses the EPCQ256 chip of CycloneV series, the realization and digital signal for logic function Processing, is connected with signal acquisition circuit, data buffer circuit；The part ARM uses 800MHZ double-core ARM Cortex-A9 MPCore realizes self-correcting as processor, for being embedded in Self-Tuning Algorithm, with signal output apparatus, data storage circuitry phase Even；

Signal output apparatus is completed by D/A converter, using DAC7615 chip, for by arm processor treated electric current number Word signal is converted to analog signal, is connected with the part ARM and signal display circuit；

Signal display circuit uses the oscillograph of DS1102E model, for showing the current waveform after correcting with measuring system, with Signal output apparatus is connected；

Data storage circuitry is to use FLASH as memory, using the S29GL512P chip of Nor FLASH, for storing ARM Data and program in processor, when carrying out power on operation, arm processor can read configuration data from FLASH automatically, with The part ARM is connected；

Key control circuit is connected for the restarting to system with data processing circuit using reset key.

2. a kind of current transformer self correcting system according to claim 1, it is characterised in that: the FPGA portion packet Include analog-to-digital conversion interface unit, programmable logic cells, phase locked-loop unit, in-line memory, reset unit；

The part ARM includes DDR₃The expanding element of SDRAM, LTC2 × 7, reset unit, Bus Interface Unit.