CN209544314U - 一种静电防护阵列芯片封装结构 - Google Patents

一种静电防护阵列芯片封装结构 Download PDF

Info

Publication number
CN209544314U
CN209544314U CN201920222257.XU CN201920222257U CN209544314U CN 209544314 U CN209544314 U CN 209544314U CN 201920222257 U CN201920222257 U CN 201920222257U CN 209544314 U CN209544314 U CN 209544314U
Authority
CN
China
Prior art keywords
array chip
electrostatic protection
pin
wire frame
protection array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201920222257.XU
Other languages
English (en)
Inventor
王海青
许贵铮
刘伟强
刘杰丰
李章夏
陈泽龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Gaote Microelectronics Co Ltd
Original Assignee
Shenzhen Gaote Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Gaote Microelectronics Co Ltd filed Critical Shenzhen Gaote Microelectronics Co Ltd
Priority to CN201920222257.XU priority Critical patent/CN209544314U/zh
Application granted granted Critical
Publication of CN209544314U publication Critical patent/CN209544314U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

一种静电防护阵列芯片封装结构,本实用新型涉及电子设备技术领域;它包含金属引线框架、绝缘固晶胶、静电防护阵列芯片、金属导线和树脂塑料外封;静电防护阵列芯片通过绝缘固晶胶固定在金属引线框架上,且静电防护阵列芯片通过金属导线与金属引线框架电性连接,树脂塑料外封包设在由金属引线框架、绝缘固晶胶、静电防护阵列芯片、金属导线组成的一个整体的外部。减小后续应用在超高清多媒体设备印刷线路板上弯曲走线的数量;电容低、弯曲走线数量少,其保证了超高清多媒体数据传输完整性,实用性更强。

Description

一种静电防护阵列芯片封装结构
技术领域
本实用新型涉及电子设备技术领域,具体涉及一种静电防护阵列芯片封装结构。
背景技术
近年来高清及超高清多媒体设备市场呈现快速增长的趋势,人们对超高清图像的追求也日趋明显;高清多媒体接口则是高清及超高清多媒体设备必备的接口;高清多媒体接口的版本也从标准版1.0升级至超高速版2.1,其传输带宽可达48.0Gbit/s,数据传输速度非常快,而现有在高速传输线上静电防护器件过大的电容及封装结构容易引起数据丢失。
综上所述,为了保证超高清多媒体设备上高清多媒体接口数据传输的完整性,有必要提出一种新的应用于超高清多媒体设备的静电防护阵列芯片封装结构。
发明内容
本实用新型的目的在于针对现有技术的缺陷和不足,提供一种结构简单,设计合理、使用方便的静电防护阵列芯片封装结构,减小后续应用在超高清多媒体设备印刷线路板上弯曲走线的数量;电容低、弯曲走线数量少,其保证了超高清多媒体数据传输完整性,实用性更强。
为实现上述目的,本实用新型采用的技术方案是:它包含金属引线框架、绝缘固晶胶、静电防护阵列芯片、金属导线和树脂塑料外封;静电防护阵列芯片通过绝缘固晶胶固定在金属引线框架上,且静电防护阵列芯片通过金属导线与金属引线框架电性连接,树脂塑料外封包设在由金属引线框架、绝缘固晶胶、静电防护阵列芯片、金属导线组成的一个整体的外部。
进一步地,所述的静电防护阵列芯片正面的电性功能点分别通过金属导线与金属引线框架上的引脚1、引脚2、引脚3、引脚8、引脚4和引脚5电性连接,引脚3和引脚8为接地端,两者通过金属导线与静电防护阵列芯片正面上的其中一个的电性功能点电性连接。
采用上述结构后,本实用新型有益效果为:本实用新型所述的一种静电防护阵列芯片封装结构,减小后续应用在超高清多媒体设备印刷线路板上弯曲走线的数量;电容低、弯曲走线数量少,其保证了超高清多媒体数据传输完整性,实用性更强,本实用新型具有结构简单,设置合理,制作成本低等优点。
附图说明
为了更清楚地说明本实用新型实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本实用新型的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本实用新型的结构示意图。
图2是本实用新型的剖面图。
附图标记说明:
金属引线框架101、绝缘固晶胶102、静电防护阵列芯片103、金属导线104、树脂塑料外封105。
具体实施方式
下面结合附图对本实用新型作进一步的说明。
参看如图1和图2所示,本具体实施方式采用的技术方案是:它包含金属引线框架101、绝缘固晶胶102、静电防护阵列芯片103、金属导线104和树脂塑料外封105;静电防护阵列芯片103通过绝缘固晶胶102固定在金属引线框架101上,且静电防护阵列芯片103通过金属导线104与金属引线框架101电性连接,树脂塑料外封105包设在由金属引线框架101、绝缘固晶胶102、静电防护阵列芯片103、金属导线104组成的一个整体的外部;所述的静电防护阵列芯片103正面的电性功能点分别通过金属导线104与金属引线框架101上的引脚1、引脚2、引脚3、引脚8、引脚4和引脚5电性连接,引脚3和引脚8为接地端,两者通过金属导线104与静电防护阵列芯片103正面上的其中一个的电性功能点电性连接;所述的金属引线框架101上的引脚6、引脚7、引脚9和引脚10空置。
本具体实施方式的工作原理:所述静电防护阵列芯片103的背面通过绝缘固晶胶102与所述金属引线框架101固定连接,因采用绝缘固晶胶102,所以,上述静电防护阵列芯片103与金属引线框架101之间完全隔离;由于静电防护阵列芯片103正面的各电性功能点通过金属导线104与金属引线框架101的各对应引脚1、引脚2、引脚3、引脚8、引脚4、引脚5电性连接,这样使得金属引线框架101的引脚1、2、4、5与金属引线框架101的引脚3和8(即接地端)之间的电容值减少一半,电容越低越能保证超高清多媒体数据传输完整性;空置的金属引线框架101的引脚6、引脚7、引脚9、引脚10与金属引线框架101的引脚1、引脚2、引脚4、引脚5之间形成该静电防护阵列芯片各功能脚的直通式分布,这样可以减小后续应用在超高清多媒体设备印刷线路板上弯曲走线的数量;弯曲走线数量越少越能保证超高清多媒体数据传输完整性。
采用上述结构后,本具体实施方式有益效果为:
1、通过绝缘固晶胶隔离了静电防护阵列芯片与金属引线框架的引脚3与引脚8(即,访芯片接地端)的电性连接,再通过金属导线将静电防护阵列芯片的其中一功能点与金属引线框架的引脚3与8(即,访芯片接地端)的电性连接,于此,金属引线框架的引脚1、2、4、5与金属引线框架的引脚3与8(即,访芯片接地端)之间的电容值减少一半;
2、空置金属引线框架的引脚6、7、9、10与金属引线框架的引脚1、2、4、5形成该静电防护阵列芯片各功能脚直通式分布,这样可以减小后续应用在超高清多媒体设备印刷线路板上弯曲走线的数量;电容越低、弯曲走线数量越少越能保证超高清多媒体数据传输完整性。
以上所述,仅用以说明本实用新型的技术方案而非限制,本领域普通技术人员对本实用新型的技术方案所做的其它修改或者等同替换,只要不脱离本实用新型技术方案的精神和范围,均应涵盖在本实用新型的权利要求范围当中。

Claims (3)

1.一种静电防护阵列芯片封装结构,其特征在于:它包含金属引线框架(101)、绝缘固晶胶(102)、静电防护阵列芯片(103)、金属导线(104)和树脂塑料外封(105);静电防护阵列芯片(103)通过绝缘固晶胶(102)固定在金属引线框架(101)上,且静电防护阵列芯片(103)通过金属导线(104)与金属引线框架(101)电性连接,树脂塑料外封(105)包设在由金属引线框架(101)、绝缘固晶胶(102)、静电防护阵列芯片(103)、金属导线(104)组成的一个整体的外部。
2.根据权利要求1所述的一种静电防护阵列芯片封装结构,其特征在于:所述的静电防护阵列芯片(103)正面的电性功能点分别通过金属导线(104)与金属引线框架(101)上的引脚1、引脚2、引脚3、引脚8、引脚4和引脚5电性连接,引脚3和引脚8为接地端,两者通过金属导线(104)与静电防护阵列芯片(103)正面上的其中一个的电性功能点电性连接。
3.根据权利要求1所述的一种静电防护阵列芯片封装结构,其特征在于:所述的金属引线框架(101)上的引脚6、引脚7、引脚9和引脚10空置。
CN201920222257.XU 2019-02-22 2019-02-22 一种静电防护阵列芯片封装结构 Active CN209544314U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201920222257.XU CN209544314U (zh) 2019-02-22 2019-02-22 一种静电防护阵列芯片封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201920222257.XU CN209544314U (zh) 2019-02-22 2019-02-22 一种静电防护阵列芯片封装结构

Publications (1)

Publication Number Publication Date
CN209544314U true CN209544314U (zh) 2019-10-25

Family

ID=68273694

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201920222257.XU Active CN209544314U (zh) 2019-02-22 2019-02-22 一种静电防护阵列芯片封装结构

Country Status (1)

Country Link
CN (1) CN209544314U (zh)

Similar Documents

Publication Publication Date Title
CN103579857B (zh) 高频信号双层排线转接卡
CN203934275U (zh) 一种板卡防静电及接地装置
CN209544314U (zh) 一种静电防护阵列芯片封装结构
CN107403659B (zh) Ffc线结构及其制造方法
CN210805279U (zh) Ffc排线
CN202353916U (zh) 一种多层柔性印刷电路板的改进结构
CN202103199U (zh) 一种hdmi dip型连接器
CN208608501U (zh) Gis设备与电缆终端连接用软导体
CN206077827U (zh) 柔性电路板转接片
CN106878129A (zh) 一种即插即用的货架标签组网连接系统及方法
CN203574934U (zh) 一种pcb板
CN206322130U (zh) 电子设备、触控显示屏、触控组件及其触控导电膜
CN205645715U (zh) 一种小型断路器
CN209517057U (zh) 一种光伏线盒及一种光伏组件
CN206962207U (zh) 一种笔记本电脑麦克风信号连接线束
CN207490197U (zh) 一种耐弯折的ffc排线
CN208142397U (zh) 一种开关插座
CN208538702U (zh) 一种应用于igbt的吸收电容结构
CN207070063U (zh) 一种以太网口的pcb
CN202308357U (zh) 一种接线排
CN206991335U (zh) 指纹识别模组及终端设备
CN206619774U (zh) 一种计算机usb接口增加装置
CN205647633U (zh) 一种移动终端接地结构和移动终端
CN206118162U (zh) 一种fpc锡点接地结构以及fpc模组
CN205509148U (zh) 双usb接线端子

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant