CN209517309U - A kind of character automatic identification counting device based on machine vision - Google Patents

Abstract

The utility model provides a kind of character automatic identification counting device based on machine vision, including FPGA development board, cmos image acquisition module, display module and system power supply module, the counting device is using FPGA development board as master controller, ambient enviroment is acquired in real time using cmos image acquisition module cooperation FPGA development board and is stored in SDRAM memory, reading by FPGA development board to image data in SDRAM memory, image preprocessing is carried out to image, such as binaryzation, gray processing and edge detection etc., finally image is carried out template comparison and identifies and in real time show processing result image and count results on the display module, design is scientific and reasonable for the utility model, it is practical, degree of intelligence is high, it is low in cost controllable, it can promote the use of.

Description

A kind of character automatic identification counting device based on machine vision

Technical field

The utility model relates to a kind of technique devices, and in particular to a kind of character automatic identification counting based on machine vision Device.

Background technique

Nowadays increasingly mature with machine recognition technology, machine recognition also everywhere may be used in our daily life See.Everybody common are two dimensional code and identifies, fingerprint recognition, Car license recognition etc., these technologies are quite mature.There are also nowadays Compare fiery Unmanned Systems.There are many machine recognition technologies in Unmanned Systems, including to people or mobile object Identification, landmark identification and range estimation etc..And in various identifying systems, the identification to number is essential.Number exists Our human worlds are ubiquitous.Identification based on machine vision is the only way which must be passed for moving towards artificial intelligence, and the identification of character is just It is the stepping-stone to success on this road.

Machine vision is more the application about industrial automation at home, and it is widely doctor that another application is relatively more Treat equipment application field.The application of the current comparative maturity of machine vision is also concentrated mainly on positioning, OCR and feature whether there is or not field, Being one as open defect detection has very big detection demand, but is also difficult to accomplish the detection application field of batch application. FPGA becomes another very burning hot digit recognition method with its quick parallel processing advantage, its processing speed is DSP Much too late Deng control chip institute, processing speed is fastly, processing capacity excellent is enough to allow people's sidelong glance.

The Chinese name of FPGA (Field-Programmable Gate Array) is field programmable gate array.It is wrapped The programming devices such as GAL, CPLD and PAL are included, are a especially high performance new products.FPGA is a kind of body of hardware reconfiguration Architecture is used as the small lot substitute of special chip throughout the year, however in recent years in the data of the companies such as Microsoft, Baidu Heart large scale deployment, to provide powerful computing capability and enough flexibilities simultaneously.

FPGA has very strong flexible ability and can be carried out the real-time pipeline operation with behavior unit.Meanwhile FPGA itself is fast-developing, and integrated level, operating rate is getting faster, and resource is more and more abundant, and function is also more and more. With the continuous development of EDA technology, FPGA is widely used, this is depending on its real hardware concurrent and greatly Flexibility, and the huge advantage that can quickly dominate the market.In conclusion before machine vision is combined application with FPGA Scape is very wide.

Utility model content

It is a kind of based on machine the technical problem to be solved by the utility model is in view of the above shortcomings of the prior art, provide The character automatic identification counting device of device vision, design is scientific and reasonable for the counting device, and integrated level is high, can by machine vision and FPGA is combined, and has powerful computing capability and flexibility, it is fast that identification counts intelligence degree height, speed.

In order to solve the above technical problems, the technical solution adopted in the utility model is: a kind of character based on machine vision Automatic identification counting device, which is characterized in that including cmos image acquisition module, the system electricity being connect respectively with FPGA development board Source module and display module；The FPGA development board includes the programming connecting respectively with the I/O BANK of EP4CE10F17C8 chip Configuration circuit, clock circuit and SDRAM memory circuit；The cmos image acquisition module uses the monocular of model OV5640 500W pixel camera head, interior one 1/4 inch of the CMOS QSXGA configured with the production of OmniVision company of the camera Imaging sensor；The system power supply module includes three kinds of kernel power supply, the power supply of PLL analog circuit and IO BANK power supply power supplies Module；The display module includes LCD1602 liquid crystal display, charactron and 5 cun of RGB LCD touch displays.

Preferably, the BANK1 and BANK2 of the EP4CE10F17C8 chip connect AD/DA circuit and LCD1602 liquid crystal Display；BANK3 connects SDRAM memory circuit and CMOS acquisition module with BANK4；BANK5 connects RGB liquid with BANK6 Brilliant touch display and clock circuit；BANK7 connects RTL8201 ethernet circuit and charactron with BANK8.

Preferably, the programming configuration circuit is the special series arrangement equipment configured to FPGA development board, is burnt It writes configuration circuit and is provided with JTAG configuration and JIC two kinds of configuration methods of configuration, the JTAG configuration method is by configuration bit-stream It directly just downloads in EP4CE10F17C8 chip, in FPGA power-up state, FPGA will retain this configuration, and logic Function can also operate normally.But if configuration information will be lost, again right after can powering on if necessary after power-off It is configured；The JIC is configured to the crossover tool carried by Quartus software, and the .sof file that compiling is generated turns It is changed to .jic file, then downloads to EPCS device by JTAG mouthfuls, data can be made not lose under power blackout situation.

Preferably, the clock circuit is designed as three tunnels, and the first via has source crystal oscillator offer, secondary route by onboard 50MHz Coaxial interface input, third road are integrated in CMOS camera interface, and it is dedicated that three road clock passes through Cyclone IV E Clock pins inputted.Three road clocks pass through the dedicated clock pins of Cyclone IV E and are inputted, and guarantee in this way Best clock quality, and guarantee that corresponding global clock chain road can be configured to.

Preferably, the GPIO compatible with friendly brilliant science and technology DE2 development board that the FPGA development board provides 1 40Pin is marked Quasi- IDC3-40 interface, the interface have the FPGA of 36 pin connection Cyclone IV E types, and the interface outputs DC+ 5V (VCC5) and DC+3.3V (VCC3P3), the interface output two grounding pins.

Preferably, the memory of the maximum mountable 256Mb of the SDRAM memory circuit, the SDRAM memory circuit The data/address bus bit wide being connected with EP4CE10F17C8 chip is 16bit, and SDRAM memory circuit is powered using 3.3V.

Preferably, there are three touch key pin, three touch key pins point for setting on the FPGA development board It is not connected with PIN-M16 pin, PIN-E15 pin, PIN-E16 pin and is connected with pull-up resistor, is not pressing key pressing When, each key end output is high level, and when pressing key pressing, the key end being pressed will export low level To FPGA pin；There are four red LEDs to debug lamp for the FPGA development board setting, and the LED debugging lamp is managed with PIN-A2 respectively Foot, PIN-B3 pin, PIN-A4 pin, the connection of PIN-A3 pin, when FPGA exports low level, LED is lighted, when LED is defeated Out when high level, LED light is extinguished.

Preferably, 1/4 inch of CMOS QSXGA that cmos image acquisition module is produced using OmniVision company And resolution ratio is the imaging sensor of 2592*1944.OV5640 module is integrated with LDO, and 3~5V of single supply power supply can work, Highest 500W pixel image fan-out capability, the double LED light supplement lamps of band, supports automatic focusing function, has very high cost performance. OV5640 chip is mapped to OV_D7~OV_D0 in mould group using D9~D2 most-significant byte data line, on the OV5640 chip CMOS_SCLK and CMOS_SDA is connected with the pull-up resistor of 2~10K.

Preferably, supply voltage needed for Cyclone IV E FPGA kernel is 1.2V, maximum current needed for Core Operational with The design work frequency and resource occupation that are run on chip and difference.It is soft that Quartus can be used in the power consumption of specific each design The power consumption analysis tool " PowerPlay Power Analyzer Tool " that part provides is analyzed.The kernel power supply module Using NCP1529 typical application circuit, DCDC reducing transformer is used in the NCP1529 typical application circuit, NCP1529 is typical The input voltage range of application circuit is 2.7V-5.5V, output voltage range 0.9V-3.9V；The PLL analog circuit supplies Electric module uses EP4CE10；The I/O port of each component is divided into 8 groups, and each group is IO a Bank, the same Bank In all IO power supply it is identical, the IO of each Bank power supply can be different.

Compared with the prior art, the utility model has the following advantages:

1, design is scientific and reasonable for the utility model, and integrated level is high, can combine machine vision and FPGA, there is powerful meter Calculation ability and flexibility, it is fast that identification counts intelligence degree height, speed.

2, the utility model devises one using the FPGA of the EP4CE10F17C8 series of Cyclone IV E type as core Heart processor can reach acquisition video image and image procossing and real-time tracing target character in real time and realize the function that identification counts Can, design is rationally easy, and integrated level is high.

3, the utility model selects 5 cun of liquid crystal touch display screens of RGB screen, driving method and driver' s timing and tradition VGA Display is completely the same, is all mainly made of VS, HS, R, G, B equisignal line, and drive code set can directly lead to VGA With only individual time sequence parameter numerical value are different, can show colour bar, waveform, text and camera realtime graphic.

The utility model is described in further detail with reference to the accompanying drawings and examples.

Detailed description of the invention

Fig. 1 is the schematic block circuit diagram of the utility model.

Fig. 2 is the system flow chart of the utility model.

Fig. 3 is the connection circuit diagram of EP4CE10F17C8 chip and clock circuit in the utility model.

Fig. 4 is kernel power supply circuit in the utility model.

Fig. 5 is PLL analog circuit power supply circuit in the utility model.

Fig. 6 is IO BANK power supply circuit in the utility model

Specific embodiment

As shown in Figure 1, the utility model includes including the cmos image acquisition mould connecting respectively with FPGA development board conducting wire Block, system power supply module and display module；The FPGA development board includes the I/O BANK with EP4CE10F17C8 chip respectively Programming configuration circuit, clock circuit and the SDRAM memory circuit of connection；The cmos image acquisition module uses model The monocular 500W pixel camera head of OV5640, interior one 1/4 inch configured with the production of OmniVision company of the camera CMOS QSXGA imaging sensor；The system power supply module includes kernel power supply, the power supply of PLL analog circuit and IO BANK It powers three kinds of power supply modules；The display module includes that LCD1602 liquid crystal display, charactron and 5 cun of RGB LCD touches are aobvious Show device.

In the present embodiment, the BANK1 and BANK2 of the EP4CE10F17C8 chip connect AD/DA circuit and LCD1602 Liquid crystal display；BANK3 connects SDRAM memory circuit and CMOS acquisition module with BANK4；BANK5 connects RGB with BANK6 LCD touch display and clock circuit；BANK7 connects RTL8201 ethernet circuit and charactron with BANK8.

In the present embodiment, the programming configuration circuit is that the special series arrangement configured to FPGA development board is set Standby, programming configuration circuit is provided with JTAG configuration and JIC configures two kinds of configuration methods, and the JTAG configuration method is that will configure ratio Spy's stream directly just downloads in EP4CE10F17C8 chip, and in FPGA power-up state, FPGA will retain this configuration, and patrol Collecting function can also operate normally.But if configuration information will be lost, after can powering on if necessary again after power-off It is configured；The JIC is configured to the crossover tool carried by Quartus software, the .sof file that compiling is generated .jic file is converted to, then downloads to EPCS device by JTAG mouthfuls, data can be made not lose under power blackout situation.

As shown in figure 3, the clock circuit is designed as three tunnels in the present embodiment, the first via has source crystal oscillator by onboard 50MHz It provides, secondary route coaxial interface input, third road is integrated in CMOS camera interface, and three road clock passes through The dedicated clock pins of Cyclone IV E are inputted.Three road clocks pass through the dedicated clock pins of Cyclone IV E It is inputted, this ensure that best clock quality, and guarantee that corresponding global clock chain road can be configured to.

In the present embodiment, the FPGA development board provides the compatible with friendly brilliant science and technology DE2 development board of 1 40Pin The IDC3-40 interface of GPIO standard, the interface have the FPGA of 36 pin connection Cyclone IV E types, and the interface is defeated DC+5V (VCC5) and DC+3.3V (VCC3P3) are gone out, the interface outputs two grounding pins.

In the present embodiment, the memory of the maximum mountable 256Mb of the SDRAM memory circuit, the SDRAM memory The data/address bus bit wide that circuit is connected with EP4CE10F17C8 chip is 16bit, and SDRAM memory circuit is powered using 3.3V.

In the present embodiment, there are three touch key pins, three touch keys to draw for setting on the FPGA development board Foot is connected with PIN-M16 pin, PIN-E15 pin, PIN-E16 pin respectively and is connected with pull-up resistor, presses in no key When lower, each key end output is high level, and when pressing key pressing, the key end being pressed will export low Level is to FPGA pin；FPGA development board setting debugs lamp there are four red LED, the LED debugging lamp respectively with PIN- A2 pin, PIN-B3 pin, PIN-A4 pin, the connection of PIN-A3 pin, when FPGA exports low level, LED is lighted, when When LED exports high level, LED light is extinguished.

In the present embodiment, cmos image acquisition module is the 1/4 inch of CMOS produced using OmniVision company The imaging sensor that QSXGA and resolution ratio are 2592*1944.OV5640 module is integrated with LDO, 3~5V of single supply power supply Work, highest 500W pixel image fan-out capability, the double LED light supplement lamps of band support automatic focusing function, have very high sexual valence Than.OV5640 chip uses D9~D2 most-significant byte data line, the OV_D7~OV_D0 being mapped in mould group, the OV5640 chip On CMOS_SCLK and CMOS_SDA be connected with the pull-up resistor of 2~10K.

As shown in figure 4, supply voltage needed for Cyclone IV E FPGA kernel is 1.2V, Core Operational in the present embodiment Required maximum current difference with the design work frequency and resource occupation run on chip.The power consumption of specific each design can be with The power consumption analysis tool " PowerPlay Power Analyzer Tool " provided using Quartus software is analyzed.It is described Kernel power supply module uses NCP1529 typical application circuit, uses DCDC reducing transformer in the NCP1529 typical application circuit, The input voltage range of NCP1529 typical application circuit is 2.7V-5.5V, output voltage range 0.9V-3.9V.Output voltage When for 1.2V, realize that R23 and R25 are feedback resistance, setting two from 3.3V power supply to the conversion of 1.2V power supply using NCP1529 Person's resistance value is 100K, and stable 1.2V output can be realized.In order to realize between power supply and actual FPGA power pin every From 1.2V output end also uses a power magnetic bead, when debugging hardware needs to disconnect 1.2V from FPGA pin, only Need to dismantle FB4.

As shown in figure 5, PLL analog circuit power supply module needs two kinds of power supplies, respectively analog portion and numerical portion is supplied Electricity, the PLL power supply that the PLL analog circuit power supply module uses EP4CE10, EP4CE10 to have 2 PLL analog circuits are drawn Foot.

As shown in fig. 6, the I/O port of each component is divided into 8 groups in IO BANK power supply, each group is an IO All IO power supply in Bank, the same Bank is identical, and the IO power supply of each Bank can be different.Directly being switched using wire jumper is A kind of easy mode, is suitable for the fewer situation of power switching option, and the switching mode that another kind is recommended is using can Volt circuit is downgraded, switches obstructed partial pressure feedback resistance directly by wire jumper the output valve of reduction voltage circuit is arranged.

As shown in Fig. 2, when the utility model is used, character (0-9) information is obtained by OV5640 camera, by FPGA Development board carries out video image processing, gray proces, binary conversion treatment, median filtering and edge detection, is then opened again by FPGA Hair plate carries out and character model library is matched, probabilistic algorithm, finally shows processing result image in LCD1602 liquid crystal Show device and RGB LCD touch display, count results are shown on charactron.

The above is only the preferred embodiment of the utility model, not imposes any restrictions to the utility model.All Factually with new technique any simple modification, change and equivalence change substantially to the above embodiments, this is still fallen within In the protection scope of utility model technical solution.

Claims (9)

1. a kind of character automatic identification counting device based on machine vision, which is characterized in that including respectively with FPGA development board The cmos image acquisition module for collecting character picture information of connection, the system power supply module powered for entire counting device With the display module of data information after display processing；The FPGA development board includes the I/O with EP4CE10F17C8 chip respectively Programming configuration circuit, clock circuit and the SDRAM memory circuit of BANK connection；The cmos image acquisition module is camera shooting Head；The system power supply module includes kernel power supply, the power supply of PLL analog circuit and IO BANK three kinds of power supply modules of power supply；It is described Display module includes display and charactron.

2. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that institute The monocular 500W pixel camera head that cmos image acquisition module uses model OV5640 is stated, is provided with CMOS in the camera QSXGA imaging sensor；Display in the display module includes that LCD1602 liquid crystal display and 5 cun of RGB LCD touches are aobvious Show device.

3. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that institute The BANK1 and BANK2 for stating EP4CE10F17C8 chip connect AD/DA circuit and LCD1602 liquid crystal display；BANK3 and BANK4 Connect SDRAM memory circuit and CMOS acquisition module；BANK5 connects RGB LCD touch display and clock electricity with BANK6 Road；BANK7 connects RTL8201 ethernet circuit and charactron with BANK8.

4. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that institute It states clock circuit and is designed as three tunnels, the first via has source crystal oscillator offer, the input of secondary route coaxial interface, third by onboard 50MHz Road is integrated in CMOS camera interface, and it is defeated that three road clock passes through the dedicated clock pins progress of Cyclone IV E Enter.

5. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that institute The IDC3-40 interface that FPGA development board provides the GPIO standard compatible with DE2 development board of 1 40Pin is stated, the interface has The FPGA of 36 pin connection Cyclone IV E types, the interface output DC+5V (VCC5) and DC+3.3V (VCC3P3), The interface outputs two grounding pins.

6. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that institute State the memory of the maximum mountable 256Mb of SDRAM memory circuit, the SDRAM memory circuit and EP4CE10F17C8 core The connected data/address bus bit wide of piece is 16bit, and SDRAM memory circuit is powered using 3.3V.

7. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that institute Setting is stated on FPGA development board there are three touch key pin, three touch key pins respectively with PIN-M16 pin, PIN-E15 pin, PIN-E16 pin are connected and are connected with pull-up resistor, and there are four red LED tune for the FPGA development board setting Lamp is tried, the LED debugging lamp is connect with PIN-A2 pin, PIN-B3 pin, PIN-A4 pin, PIN-A3 pin respectively.

8. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that Chip in OV5640 uses D9~D2 most-significant byte data line, the OV_D7~OV_D0 being mapped in mould group, the OV5640 chip On CMOS_SCLK and CMOS_SDA be connected with the pull-up resistor of 2~10K.

9. a kind of character automatic identification counting device based on machine vision according to claim 1, which is characterized in that institute It states kernel power supply module and uses NCP1529 typical application circuit, be depressured in the NCP1529 typical application circuit using DCDC Device, the input voltage range of NCP1529 typical application circuit are 2.7V-5.5V, output voltage range 0.9V-3.9V；It is described PLL analog circuit power supply module uses EP4CE10；The I/O port of each component is divided into 8 groups, and each group is an IO All IO power supply in Bank, the same Bank is identical, and the IO power supply of each Bank is same or different.