CN209496624U - Memory body hot-wire array - Google Patents
Memory body hot-wire array Download PDFInfo
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- CN209496624U CN209496624U CN201920429426.7U CN201920429426U CN209496624U CN 209496624 U CN209496624 U CN 209496624U CN 201920429426 U CN201920429426 U CN 201920429426U CN 209496624 U CN209496624 U CN 209496624U
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Abstract
A kind of memory body hot-wire array includes the first memory array, the second memory array and multiple first shared conductive pads.First memory array includes a plurality of first bit line and a plurality of first word-line.Second memory array is adjacent with the first memory array, and includes a plurality of second bit line and a plurality of second word-line.Each first shared conductive pad has first end and second end, and first end and second end are respectively coupled to the first bit line and second bit line, or are respectively coupled to the first word-line and the second word-line.The memory body hot-wire array of the utility model can effectively save the area of memory body test chip, and make test process more efficiently.
Description
Technical field
The utility model relates to a kind of memory body hot-wire array and its test method.
Background technique
Memory body is the semiconductor element to store data or data, can be divided mainly into non-volatility memory and volatilization
Two kinds of memory body of property.With flourishing for science and technology, industry also gradually promotes the demand of memory body, such as high-reliability,
High erasable number, quick storage speed and large capacity etc..Therefore, semiconductor industry ongoing effort develops various technologies to contract
Subtract component size, and increases the component density of memory body.
In the prior art, as shown in Figure 1A, wafer contain multiple Standard memory product chip Cp1, Cp2,
Cp4.In order to further appreciate that the characteristic of the memory cell in memory chip, it is brilliant that at least one test can be set in wafer
Piece (Test Chip), such as test chip Cp3, and it includes multiple memory body hot-wire array A11, Ax1, A1y, Axy etc..
Figure 1B is the partial enlargement diagram that chip Cp3 is tested in Figure 1A.As shown in Figure 1B, memory body hot-wire array A11,
Each of A12, A21, A22 include memory cell array 10, and memory cell array 10 includes multiple memory cells, example
Such as, each memory cell array 10 may include 100 memory cells.Each memory cell array 10 has respective test
Pad, can access each independent memory cell in memory cell array 10, to detect the characteristic of memory cell.To have
For the memory cell array of 100 memory cells, testing cushion at least need comprising 10 character signal pads (such as conductive pad 1A~
1L) and 10 bit signal pads (such as conductive pad 2A~2L), to access 100 independent memory elements in memory cell array
Part, and detect its characteristic.
In order to obtain more memory cell data, it is necessary to more memory cells be arranged in test chip Cp3.Cause
This, it is one of current technical problem to be solved that more memory cells how are accommodated in the confined space of test chip Cp3.
In addition, in the prior art, measure a large amount of memory cell and need the more long testing time, thus how to reduce the survey formula time with
Promote testing efficiency and technical problem to be solved.
Utility model content
Various embodiments according to the present utility model provide a kind of memory body hot-wire array, include the first memory body battle array
Column, the second memory array and multiple first shared conductive pads.First memory array includes a plurality of first bit line and more
The first word-line of item.Second memory array is adjacent with the first memory array, and the second memory array includes a plurality of second
Bit line and a plurality of second word-line.Each first shared conductive pad has first end and second end, first end and second end point
It is not coupled to the first bit line and second bit line, or is respectively coupled to the first word-line and the second word-line.
Certain embodiments according to the present utility model, the first shared conductive pad are located at the first memory array and the second note
Recall between volume array.
Certain embodiments according to the present utility model, memory body hot-wire array further include multiple first conductive pads and are coupled to
First memory array and multiple second conductive pads are coupled to the second memory array.First conductive pad and first share lead
Electrical pad is located at the opposite sides of the first memory array, and the second conductive pad and the first shared conductive pad are located at the second memory body battle array
The opposite sides of column.
Certain embodiments according to the present utility model, the first conductive pad are coupled to the first word-line, and first shares conduction
Pad is coupled to the first bit line and second bit line, and the second conductive pad is coupled to the second word-line.
Certain embodiments according to the present utility model, the first conductive pad are coupled to the first bit line, and first shares conduction
Pad is coupled to the first word-line and the second word-line, and the second conductive pad is coupled to second bit line.
Certain embodiments according to the present utility model, memory body hot-wire array further include third memory array and more
A second shared conductive pad.Third memory array is adjacent with the second memory array, and includes a plurality of third bit line and more
Third word-line.Multiple second shared conductive pads are between the second memory array and third memory array, wherein often
A second shared conductive pad has first end and second end, and first end and second end are respectively coupled to second bit line and third position
First line, or it is respectively coupled to the second word-line and third word-line.
Certain embodiments according to the present utility model, memory body hot-wire array further include multiple first conductive pads and multiple
Third conductive pad.First conductive pad is coupled to the first memory array, and the first conductive pad and the first shared conductive pad are located at the
The opposite sides of one memory array.Third conductive pad is coupled to third memory array, and third conductive pad and second shares
Conductive pad is located at the opposite sides of third memory array.
Certain embodiments according to the present utility model, the first conductive pad are coupled to the first word-line, third conductive pad coupling
It is connected to third bit line, and the first shared conductive pad is coupled to the first bit line and second bit line, the second shared conductive pad coupling
It is connected to the second word-line and third word-line.
Certain embodiments according to the present utility model, the first conductive pad are coupled to those the first bit lines, and third is conductive
Pad is coupled to third word-line, and the first shared conductive pad is coupled to the first word-line and the second word-line, and second shares conduction
Pad is coupled to second bit line and third bit line.
Various embodiments according to the present utility model provide a kind of memory body hot-wire array, include the first memory body battle array
Column and the second memory array.First memory array includes multiple first bit engagement pads and multiple first character engagement pads.
Second memory array includes multiple second bit engagement pads and multiple second character engagement pads.First bit engagement pad and second
Bit engagement pad is shared or the first character engagement pad is shared with the second character engagement pad.
Detailed description of the invention
When reading the attached drawing of accompanying, the various aspects of this exposure can be fully understood from narration in detailed below.It is worth noting
, according to industrial standard practice, various features are not drawn to scale.In fact, in order to clearly discuss, various spies
The size of sign can be increased or decreased arbitrarily.
Figure 1A is painted the memory body product chip and test chip top view of the prior art；
Figure 1B is the partial enlargement diagram that memory body tests chip in Figure 1A；
Fig. 2 is the memory body hot-wire array schematic diagram being painted according to the certain embodiments of the utility model；
Fig. 3 A is the schematic diagram for the phase-change memory array being painted according to the certain embodiments of the utility model；
Fig. 3 B is the schematic diagram for the phase-change memory unit being painted according to the certain embodiments of the utility model；
Fig. 4 is the memory body hot-wire array schematic diagram being painted according to the certain embodiments of the utility model；
Fig. 5 is that the memory body being painted according to the certain embodiments of the utility model tests chip upper schematic diagram.
Specific embodiment
Multiple embodiments that the utility model will be disclosed with attached drawing below, as clearly stated, in many practices
Details will be explained in the following description.It should be appreciated, however, that the details in these practices does not apply this with limitation practical new
Type.That is, the details in these practices is non-essential in the utility model some embodiments.And to ask clear
Chu's explanation, the size or thickness of element may exaggerate display, and map not according to full size.In addition, for the sake of to simplify the illustration, one
A little known usual structures will be painted in a manner of simply illustrating in the example shown with element.
Space relative terms used herein, for example, " lower section ", " under ", " top ", " on " etc., this is in order to just
Relativeness between one elements or features of narration and another elements or features, as depicted in figure.These phases spatially
True meaning to term includes other orientation.For example, when diagram spins upside down 180 degree, an element and another element it
Between relationship, may from " lower section ", " under " become " top ", " on ".In addition, spatially opposite used herein
Narration also should be explained similarly.
Fig. 2 is the schematic diagram for the memory body hot-wire array 100 being painted according to the certain embodiments of the utility model.It please join
Fig. 2 is examined, memory body hot-wire array 100 is total to comprising the first memory array 110, the second memory array 130 and multiple first
With conductive pad 12A~12L.Second memory array 130 is adjacent with the first memory array 110.In some embodiments, more
A first shared conductive pad 12A~12L is between the first memory array 110 and the second memory array 130.Above-mentioned note
Recalling volume array 110,130 may include multiple memory cells, and these memory cells are not limited to specific memory body, can
To include phase-change memory (Phase Change Memory；PCM), magnetoresistive memory body (Magnetoresistive
Random Access Memory；MRAM), resistance-type memory body (Resistive Random Access Memory；RRAM)
Etc..That is this creation conception is not limited to the form of memory body.For convenience of description, it is with phase-change memory below
Example.
Fig. 3 A is the schematic diagram for the phase-change memory array being painted according to the certain embodiments of the utility model.Fig. 3 B
For the schematic diagram for the phase-change memory unit 20 that the certain embodiments according to the utility model are painted.In certain embodiments
In, the first memory array 110 can be phase-change memory array as shown in Figure 3A.It below will be using Fig. 3 A-3B as example
Illustrate the first memory array 110.
Please refer to Fig. 3 A-3B.First memory array 110 may include multiple phase-change memory units 20, a plurality of
One bit line BL (for example, BL1~BL10) and a plurality of first word-line WL (for example, WL1~WL10).Each phase-change memory
Unit 20 is electrically connected an a corresponding word-line WL and bit line BL.In certain embodiments, word-line WL can be waited
Current potential is connected to character engagement pad, and bit line BL can be with equipotential link to bit engagement pad.Phase-change memory unit 20 can
Think any of phase change memory unit.As shown in Figure 3B, phase-change memory unit 20 may include transistor T1 and
Phase change memory cell PCM, the wherein gate of word-line WL connection transistor T1, phase change memory cell PCM connection bit line
BL。
In certain embodiments, the first memory array 110 may include the phase-change memory array of 10x10, that is, wrap
Containing 100 phase-change memory units 20.It will be understood that phase-change memory array shown in Fig. 3 A is merely illustrative, this is practical
It is novel without being limited thereto.In other embodiments, the first memory array 110 may include any number of phase-change memory list
Member 20.In other embodiments, the first memory array 110 also may include the memory array and memory body of other forms
Unit.
Please continue to refer to Fig. 2.In some embodiments, the second memory array 130 can be with the first memory array
110 is same or similar.That is, in certain embodiments, the second memory array 130 can be phase change shown in Fig. 3 A
Memory array, and include multiple phase-change memory units 20, a plurality of second bit line BL and a plurality of second word-line WL.More
Specifically, the second memory array 130 may include the memory cell of quantity identical as the first memory array 110, phase
With the bit line and word-line of quantity.In other embodiments, the note of the second memory array 130 or other forms
Recall volume array.
Multiple first shared conductive pad 12A~12L are respectively provided with first end 121 and second end 122.In certain embodiments
In, first end 121 can be coupled to the first bit line BL of the first memory array 110, and second end 122 can be coupled to second
The second bit line BL of memory array 130.In other embodiments, first end 121 can be coupled to the first memory body battle array
First word-line WL of column 110, second end 122 can be coupled to the second word-line WL of the second memory array 130.It is detailed
It says, in some embodiments, the first end 121 of the first shared conductive pad 12L can pass through 210 equipotential link of conducting wire to
A corresponding first bit line BL in one memory array 110, and its second end 122 can be connected by 220 equipotential of conducting wire
It is connected to corresponding second bit line BL in the second memory array 130.Alternatively, in other embodiments, first shares
The first end 121 of conductive pad 12L can be by 210 equipotential link of conducting wire into the first memory array 110 corresponding one
First word-line WL, and its second end 122 can be corresponding into the second memory array 130 by 220 equipotential link of conducting wire
A second word-line WL.
Please continue to refer to Fig. 2.In some embodiments, memory body hot-wire array 100 further includes multiple first conductive pads
11A~11L and multiple second conductive pad 13A~13L.As shown in Fig. 2, each of first conductive pad 11A~11L is coupled to
First memory array 110, and the shared conductive pad 12A~12L of first conductive pad 11A~11L and first is located at the first memory body
The opposite sides of array 110.Each of second conductive pad 13A~13L is coupled to the second memory array 130, and second
The shared conductive pad 12A~12L of conductive pad 13A~13L and first is located at the opposite sides of the second memory array 130.Certain
In embodiment, first conductive pad 11A~11L can be coupled to corresponding first word-line WL in the first memory array 110,
First shared conductive pad 12A~12L is coupled to corresponding first bit line BL and the second memory body in the first memory array 110
Corresponding second bit line BL in array 130, and second conductive pad 13A~13L is coupled in the second memory array 130 and corresponds to
The second word-line WL.In other embodiments, first conductive pad 11A~11L can be coupled to the first memory array 110
In corresponding first bit line BL, first shared conductive pad 12A~12L is coupled to corresponding in the first memory array 110
Corresponding second word-line WL in one word-line WL and the second memory array 130, and second conductive pad 13A~13L is coupled to
Corresponding second bit line BL in second memory array 130.
In detail, the first bit line of each BL in the first memory array 110 can pass through conducting wire 212 etc. respectively
Current potential is connected in first conductive pad 11A~11L corresponding one.For example, the first bit line BL10 can be with equipotential link extremely
First conductive pad 11L.The first word-line of each WL of first memory array 110 can pass through 210 equipotential of conducting wire respectively
It is connected to corresponding one first end 121 in first shared conductive pad 12A~12L.For example, the first word-line WL10 equipotential
It is connected to the first shared conductive pad 12L.
Similarly, each second bit line BL in the second memory array 130 can pass through the electricity such as conducting wire 232 respectively
Position is connected in second conductive pad 13A~13L corresponding one.For example, second bit line BL10 equipotential link is led to second
Electrical pad 13L.The second word-line of each WL of second memory array 130 can pass through 220 equipotential link of conducting wire extremely respectively
Corresponding one second end 122 in first shared conductive pad 12A~12L.For example, the second word-line WL10 equipotential link is extremely
First shared conductive pad 12L.That is, first shared conductive pad 12A~12L can simultaneously the first memory body of equipotential link
110 corresponding first word-line WL of the array and corresponding second word-line WL of the second memory array 130.For example,
The the first word-line WL10 and the second memory body of first shared conductive pad 12L while the first memory array of equipotential link 110
Second word-line WL10 of array 130.In some embodiments, memory body hot-wire array 100 can also include other elements.
For example, virtually sharing conductive pad.
In other embodiments, the first memory array 110 includes multiple first bit engagement pads and multiple first words
First engagement pad, the second memory array 130 include multiple second bit engagement pads and multiple second character engagement pads.In certain realities
It applies in example, each first bit engagement pad can distinguish equipotential link into first bit line BL1~BL10 corresponding one,
And each first character engagement pad can distinguish equipotential link into first word-line WL1~WL10 corresponding one.?
In some embodiments, it is corresponding into second bit line BL1~BL10 that each second bit engagement pad can distinguish equipotential link
One, and can to distinguish equipotential link corresponding into second word-line WL1~WL10 for each second character engagement pad
One.In certain embodiments, the first bit engagement pad and second bit engagement pad are shared.In other embodiments, the first word
First engagement pad and the second character engagement pad are shared.
It will be understood that first conductive pad 11A~11L being painted in Fig. 2, first shared conductive pad 12A~12L and second are led
The quantity and size of electrical pad 13A~13L is merely illustrative, and the utility model is without being limited thereto.It can be according to the first memory array 110 and
Memory cell number included in two memory arrays 130 be correspondingly arranged first conductive pad 11A~11L, first share lead
Electrical pad 12A~12L and second conductive pad 13A~13L.
Fig. 4 is the schematic diagram for the memory body hot-wire array 200 being painted according to the certain embodiments of the utility model.Memory
Body hot-wire array 200 can identical or phase with the element with similar elements number in memory body hot-wire array 100 shown in Fig. 2
Seemingly.Therefore, the first memory array 110, the first shared conductive pad in memory body hot-wire array 200 be will not be described in great detail below
The element and its connection relationship that 12A~12L and the second memory array 130 are included.As shown in figure 4, memory body hot-wire array
200 further include third memory array 150 and second shared conductive pad 14A~14L.
Third memory array 150 is adjacent with the second memory array 130.Third memory array 150 can be with first
Memory array 110 and the second memory array 130 are same or similar.That is, in some embodiments, third memory
Volume array 150 can be phase-change memory array shown in Fig. 3 A, (be illustrated in figure comprising multiple phase-change memory units 20
3B), a plurality of third bit line BL and a plurality of third word-line WL.In more detail, third memory array 150 may include with
The bit line and word of first memory array 110 and the memory cell of the identical quantity of the second memory array 130, identical quantity
First line.In other embodiments, third memory array 150 or the memory array of other forms.
As shown in figure 4, multiple second shared conductive pad 14A~14L are located at the second memory array 130 and third memory body
Between array 150, and each of second shared conductive pad 14A~14L has first end 141 and second end 142.Certain
In embodiment, the first end 141 of second shared conductive pad 14A~14L can be coupled to the second of the second memory array 130
Bit line BL, second end 142 can be coupled to the third bit line BL of third memory array 150.In other embodiments,
First end 141 can be coupled to the second word-line WL of the second memory array 130, and second end 142 can be coupled to third note
Recall the third word-line WL of volume array 150.
In detail, in some embodiments, the first end 141 of second shared conductive pad 14A~14L can lead to respectively
230 equipotential link of conducting wire is crossed to the corresponding second bit line BL of the second memory array 130, and second end 142 can be with
Equipotential link is distinguished to 150 corresponding third bit line BL of third memory array by conducting wire 240.Alternatively, at it
In his embodiment, the first end 141 of second shared conductive pad 14A~14L can pass through 230 equipotential link of conducting wire extremely respectively
The corresponding second word-line WL of second memory array 130, and its second end 142 can pass through the electricity such as conducting wire 240 respectively
Position is connected to 150 corresponding third word-line WL of third memory array.
Please continue to refer to Fig. 4.In some embodiments, memory body hot-wire array 200 further includes multiple first conductive pads
11A~11L and multiple third conductive pad 15A~15L.First conductive pad 11A~11L and first shared conductive pad 12A~12L
In the opposite sides of the first memory array 110.Third conductive pad 15A~15L is coupled to third memory array 150, and
The shared conductive pad 14A~14L of third conductive pad 15A~15L and second is located at the opposite sides of third memory array 150.
In some embodiments, each first conductive pad 11A~11L can pass through 212 equipotential link first of conducting wire
The corresponding first word-line WL of one of memory array 110.First shared conductive pad 12A~12L passes through 210 equipotential of conducting wire
A corresponding first bit line BL of the first memory array 110 is connected, and is remembered by 220 equipotential link second of conducting wire
The corresponding second bit line BL of one of volume array 130.Second shared conductive pad 14A~14L passes through 230 equipotential link of conducting wire
The corresponding second word-line WL of one of second memory array 130, and pass through 240 equipotential link third memory body battle array of conducting wire
The corresponding third word-line WL of one of column 150.Each third conductive pad 15A~15L passes through 252 equipotential link third of conducting wire
The corresponding third bit line BL of one of memory array 150.
In other embodiments, each first conductive pad 11A~11L can pass through 212 equipotential link first of conducting wire
The corresponding first bit line BL of one of memory array 110.First shared conductive pad 12A~12L passes through 210 equipotential of conducting wire
A corresponding first word-line WL of the first memory array 110 is connected, and is remembered by 220 equipotential link second of conducting wire
The corresponding second word-line WL of one of volume array 130.Second shared conductive pad 14A~14L passes through 230 equipotential link of conducting wire
The corresponding second bit line BL of one of second memory array 130, and pass through 240 equipotential link third memory body battle array of conducting wire
The corresponding third bit line BL of one of column 150.Each third conductive pad 15A~15L passes through 252 equipotential link third of conducting wire
The corresponding third word-line WL of one of memory array 150.
It is worth noting that, the opposite sides of second memory array 130 is multiple in memory body hot-wire array 200
First shared conductive pad 12A~12L and multiple second shared conductive pad 14A~14L.That is, the second memory array 130
In second bit line BL1~BL10 can be right into first shared conductive pad 12A~12L by 220 equipotential link of conducting wire
One answered, further first bit line BL1~BL10 of equipotential link to the first memory array 110.Also, second
Second word-line WL1~WL10 in memory array 130 can pass through 230 equipotential link of conducting wire to the second shared conductive pad
Corresponding one in 14A~14L, further the third word-line WL1 of equipotential link to third memory array 150~
WL10。
The concept of this shared conductive pad can continue to extend, however it is not limited to Fig. 2 and memory body hot-wire array shown in Fig. 4
100 and 200.Specifically, it can be arranged between two adjacent memory arrays and share conductive pad with by its bit line etc.
Current potential connection, or by its word-line equipotential link.
Fig. 5 is that the memory body being painted according to the certain embodiments of the utility model tests the upper schematic diagram of chip 300.
Memory body test chip 300 may include multiple memory body hot-wire arrays 100.In some embodiments, adjacent two notes
Recalling has space D 1 between body hot-wire array 100.In certain embodiments, space D 1 can be about 10-50 microns.For example, about
10,15,20,25,30,35,40,45 or 50 microns.It will be understood that although Fig. 5 is only painted 4 memory body hot-wire arrays 100,
The utility model is without being limited thereto.Multiple memory body hot-wire arrays 100 are arranged in the size that chip 300 can be tested according to memory body.
In other embodiments, memory body test chip 300 also may include multiple memory body hot-wire arrays 200 as shown in Figure 4.
It is shared by being arranged between adjacent memory array (for example, the first memory array 110 and second memory array 130)
The design of conductive pad can effectively save the area of memory body test chip 300.That is, in the memory body of fixed-area
It tests in chip 300, more memory cells can be accommodated for test.
Another aspect of the utility model is to provide a kind of test method of memory body hot-wire array.It please refer to Fig. 2,
The test method of memory body hot-wire array 100 includes to use the probe card comprising at least two rows of parallel probes, will be under this probe card
The shared conductive pad 12A~12L of press contacts the first conductive pad 11A~11L and first, and transmit the first electric signal to the first conductive pad
The shared conductive pad 12A~12L of 11A~11L and first is to test the first memory array 110.Then, this probe card is risen, then
It moves, be aligned and pushing probe card makes it contact first shared conductive pad 12A~12L and second conductive pad 13A~13L, and pass
The second electric signal is passed to the shared conductive pad 12A~12L of second conductive pad 13A~13L and first to test the second memory array
130.In some embodiments it is possible to be tested in the first memory array 110 and the second memory array 130 by the above method
The characteristic of each memory cell.For example, each phase transformation in the first memory array 110 of test and the second memory array 130
Change the resistance of memory cell 20.
With continued reference to FIG. 2, in other embodiments, the test method of memory body hot-wire array 100 includes using packet
Probe card pushing is made it contact first conductive pad 11A~11L, the first shared conductive pad by the probe card containing three row's parallel probes
12A~12L and second conductive pad 13A~13L.It is controlled via test software and transmits the first electric signal to the first conductive pad 11A
~11L, first shared conductive pad 12A~12L are to test the first memory array 110.The first memory array 110 is being surveyed,
After tested after software exchange, the second electric signal to second conductive pad 13A~13L, first total is controlled and transmitted via test software
With conductive pad 12A~12L to test the second memory array 130.Therefore, it is not necessary to which traveling probe card can test the first memory body
The characteristic of each memory cell, so can reduce the testing time in array 110 and the second memory array 130.Certain
In embodiment, the testing time of the first electric signal and the second telecommunications signal on a timeline is not repeated
Referring to FIG. 4, similarly, in some embodiments, the test method of memory body hot-wire array 200 includes to use
The shared conductive pad 12A~12L of press contacts the first conductive pad 11A~11L and first under the probe card of at least two rows of parallel probes, and
The first electric signal is transmitted to the shared conductive pad 12A~12L of first conductive pad 11A~11L and first to test the first memory body battle array
Column 110.Then probe card is risen, mobile and lower press contacts first share the shared conductive pad 14A of conductive pad 12A~12L and second
~14L, and the second electric signal to the first shared shared conductive pad 14A~14L of conductive pad 12A~12L and second is transmitted to test
Second memory array 130.Rise probe card again later, mobile and lower press contacts second share conductive pad 14A~14L and third
Conductive pad 15A~15L, and transmit the second electric signal to second shared conductive pad 14A~14L and third conductive pad 15A~15L with
Test third memory array 150.In this way, the first memory array 110, the second memory array 130 and third can be tested
The characteristic of each memory cell in memory array 150.Therefore three memory bodys in memory body hot-wire array 200 are being detected
When array, probe card needs pushing three times and rise and displacement twice.
In other embodiments, the test method of memory body hot-wire array 200 includes to use at least four row's parallel probes
Probe card under the first conductive pad of press contacts 11A~11L, first shared conductive pad 12A~12L, the second shared conductive pad 14A~
After 14L and third conductive pad 15A~15L, is controlled first via test software and transmit the first electric signal to the first conductive pad 11A
The shared conductive pad 12A~12L of~11L and first, to test the first memory array 110, then via the control of software, transmitting
Second electric signal to the first shared shared conductive pad 14A~14L of conductive pad 12A~12L and second, to test the second memory body battle array
Column 130.Finally third electric signal is transmitted to second shared conductive pad 14A~14L and third conductive pad via the control of software again
15A~15L, to test third memory array 150.Therefore, it is not necessary to which traveling probe card can test the first memory array
110, in the second memory array 130 and third memory array 150 each memory cell characteristic, probe card can be saved
The time with displacement is risen twice.In some embodiments, the first electric signal, the second telecommunications signal and third electric signal when
Between testing time on axis do not repeat.
As described above, embodiment according to the present utility model, is arranged between adjacent memory array and shares conduction
Pad is with its bit line of equipotential link or its word-line.The utility model is with the memory body hot-wire array for sharing conductive pad and now
Some memory body hot-wire arrays are compared, and the area of memory body test chip can be effectively saved.That is, in memory chip
In can accommodate more memory cells for test.In addition, sharing the design of conductive pad by this, and probe of arranging in pairs or groups sticks into
Row test, can save the testing time makes test process more efficiently, and can reduce the abrasion of probe.
Although the utility model is disclosed above with embodiment, so it is not intended to limit the utility model, any ripe
This those skilled in the art is known, without departing from the spirit and scope of the utility model, when can be used for a variety of modifications and variations, therefore this is practical
Novel protection scope is subject to the view scope of which is defined in the appended claims.
Claims (10)
1. a kind of memory body hot-wire array, characterized by comprising:
One first memory array includes a plurality of first bit line and a plurality of first word-line；
One second memory array is adjacent with first memory array, which includes a plurality of second bit line
And a plurality of second word-line；And
Multiple first shared conductive pads, respectively the first shared conductive pad have a first end and a second end, those first ends and
Those second ends are respectively coupled to those first bit lines and those second bit lines or those first ends and those second ends
It is respectively coupled to those first word-lines and those second word-lines.
2. memory body hot-wire array according to claim 1, which is characterized in that those first shared conductive pads be located at this
Between one memory array and second memory array.
3. memory body hot-wire array according to claim 2, which is characterized in that also include:
Multiple first conductive pads are coupled to first memory array, and those first conductive pads and those first shared conductive pads
Positioned at the opposite sides of first memory array；And
Multiple second conductive pads are coupled to second memory array, and those second conductive pads and those first shared conductive pads
Positioned at the opposite sides of second memory array.
4. memory body hot-wire array according to claim 3, which is characterized in that those first conductive pads be coupled to those
One word-line, those first shared conductive pads are coupled to those first bit lines and those second bit lines, and those second are led
Electrical pad is coupled to those the second word-lines.
5. memory body hot-wire array according to claim 3, which is characterized in that those first conductive pads be coupled to those
One bit line, those first shared conductive pads are coupled to those first word-lines and those second word-lines, and those second are led
Electrical pad is coupled to those second bit lines.
6. memory body hot-wire array according to claim 1, which is characterized in that also include:
One third memory array is adjacent with second memory array, which includes a plurality of third bit line
And a plurality of third word-line；And
Multiple second shared conductive pads, between second memory array and the third memory array, wherein respectively this
Two shared conductive pads have a first end and a second end, those first ends and those second ends are respectively coupled to those seconds
First line and those third bit lines or those first ends and those second ends be respectively coupled to those second word-lines and those
Third word-line.
7. memory body hot-wire array according to claim 6, which is characterized in that also include:
Multiple first conductive pads are coupled to first memory array, and those first conductive pads and those first shared conductive pads
Positioned at the opposite sides of first memory array；And
Multiple third conductive pads are coupled to the third memory array, and those third conductive pads and those second shared conductive pads
Positioned at the opposite sides of the third memory array.
8. memory body hot-wire array according to claim 7, which is characterized in that those first conductive pads be coupled to those
One word-line, those third conductive pads are coupled to those third bit lines, and those first shared conductive pads be coupled to those
One bit line and those second bit lines, those second shared conductive pads are coupled to those second word-lines and those third characters
Line.
9. memory body hot-wire array according to claim 7, which is characterized in that those first conductive pads be coupled to those
One bit line, those third conductive pads are coupled to those third word-lines, and those first shared conductive pads be coupled to those
One word-line and those second word-lines, those second shared conductive pads are coupled to those second bit lines and those third bits
Line.
10. a kind of memory body hot-wire array, characterized by comprising:
One first memory array includes multiple first bit engagement pads and multiple first character engagement pads；And
One second memory array includes multiple second bit engagement pads and multiple second character engagement pads；
Wherein, those the first bit engagement pads and those second bit engagement pads are shared or those the first character engagement pads with should
A little second character engagement pads are shared.
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| CN109979523A (en) * | 2019-04-01 | 2019-07-05 | 江苏时代全芯存储科技股份有限公司 | Memory body hot-wire array and its test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109979523A (en) * | 2019-04-01 | 2019-07-05 | 江苏时代全芯存储科技股份有限公司 | Memory body hot-wire array and its test method |
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