CN209345145U - Long-wave signal Full automatic timing reception device - Google Patents
Long-wave signal Full automatic timing reception device Download PDFInfo
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- CN209345145U CN209345145U CN201821949227.0U CN201821949227U CN209345145U CN 209345145 U CN209345145 U CN 209345145U CN 201821949227 U CN201821949227 U CN 201821949227U CN 209345145 U CN209345145 U CN 209345145U
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Abstract
The utility model provides a kind of long-wave signal Full automatic timing reception device, and adc circuit receives the sampling clock from FPGA；Long-wave signal exports digital medium-frequency signal after ADC is sampled, and digital medium-frequency signal is sent to FPGA, and frequency control word information is back to FPGA by the BPL signal envelope of FPGA output I/Q branch to DSP, DSP；Meanwhile FPGA sends serial time information to network port circuit, realizes time calibration in network；FPGA is connected by 14 bit parallel data interfaces with LCD and LED, and matrix keyboard is connected with FPGA and DSP respectively by serial data interface；FPGA exports the machine 1PPS signal and TOC information to man-machine interface, the final autonomous timing for realizing BPL receiver.The present invention can carry out autonomous timing to long-wave time service signal, and increase NTP/PTP time calibration in network function, have the characteristics that precision height, integrated level height, high reliablity, maintenanceability are strong, easy to use.
Description
Technical field
The invention belongs to long-wave time service fields, are related to a kind of long-wave signal reception device.
Background technique
Long-wave signal time dissemination system BPL is one of the main time service means at country, Chinese Academy of Sciences time service center, and long-wave signal covers
The entire land in lid China and offshore sea waters.Since system commencement of commercial operation, providing for all conglomeraties of Chinese national economy and department can
The time service service leaned on plays particularly important effect in the fields such as national economy and national defense construction.
Under the subsidy of the projects project such as state natural sciences fund, national time service center lasts 3 years and completes " China sieve
The research of the autonomous time service of orchid-C ", the research are contained by establishing additional modulation channel in long-wave signal time dissemination system, increasing information
Amount, thus accomplish autonomous time service and real-time broadcast correction to time signals, sophisticated systems timing function and performance.Long-wave signal is autonomous
TOC is synchronous and broadcast time encodes, and realizes the autonomous time service of long wave (the full information time encoding containing broadcast), still belongs to first in the world
Wound, this is also that international rowland-C it is expected to solve the problems, such as always.Synchronization of the research to the communication networks such as China GSM, CDMA are ensured,
It avoids relying on technical risk that the satellite navigation and positionings time dissemination system such as GPS may cause and security risk is significant；Research
Achievement can equally meet the needs of other departments such as China's electric power, traffic, have weight to the safe operation of Communication in China network etc.
Want meaning.
Long wave time service system state-of-the-art technology transformation project realizes the daily continuous broadcast in 24 hours of long wave time service system, and
And modulation time-code information and time signal is added in long-wave time service signal under the premise of not influencing existing long wave user normal use
Correction etc., this allows for realizing that autonomous timing and calibrating frequency are possibly realized using long wave time service system.Long wave known today is fixed
When time-code information and time signal correction of the receiver mainly for original long wave time service system, after not having demodulation output upgrading
Several functions does not have the function that time calibration in network is realized using long-wave time service signal as time source yet.Therefore research has long wave
The autonomous timing technology of signal, the long-wave receiver with autonomous timing function and NTP/PTP time calibration in network function have important
Realistic meaning and specific application background.
Summary of the invention
For overcome the deficiencies in the prior art, the present invention provides one kind and has for the BPL long wave time service system after upgrading
Digital signal reception function is realized the device for carrying out autonomous timing to long-wave time service signal using the time-code data of demodulation, and increased
NTP/PTP time calibration in network function is added.The device has provides the user's specification time in real time in the long wave time service system area of coverage
Information and time reference signal receive and show the functions such as long-wave signal transmitting impulse modulation text.Guaranteeing equipment function simultaneously
Can have that precision height, integrated level height, high reliablity, maintenanceability be strong, the spies such as easy to use under conditions of complete, technical indicator
Point.
The technical solution adopted by the present invention to solve the technical problems is: including adc circuit, baseband processing circuitry and man-machine
Interface circuit.
The baseband processing circuitry includes FPGA and DSP；Adc circuit receives the sampling clock from FPGA；Long wave letter
Number export digital medium-frequency signal after ADC is sampled, digital medium-frequency signal by 16 position datawires be sent to FPGA, FPGA and DSP it
Between by 16 position datawires and 12 bit address lines realize interaction, FPGA export the BPL signal envelope of I/Q branch to DSP, DSP will
Frequency control word information is back to FPGA；Meanwhile FPGA sends serial time information to network port circuit, realizes time calibration in network；
FPGA is connected by 14 bit parallel data interfaces with LCD and LED, matrix keyboard by serial data interface respectively with FPGA and
DSP is connected；FPGA exports the machine 1PPS signal and TOC information to man-machine interface, and final the autonomous of realization BPL receiver is determined
When.
The beneficial effects of the present invention are: having used adc circuit, baseband processing circuitry and man-machine interface circuit to constitute receives dress
It sets.In the long wave time service system area of coverage, user's specification temporal information is provided in real time, receives and shows longwave transmissions impulse modulation
Temporal information is exported to user by gigabit ethernet interface and realizes NTP/PTP time service by text.Long-wave signal Full automatic timing
Reception device performance is as follows:
Signal level: 30~120dB μ v/m；
Differential range: 0~80dB；
Envelope to cycle difference (ECD): -2.4~+2.4 μ s；
Signal-to-noise ratio (SNR): >=-14dB (atmospheric noise)；
Its wave interference: 37.5~60 μ s/12~26dB；
Continuous wave CO_2 laser: >=-10dB；
Cross jamming: 0dB.
Under the above conditions, as SNR >=-9.5dB, time difference accuracy is better than 150ns；When SNR >=0dB, the time difference is accurate
Degree is better than 100ns；The opposite broadcast timing pip in time service mode, synchronization accuracy are ± 100ns (- 9.5dB).
Detailed description of the invention
Fig. 1 is structural block diagram of the invention.
Fig. 2 is electronic circuit schematic diagram of the invention.
Fig. 3 is software flow pattern of the invention.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples, and the present invention includes but are not limited to following implementations
Example.
Referring to Fig. 1, the present invention is connected and composed by adc circuit 1, baseband processing circuitry 2 and man-machine interface circuit 3.
The radiofrequency signal by filter and amplification of 1 pair of adc circuit input carries out analog/digital conversion, the number after conversion
Signal is sent to digital signal processing unit.The sample rate of adc circuit 1 is controlled by baseband processing circuitry 2, and ADC requires input terminal
The amplitude of analog signal is in 1Vpp or so, sample frequency 400KHz.
Baseband processing circuitry 2 is mainly made of FPGA and DSP, and FPGA includes search/tracking module and data demodulation module.
Search/tracking module is filtered the digital medium-frequency signal from ADC, amplifies and tracks, and finds out the trace point of long-wave signal
And it is sent to data demodulation module.Data demodulation module be based on DDS structure generate just, cosine signal, then utilize FIR low pass
Filter removes carrier wave to BPL signal, and the BPL signal envelope of I/Q branch is finally sent to DSP.DSP reflects to BPL signal
Then phase demodulation output signal is carried out loop filtering, and frequency control word is sent to data demodulation by parallel data line by phase
Module.Data demodulation module according to frequency control word adjust DDS generate just, cosine signal frequency, realize it is locally generated just
String signal is synchronous with BPL signal carrier.FPGA exports synchronization accuracy≤100ns 1PPS signal and TOC synchronizing information, final real
The autonomous timing of existing BPL receiver.
Man-machine interface circuit 3 is made of matrix keyboard, LCD, LED and network interface, the output of completion timing signal, textual information
And the display function of working state of system.Data demodulation module is by the current search/tracking mode of reception device, temporal information
It is shown by LCD, and is indicated by LED.The setting information that outside is sent is sent to search/tracking by matrix keyboard
Module and DSP, search/tracking module convert setting information to the signal for meeting bus timing, and DSP carries out respective handling.Number
The machine 1PPS and temporal information after synchronizing according to demodulation module are sent to user by network interface, realize NTP/PTP network
Time service.
Electronic circuit schematic diagram of the invention is as shown in Figure 2.Radiofrequency signal from antenna is sent to integrated circuit U1, and U1 is
The two-way voltage feedback type amplifier of model AD8056, open-loop gain 71dB.0.1dB flat gain with 10MHz
The bandwidth of degree and 300MHz.Radiofrequency signal exports after U1 amplifies to U2 input terminal.
The model AD8138 of U2, its effect are that single ended signal is converted to differential signal output, are suitable as
Gain module in intermediate frequency and baseband signal chain.The differential signal of U2 output is sent to the input terminal of U3, differential output signal foot
To drive 16 ADC converter U3 under the conditions of upper frequency, facilitates the Differential Input for balancing U3, reach U3 performance most
It is high.
The model AD9260 of U3 is 16 high speeds an over-sampling ADC, 0~4V of input voltage range, to input signal
Common mode inhibition be 60dB.The range of signal of each Differential Input is the ± 1V centered on 2.0V common mode electrical level.Device configuration
Decimation filter in piece accesses the data in decimation filters at different levels by piece digital multiplexer, while passing through and configuring
It may be programmed reference voltage source in piece and reference voltage buffer amplifier obtain highest precision.In 16 bit digitals after U3 is sampled
Frequency signal is sent to U4.
U4 is the fpga chip of model EP2C70F672, its external connection one 256K*16 word lengths, models
High speed static the random access memory U6, U6 of IS61LV25616 is mainly used as the second level cache of U4.
U5 is the dsp chip of model TMS320C6713, the 16M bit's of an external model S29AL016
FLASH memory U7, U7 are used to realize the bootload of U5, realize the off-line operation of U5.
Integrated circuit U8 is the ethernet mac control of model DM9010 and general processor, integrated circuit U9 are models
For E2023 network interface.Reception device realizes communication and information exchange with user, including solution by the circuit that U8 and U9 is constituted
Adjust information, the output of signal and input of external control information etc..
U4 and U5 constitutes the core processing unit of reception device.The working principle of core processing unit is first to convert ADC
BPL signal afterwards carries out adaptive notch and FIR bandpass filtering treatment, the purpose of adaptive notch and FIR bandpass filtering treatment
It is to further eliminate radiofrequency signal processing unit and filter the interference signal for failing to filter out, is subsequent signal search, period
The links such as identification and Phase Tracking provide the preprocessed signal of preferable signal-to-noise ratio.The signal of processing is divided into two-way after allowing, one
Road is used to carry out the search, tracking and data demodulation of BPL signal, and another way is used to carry out the Periodic identification of BPL pulse signal.Core
The major function of heart processing unit includes:
1) search, capture and tracking of signal: firstly, search program is carried out according to different main, secondary platform phase code
Main, secondary platform identification, generate capture of the GRI synchronization signal realization to BPL signal.After the completion of capture, trace routine is realized to BPL
Signal goes carrier processing, obtains phase modulation information entrained by BPL signal, and the global work clock of generation system；
2) identification of day earthwave and Periodic identification: sky-wave detection program completes each sky-wave detection, guarantees to receive
Machine tracks on the earthwave of BPL signal；Periodic identification program guarantees semaphore lock in third week on zero crossing of BPL signal；
3) modulation textual information resolves: the demodulation of BPL modulated signal is detected using crosscorrelation, and crosscorrelation detection refers to
In data demodulation, the sampled value of every group of data the first two unmodulated pulse is as reference pulse data, then six pulses by after
The data information of acquirement is compared with the data information of benchmark respectively, and according to the size of comparison result, judgement is positively-modulated, bears
It modulates or unmodulated, to demodulate modulation intelligence；
4) the machine time and defeated the generation of timing signal: is calculated according to the digital signal and signal trace information that demodulate
Out；
5) time delay is corrected: for timing receipt device after tracking BPL signal, TOC are synchronized, the timing signal 1PPS of output is opposite
In UTC (NTSC) the 1PPS time there is also certain delay, this delay is known as total constant time lag of BPL receiver.It is total fixed
Shi Yanchi is mainly by propagation delay td, receiver postpone trAnd cycle correction postpones tcThree parts form, in which:
A) propagation delay tdIt is that signal from transmitting antenna propagates to the time required for receiving antenna；
B) receiver postpones trThe main time delay including receiving antenna, feeder line and receiver circuit.
C) cycle correction postpones tcIt is to Phase Tracking in which week relevant correction amount.At the TOC moment, the starting point of pulse
It is consistent with TOC seconds forward positions, because signal amplitude is that zero, BPL timing receiver can not track in pulse starting point
This point, and to track after starting point on the zero crossing in a certain week.At this moment phase gating just has certain prolong relative to pulse starting point
Late, it needs to be modified, i.e. cycle correction.
Since long-wave signal is influenced by earth conductivity on propagation path than more significant, thus need to timing results into
Row additional secondary phase factor ASF amendment, value TjδIt can be by tabling look-up to obtain.It is fixed after carrying out additional secondary phase factor amendment
When receiver total constant time lag be equal to this sum of four, i.e. Δ T=td+tr+tc+Tjδ。
If the secondary platform using the long wave chain of stations is timed, since there are a fixed transmittings to prolong relative to main for secondary platform
Late, so also needing the transmitting delay plus secondary platform in its total constant time lag when reception device receives secondary platform timing signal.
Software flow of the invention is as shown in Figure 3.Software flow is as follows:
1) after being switched on, control program detects storage chip first, and generates display interface.Initialize it is errorless after, system into
Enter automatic search initialization program；
2) automatic search initialization program sets 60000 for group repetition interval, and starts main task of search, makes program
Into search condition；
3) after search is completed to enter trapped state, the data of data demodulation module output become effectively, controlling journey at this time
Phase shift signal is sent into search/trace routine by sequence.After phase shift success, then when being sent into effective UTC to search/trace routine
Between；
4) by obtaining search/trace routine tracking signal, judge whether equipment enters tracking mode and keep；
5) after closing main platform by key, reception device enters manual mode and exits tracking mode, reenters and searches
Strand state；
6) in a manual mode, program reads group repetition interval, phase shift information, the UTC time, TOC moment of manual setting
Etc. information, and execute step 3) and 4).
Claims (1)
1. a kind of long-wave signal Full automatic timing reception device, including adc circuit, baseband processing circuitry and man-machine interface circuit,
It is characterized by: the baseband processing circuitry includes FPGA and DSP；Adc circuit receives the sampling clock from FPGA；Long wave
Signal exports digital medium-frequency signal after ADC is sampled, and digital medium-frequency signal is sent to FPGA, FPGA and DSP by 16 position datawires
Between by 16 position datawires and 12 bit address lines realize interaction, FPGA exports the BPL signal envelope of I/Q branch to DSP, DSP
Frequency control word information is back to FPGA；Meanwhile FPGA sends serial time information to network port circuit, realizes time calibration in network；
FPGA is connected by 14 bit parallel data interfaces with LCD and LED, matrix keyboard by serial data interface respectively with FPGA and
DSP is connected；FPGA exports the machine 1PPS signal and TOC information to man-machine interface, and final the autonomous of realization BPL receiver is determined
When.
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| CN201821949227.0U CN209345145U (en) | 2018-11-26 | 2018-11-26 | Long-wave signal Full automatic timing reception device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111726317A (en) * | 2020-05-25 | 2020-09-29 | 中山大学 | Rowland C signal modulation method, device, equipment and storage medium |
| CN112083442A (en) * | 2020-08-31 | 2020-12-15 | 中国科学院国家授时中心 | BPL (Business Process language) long wave data modulation design method based on additional modulation pulse |
| CN112994821A (en) * | 2021-02-08 | 2021-06-18 | 中国科学院国家授时中心 | Loran-C magnetic antenna received signal synthesis method based on signal characteristic detection |
-
2018
- 2018-11-26 CN CN201821949227.0U patent/CN209345145U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111726317A (en) * | 2020-05-25 | 2020-09-29 | 中山大学 | Rowland C signal modulation method, device, equipment and storage medium |
| CN112083442A (en) * | 2020-08-31 | 2020-12-15 | 中国科学院国家授时中心 | BPL (Business Process language) long wave data modulation design method based on additional modulation pulse |
| CN112994821A (en) * | 2021-02-08 | 2021-06-18 | 中国科学院国家授时中心 | Loran-C magnetic antenna received signal synthesis method based on signal characteristic detection |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211028 Address after: 710000 317, floor 3, Xi'an test mission complex building, national time service center, Hangtian East Road, national civil aerospace industry base, Xi'an, Shaanxi Province Patentee after: Xi'an Zhongke spacetime Asset Management Co.,Ltd. Address before: 710600 No. 3, Tung Road, Lintong District, Shaanxi, Xi'an Patentee before: NATIONAL TIME SERVICE CENTER, CHINESE ACADEMY OF SCIENCE |
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| TR01 | Transfer of patent right |