CN209267558U - A kind of matched filter multiplexer in multiple signals digital receiver - Google Patents
A kind of matched filter multiplexer in multiple signals digital receiver Download PDFInfo
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- CN209267558U CN209267558U CN201920335101.2U CN201920335101U CN209267558U CN 209267558 U CN209267558 U CN 209267558U CN 201920335101 U CN201920335101 U CN 201920335101U CN 209267558 U CN209267558 U CN 209267558U
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Abstract
The utility model discloses the matched filter multiplexers in a kind of multiple signals digital receiver.Including input converting unit, filter unit, quantifying unit and output unit.A beacon signal is generated by high power clock and parallel-serial conversion is carried out to the multiple signals inputted parallel, pipelining design is carried out to matched filtering algorithm again, realize the simultaneously match filtering of serial multiple signals, then filter result is quantified according to design requirement, parallel output is finally turned to serial result according to beacon signal to realize the purpose of matched filter synchronous multiplexing.The utility model combines the time division multiplexing idea of multiple signals and calculating process with matched filter pipelining design, have the characteristics that not needing relative to the existing matched filtering method for being applicable in multiple signals additionally to increase a large amount of logic module resources and synchronous realization multiple signals matched filtering, especially suitable for situation high to logic module resource and signal processing requirement of real-time in multiple signals digital receiver.
Description
Technical field
The utility model relates to the matched filters in the multiple signals digital receiver of one of communications field to be multiplexed dress
The time division multiplexing idea of multiple signals and calculating process can be combined by the realization set with matched filter pipelining design
Realize the purpose that there is multichannel identical sampling rate signal to share a matched filter.
Background technique
With the diversification that multi-beam synchronous satellite system is applied, more and more digital receiver needs are faced while being solved
The problem of adjusting multiple signals, and propose demodulation real-time and save the requirement of fpga logic module resource.It is set pervious
In meter, digital receiver generally only handles signal all the way, and such matched filter can only handle digital baseband signal all the way, in this way
Being applied in multiple signals digital receiver can bring multidiameter delay matched filter to consume a large amount of fpga logic module resources
Problem.Realize that multichannel has identical sampling rate signal using the matched filter multiplexer in multiple signals digital receiver
Matched filtering have important application value.
Utility model content
The purpose of this utility model is that avoiding the shortcoming in above-mentioned background technique and providing a kind of multiple signals number
Matched filter multiplexer in word receiver realizes that there is multichannel identical sampling rate signal to share a matched filter
Purpose.The utility model, which is able to achieve, to be had the characteristics that real-time matching filtering, saves simple more of fpga logic module resource, algorithm
The matched filtering with identical sampling rate signal in the signal digital receiver of road.
The technical issues of the utility model further solves is: the utility model is by the time-division of multiple signals and calculating process
Multiplexing thought combines to realize that there is multichannel identical sampling rate signal to share one with matched filter pipelining design
With filter.
The technical solution adopted in the utility model are as follows:
A kind of matched filter multiplexer in multiple signals digital receiver, including input converting unit 1, filtering are single
Member 2, quantifying unit 3 and output unit 4；The multiple signal input ports and external connection of the input converting unit 1 receive
Multi-path digital baseband signal with identical sample rate, and the two-way that will be obtained after multi-path digital baseband signal progress parallel-serial conversion
Serial i, Q signal and beacon signal are respectively fed to filter unit 2；Filter unit 2 matches two-way serial i, Q signal
Filtering, and beacon signal is adjusted according to processing delay, by filtered two-way serial i, Q signal and beacon signal adjusted
It is sent into quantifying unit 3；Quantifying unit 3 quantifies filtered two-way serial i, Q signal, and is adjusted and marked according to processing delay
Show signal, quantized result and beacon signal adjusted are sent into output unit 4；Output unit 4 is taken out respectively according to beacon signal
As a result, realizing the serioparallel exchange of two-way serial i, Q signal after the matched filtering of the road Qu Ge, the road serioparallel exchange Hou Ge signal is passed through
Multiple signal output ports are output to external data interface.
Wherein, input port 1_1,1_2 of the input converting unit 1 receive the 1st railway digital baseband signal 1_I, 1_Q,
Input port 1_2N-1,1_2N receive N railway digital baseband signal N_I, N_Q, and are equal to N times of input number base using one
The signal that the high power clock of band signal sample rate inputs port 1 carries out parallel-serial conversion, and the road I of the serial signal after conversion is from defeated
Exit port 2_1 is exported to the input port 1_1 of filter unit 2, and the road Q of the serial signal after conversion is exported from output port 2_2
To the input port 1_2 of filter unit 2, and generates a beacon signal synchronous with high power clock and carry out indication output end mouth 2_1
Channel corresponding to each clock cycle signal with output port 2_2, and export from output port 3 by beacon signal to filtering
The input port 2 of unit 2.
Wherein, the quantifying unit 3 inputs input port 1_1 and 1_2 filtered two-way serial i, Q signal carry out
The quantization of fixed-point number, and result is correspondingly outputting to the input port 1_1 and 1_ of output unit 4 by output port 3_1 and 3_2
2, and beacon signal is adjusted according to the processing delay of quantifying unit 3, it is allowed to the every of accurate indication output end mouth 3_1 and 3_2 output
Channel corresponding to a clock cycle signal, and beacon signal adjusted is defeated from the output of output port 4 to output unit 4
Inbound port 2.
Wherein, beacon signal opposite end the input port 1_1 and 1_2 that the output unit 4 is inputted according to input port 2 first are defeated
Two-way serial i, the Q signal entered extracts the filtered signal of each channel matched respectively, then defeated by output port 3_1 and 3_2
The road I, Q of digital signal after 1st tunnel matched filtering out, and so on by output port 3_2N-1 and 3_2N export the road N
The road I, Q of digital signal after matched filtering, while the road N I, Q signal synchronism output are guaranteed by timing_delay estimation.
The utility model has the advantages that compared with the background art
1. the utility model does not need additionally to increase a large amount of fpga logic module resources, only needed using time-multiplexed thought
Want a matched filter that can realize that multichannel has the matched filtering of identical sampling rate signal, so that FPGA be greatly saved
Logic module resource.
It can be with 2. the utility model designs matched filter using pipelining structure, when making multiple signals serial inputs
It is independent to realize filter function, and can be smaller with real-time working, time delay.
3. the utility model structure is simple, implementation complexity is low.
Detailed description of the invention
Fig. 1 is the principles of the present invention block diagram.
Fig. 2 is the timing diagram of the utility model input converting unit.
Fig. 3 is the timing diagram of the utility model output unit.
Specific embodiment
Referring to figs. 1 to Fig. 3, the utility model includes that input converting unit 1, filter unit 2, quantifying unit 3 and output are single
Member 4.Fig. 1 is the principles of the present invention block diagram, and embodiment presses Fig. 1 connection line.Wherein inputting its effect of converting unit 1 is
The multi-path digital baseband signal of input is converted into serial data from parallel data under the control of a high power clock, filtering is single
First 2 its effect are that each road Signal Matching is filtered and exported, its effect of quantifying unit 3 is according to receiver design requirement to filtering
As a result fixed point quantization is carried out, its effect of output unit 4 is that the filtered serial result of each road signal is reverted to parallel signal.
Fig. 2 is the timing diagram for inputting converting unit 1.Digital baseband signal 1_I, digital baseband signal 1_Q are respectively from input
Port 1_1,1_2 of converting unit 1 are sent into, and so on digital baseband signal N_I, digital baseband signal N_Q respectively from input
Port 1_2N-1,1_2N of converting unit 1 are sent into.The road N I, Q signal have identical input sample clock frequency f, in moment t
Signal be expressed as I1 (t), Q1 (t) ..., IN (t), QN (t).The high power clock for being Nf with a frequency is respectively to this
The road N I, Q signal sampling, obtain serial i road signal I1 (t) ..., IN (t), I1 (t+1) ..., the serial road Q signal Q1
(t),……,QN(t),Q1(t+1),…….Port 3 export beacon signal indicate current time t serial i road signal and
Which digital baseband signal the serial road Q signal respectively represent.The beacon signal for inputting the output of 1 port 3 of converting unit is 1 table
Two-way serial i that bright current time t is exported from port 2_1,2_2, the 1st railway digital base band that Q signal is port 1_1,1_2 input
Signal, and so on input 1 port 3 of converting unit output beacon signal be N show that current time t is defeated from port 2_1,2_2
Two-way serial i out, the N railway digital baseband signal that Q signal is port 1_2N-1,1_2N input.
Fig. 3 is the timing diagram of output unit 4.Serial i road signal and the serial road Q signal after completing quantization is respectively from output
Port 1_1,1_2 of unit 4 are inputted, and the beacon signal that the port 2 of output unit 4 inputs indicates the serial i road of current time t
Signal and the serial road Q signal respectively represent the digital signal after which quantization.The mark letter of 4 port 2 of output unit input
Number for 1 demonstrate the need for by port 1_1,1_2 input I, Q signal respectively from port 3_1,3_2 of output unit 4 export, with this
The beacon signal for analogizing the input of 4 port 2 of output unit is that N demonstrates the need for the I for inputting port 1_1,1_2, Q signal respectively from defeated
Port 3_2N-1,3_2N output of unit 4 out obtains initial input sample clock frequency f by N times of sampling recovery.Simultaneously
In order to guarantee N railway digital signal from the port 3_1 of output unit 4 to 3_2N synchronism output, to output unit 4 port 3_1,3_2
The high power clock cycle that N-1 frequency of delay is Nf exports, and so on to output unit 4 port 3_2N-1,3_2N delay 1
The high power clock cycle that frequency is Nf exports.
The process for the Signal Matching filtering that 2 pairs of filter unit input converting units 1 input is as follows:
Current channel information is judged according to the beacon signal of port 2, selects filter coefficient；
The serial two-way I of port 1_1 and 1_2 input, Q signal deposit displacement are posted respectively according to known filter length
Selected filter coefficient is stored in variable reg3 by storage reg1, reg2；
Variable reg1, reg2 are multiplied respectively to obtain correlation reg4, reg5 with reg3；
According to known filter length by correlation reg4, reg5 respectively add up summation obtain filter result, respectively from
Port 3_1 and 3_2 are exported to the port 1_1 and 1_2 of quantifying unit 3；
Beacon signal is adjusted according to the processing delay of filter unit 2, is allowed to accurately indicate the every of port 3_1 and 3_2 output
Channel corresponding to a clock cycle signal, and from the output of port 4 to the input port 2 of quantifying unit 3.
The brief working principle of the utility model is as follows:
Matched filter multiplexer, which can undertake in multiple signals digital receiver while handle multichannel, has identical adopt
The matched filtering function of the digital baseband signal of sample rate.
The utility model is based on existing matched-filter approach, is thought using the time division multiplexing of multiple signals and calculating process
Think, handles the matched filtering of multiple signals simultaneously using high power clock, while pipelining to matched filtering algorithm flow
Design, allows the filter function that each road signal is independently realized when multiple signals serial input, to realize that multiple signals match
The real-time multiplexing of filtering.It is mainly made of input converting unit 1, filter unit 2, quantifying unit 3, output unit 4 inside it.It is defeated
Enter the parallel-serial conversion that converting unit completes each roadbed band signal.Filter unit simultaneously filters each road Signal Matching.Quantifying unit
Filter result is pinpointed and is quantified.Output unit completes the serioparallel exchange of each road signal filter result.
The course of work that matched filter is multiplexed in multiple signals digital receiver is as follows: digital receiver is received comprising complete
Signal in the whole bandwidth of portion's wave beam has the Parallel Digital base band of identical sample rate by the multichannel that AD sampling filter obtains
Signal is sent into input converting unit 1, each roadbed band signal parallel-serial conversion is obtained high-speed serial signals by high power clock, and produce
A raw beacon signal indicates channel corresponding to serial signal in each clock cycle.Filter unit 2 is due to its streamlined knot
The design of structure can carry out matched filtering independent to each channel simultaneously, and by filtered result Serial output.Quantifying unit 3
Fixed point quantization is carried out to the result after 2 matched filtering of filter unit according to the design requirement of receiver, to be suitble to FPGA fixed point fortune
The required precision of calculation.The beacon signal that output unit 4 is exported according to quantifying unit 3, the matching filter that can be exported from quantifying unit 3
The filter result of each channel is accurately found in serial result after wave, to extract the sampling clock for being used together and inputting originally
Recovery is gone back, and parallel multiple signals are retrieved, to complete what matched filter in multiple signals digital receiver was multiplexed
Function.
Claims (4)
1. the matched filter multiplexer in a kind of multiple signals digital receiver, including input converting unit (1), filtering list
First (2), quantifying unit (3) and output unit (4)；It is characterized in that, multiple signals of the input converting unit (1) input
Port and external connection receive the multi-path digital baseband signal with identical sample rate, and multi-path digital baseband signal are carried out
Two-way serial i, Q signal and the beacon signal obtained after parallel-serial conversion is respectively fed to filter unit (2)；Filter unit (2) is right
Two-way serial i, Q signal carry out matched filtering, and adjust beacon signal according to processing delay, by filtered two-way serial i, Q
Signal and beacon signal adjusted are sent into quantifying unit (3)；Quantifying unit (3) is to filtered two-way serial i, Q signal
Quantified, and beacon signal is adjusted according to processing delay, quantized result and beacon signal adjusted are sent into output unit
(4)；Output unit (4) extracts after each road matched filtering according to beacon signal respectively as a result, realizing the string of two-way serial i, Q signal
And convert, serioparallel exchange Hou Ge road signal is output to external data interface by multiple signal output ports.
2. the matched filter multiplexer in a kind of multiple signals digital receiver according to claim 1, feature
Be: input port 1_1,1_2 of input converting unit (1) receive the 1st railway digital baseband signal 1_I, 1_Q, input port 1_
2N-1,1_2N receive N railway digital baseband signal N_I, N_Q, and are sampled using an input digital baseband signal equal to N times
The signal that the high power clock of rate inputs port 1 carries out parallel-serial conversion, and the road I of the serial signal after conversion is from output port 2_1
It exports to the input port 1_1 of filter unit (2), the road Q of the serial signal after conversion exports single to filtering from output port 2_2
The input port 1_2 of first (2), and generate a beacon signal synchronous with high power clock and come indication output end mouth 2_1 and output
Channel corresponding to each clock cycle signal of port 2_2, and export from output port 3 by beacon signal to filter unit
(2) input port 2.
3. the matched filter multiplexer in a kind of multiple signals digital receiver according to claim 1, feature
It is: the amount of filtered two-way serial i, Q signal progress fixed-point number that quantifying unit (3) inputs input port 1_1 and 1_2
Change, and result is correspondingly outputting to the input port 1_1 and 1_2 of output unit (4) by output port 3_1 and 3_2, and according to
The processing delay of quantifying unit (3) adjusts beacon signal, is allowed to each clock of accurate indication output end mouth 3_1 and 3_2 output
Channel corresponding to periodic signal, and beacon signal adjusted is exported from output port 4 to the input terminal of output unit (4)
Mouth 2.
4. the matched filter multiplexer in a kind of multiple signals digital receiver according to claim 1,2 or 3,
It is characterized in that: the two of beacon signal opposite end input port 1_1 and the 1_2 input that output unit (4) is inputted according to input port 2 first
Road serial i, Q signal extract the filtered signal of each channel matched respectively, then export the 1st tunnel by output port 3_1 and 3_2
The road I, Q of digital signal after matched filtering, and so on by output port 3_2N-1 and 3_2N export the matched filtering of the road N
The road I, Q of digital signal afterwards, while the road N I, Q signal synchronism output are guaranteed by timing_delay estimation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112596087A (en) * | 2021-03-04 | 2021-04-02 | 长沙海格北斗信息技术有限公司 | FIR digital filtering method for satellite navigation, navigation chip and receiver |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112596087A (en) * | 2021-03-04 | 2021-04-02 | 长沙海格北斗信息技术有限公司 | FIR digital filtering method for satellite navigation, navigation chip and receiver |
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