CN209120328U - DP signal distribution system based on FPGA - Google Patents
DP signal distribution system based on FPGA Download PDFInfo
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- CN209120328U CN209120328U CN201920085709.4U CN201920085709U CN209120328U CN 209120328 U CN209120328 U CN 209120328U CN 201920085709 U CN201920085709 U CN 201920085709U CN 209120328 U CN209120328 U CN 209120328U
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Abstract
The utility model discloses a kind of DP signal distribution system based on FPGA, including DP signal input module, DP signal conversion module, FPGA module, the power module being connect with FPGA module, the second conversion module being connect with FPGA module, the DP signal output module being connect with the second conversion module, the control module being connect with FPGA module and the terminal being connect with control module, the output end of DP signal input module is connect with the input terminal of DP signal conversion module and control module simultaneously, and the output end of DP signal conversion module and the input terminal of FPGA module connect.Solve it is existing in the prior art, most of DP signal distribution system stable signal transmissions it is low caused by upstream device show unstable technical problem.
Description
Technical field
The utility model belongs to technical field of optical fiber communication more particularly to a kind of DP signal distribution system based on FPGA.
Background technique
Currently, signal transmission application in more and more equipment, under its special use environment, there is signal transmission
The requirement of higher standard includes ultra high-definition, at a distance, multiple terminals is shown etc., especially medical industry.Meanwhile new neck
Domain, new technology expedite the emergence of out more industry requirements, and similar two or four display terminals of this demand of newest CT synchronize aobvious
The case shown emerges one after another, and for the high-performance and high reliability request of industrial circle, but rarely has product can satisfy, and passes
The DP signal distributor of system is difficult to meet the application scenarios of this harshness.
Existing most of DP distributor, such as number of patent application are CN201721089674, apply for entitled DP letter
Number distributor only supports the output of two-way DP, is unable to satisfy the DP output demand of two-way or more, and requires environment in technical grade
Under, existing scheme will appear the case where can not identifying display to cause display not show image generation.
Therefore, the prior art is to be improved.
Utility model content
The main purpose of the utility model is that proposing a kind of DP signal distribution system based on FPGA, it is intended to solve background
The technical issues of mentioned in technology.
The DP signal distribution system based on FPGA of the utility model, including DP signal input module, DP signal modulus of conversion
Block, FPGA module, the power module being connect with FPGA module, the second conversion module being connect with FPGA module and the second conversion
DP signal output module, the control module being connect with FPGA module and the terminal being connect with control module of module connection, DP letter
The output end of number input module is connect with the input terminal of DP signal conversion module and control module simultaneously, DP signal conversion module
Output end and the input terminal of FPGA module connect.
Preferably, DP signal conversion module includes third chip, and the third pin of third chip, four-limbed, the 5th insert
Foot and the 6th pin are connect with DP signal input module, the 51st pin of third chip simultaneously with the 92nd resistance one
End is connected with control module, and the 52nd pin of third chip connects with the 120th resistance one end and control module simultaneously
It connects.
Preferably, control module includes fourth chip and the first socket, and the 18th pin of fourth chip and the 19th are inserted
Foot is connect with first by socket, and the 32nd pin of fourth chip and the 33rd pin connect with DP signal conversion module
It connects.
Preferably, sink equipment includes display screen.
Preferably, power module includes the 9th chip, the 47th resistance, the 80th capacitor, the 81st capacitor and the
Three inductance coils, the 6th pin of the 9th chip first are inserted with feeder ear, the 47th resistance one end, the 9th chip simultaneously
Foot, the 81st capacitor one end are connected with the 80th capacitor one end, the 5th pin of the 9th chip simultaneously with four-limbed, the 8th
Pin, the 9th pin, the 49th resistance one end, the 81st capacitor other end, the 80th capacitor other end are connected with ground, the
The 49 resistance other ends are connect with the third pin of the 9th chip and the 50th resistance one end simultaneously, the 50th resistance other end
Connect with the 48th resistance one end, the 48th resistance other end simultaneously with third inductance coil one end, the 82nd capacitor
One end, the 83rd capacitor one end, the 5th diode one end are connected with FPGA module.
The DP signal distribution system based on FPGA of the utility model, has the advantages that
1, it is arranged based on terminal, control module, control module has been able to recognise whether that DP signal is input to the conversion of DP signal
Module, and control DP signal conversion module and convert DP signal to LVDS signal, terminal is able to monitoring control module, sink equipment
State guarantee stable signal transmission so that all processes are all fully transparent and controllable, avoid the occurrence of sink equipment without
The problem of method is shown.
2, it is arranged based on FPGA module, can at least exports two-way LVDS signal, i.e., at least convert the first LVDS signal
At the 2nd LVDS signal and the 3rd LVDS signal, to be adapted in the application scenarios of the above DP signal output of two-way.
Detailed description of the invention
Fig. 1 is the functional block diagram of DP signal distribution system of the utility model based on FPGA；
Fig. 2 is circuit connection signal of the utility model based on DP signal input module in the DP signal distribution system of FPGA
Figure；
Fig. 3 is the utility model based on input connection protection circuit in the DP signal distribution system of FPGA；
Fig. 4 is circuit connection signal of the utility model based on DP signal conversion module in the DP signal distribution system of FPGA
Figure；
Fig. 5 is circuit connection diagram of the utility model based on power module in the DP signal distribution system of FPGA；
Fig. 6 is circuit connection signal of the utility model based on power filtering module in the DP signal distribution system of FPGA
Figure；
Fig. 7 is circuit connection diagram of the utility model based on FPGA module in the DP signal distribution system of FPGA；
Fig. 8 exports showing for the 2nd LVDS signal based on FPGA module in the DP signal distribution system of FPGA for the utility model
It is intended to；
Fig. 9 exports showing for the 3rd LVDS signal based on FPGA module in the DP signal distribution system of FPGA for the utility model
It is intended to；
Figure 10 is circuit connection signal of the utility model based on the second conversion module in the DP signal distribution system of FPGA
Figure；
Figure 11 is that the utility model is shown based on the circuit connection of DP signal output module in the DP signal distribution system of FPGA
It is intended to；
Figure 12 is circuit connection diagram of the utility model based on control module in the DP signal distribution system of FPGA.
The embodiments will be further described with reference to the accompanying drawings for the realization, functional characteristics and advantage of the utility model aim.
Specific embodiment
It should be appreciated that specific embodiment described herein is only used to explain the utility model, it is not used to limit this
Utility model.
It should be noted that relational language such as " first ", " second " can be used for describing various assemblies, but these arts
Language is not intended to limit the component.These terms are only used to distinguish a component and another component.For example, not departing from the utility model
Range, first assembly can be referred to as the second component, and the second component can also similarly be referred to as first assembly.Term
"and/or" refers to continuous item and describes the combination of any one or more of item.
It is the functional block diagram of DP signal distribution system of the utility model based on FPGA with reference to Fig. 1, Fig. 1.
A kind of DP signal distribution system based on FPGA, which is characterized in that turn including DP signal input module 10, DP signal
Change the mold block 11, FPGA module 12, the power module 13 connecting with FPGA module 12, the second modulus of conversion connecting with FPGA module 12
Block 21, the DP signal output module 22 being connect with the second conversion module 21, the control module 20 being connect with FPGA module 12 and with
The terminal 30 that control module 20 connects, the output end of DP signal input module 10 while the input terminal with DP signal conversion module 11
It is connected with control module 20, the output end of DP signal conversion module 11 is connect with the input terminal of FPGA module 12.Concrete principle is such as
Under: DP signal enters DP signal conversion module via DP signal input module, and control module DP signal and controls DP for identification
DP signal is converted into the first LVDS signal by signal conversion module, and the first LVDS signal exports the 2nd LVDS letter after FPGA module
Number and the 3rd LVDS signal to the second conversion module, the second conversion module the 2nd LVDS signal received and the 3rd LVDS are believed
Number it is converted into the 2nd DP signal and the 3rd DP signal, to be transmitted to sink equipment through DP signal output module；Sink equipment includes
Display screen, display screen include the first display screen 31 and second display screen 32.The DP signal distribution based on FPGA of the utility model
System is had the advantages that 1, is arranged based on control module, and control module has been able to recognise whether that DP signal is input to DP
Signal conversion module, and control DP signal conversion module and convert DP signal to LVDS signal, terminal setting is able to monitoring control
The state of module, sink equipment guarantees stable signal transmission, avoids the occurrence of sink and set so that all processes are all controllable
Standby the problem of can not being shown.2, wherein, for the connection relationship of control module, FPGA module, DP signal conversion module and
Second conversion module is connect with control module, is arranged based on FPGA module, can at least be exported two-way LVDS signal, i.e., by the
One LVDS signal is at least converted to the 2nd LVDS signal and the 3rd LVDS signal, to be adapted to answering for the above DP signal output of two-way
With in scene.3, all link layer data states, Source can be obtained by the communication between terminal and control module in real time
With the state of sink equipment, MCU working condition etc. so that all processes are all fully transparent and can monitor.
It is noted that as shown in fig. 7, FPGA module includes the tenth chip U10, the model of the tenth chip
XC6SLX16CSG324I；Be it is a it is existing with multioutlet chip (its have more than 500 a pins, therefore Fig. 7, Fig. 8,
Chip U10 in Fig. 9 is same), it is arranged based on FPGA module, to realize that the first LVDS signal is converted into two-way is identical
LVDS signal, as shown in figure 8, the 2nd LVDS signal of output；As shown in figure 9, the 3rd LVDS signal of output.And it is based on FPGA module
Using the tenth chip, different from traditional DP distribution system, the utility model, which is based on FPGA module, can be realized at least two-way
LVDS signal output, so that the subsequent at least two-way DP signal that can convert exports, to adapt to the output demand on three tunnels, four tunnels, especially
It is suitable for medical display screens.
As shown in Figure 4, it is preferable that DP signal conversion module includes third chip U3, the third pin of third chip U3
DPRX_LNO_P, four-limbed DPRX_LNO_N, the 5th pin DPRX_LN1_P and the 6th pin DPRX_LN1_N believe with DP
Number input module 10 connects, the 51st pin CFG_SCL of third chip U3 simultaneously with the 92nd one end resistance R92 and control
Molding block 20 connects, the 52nd pin CFG_SDA of third chip U3 simultaneously with the 120th one end resistance R120 and control
Molding block 20 connects；DP signal is converted into the first LVDS semiotic function to realize.
As shown in figure 12, it is preferable that control module 20 includes the of fourth chip U4 and the first socket J2, fourth chip U4
18 pins and the 19th pin connect with the first socket, the 32nd pin I2CSCL_2/P2.5 and third of fourth chip
13 pin I2CSCL_2/P2.4 are connect with DP signal conversion module 11.To realize following principle: control module can identify
Whether there is DP signal to be input to DP signal conversion module, i.e., by the detection to signal transmission link, controls DP signal modulus of conversion
Block works and obtains the status information of DP signal conversion module and DP signal in real time.
As shown in figure 5, Fig. 5 is circuit connection of the utility model based on power module in the DP signal distribution system of FPGA
Schematic diagram, it is preferable that the input termination 5V power supply of power module, power module are used to 5V being transformed into 3.3V to export to FPGA
Module；It further include the power filtering module being connect with power module, specific connection schematic diagram is as shown in fig. 6, to play filtering
Function improves voltage and converts stability.Specifically: power module includes the 9th chip U9, the 47th resistance R47, the 80th
The 6th pin VIN_SW of capacitor C80, the 81st capacitor C81 and third inductance coil L3, the 9th chip U9 simultaneously with power supply
End+5V_DVDD, the 47th resistance one end, the first pin VIN_A of the 9th chip, the 81st capacitor one end and the 80th
The connection of capacitor one end, the 5th pin SYNC of the 9th chip simultaneously with four-limbed AGND, the 8th pin PGND, the 9th pin
PAD, the 49th one end resistance R49, the 81st capacitor other end, the 80th capacitor other end are connected with ground, and the 49th
The resistance other end is connect with the third pin FB of the 9th chip and the 50th one end resistance R50 simultaneously, the 50th resistance other end
Connect with the 48th resistance one end, the 48th resistance other end simultaneously with third inductance coil one end, the 82nd capacitor
The one end C82, the 83rd one end capacitor C83, the 5th one end diode D5 and FPGA module 12 connect；5V voltage is turned with realizing
Output is to FPGA module after changing 3.3V into, for its work.
Wherein, the second conversion module includes the 11st chip U11, and specific connection is as shown in Figure 10, to realize FPGA
Module 12 issues the 2nd LVDS signal to come and the 3rd LVDS signal is converted into the 2nd DP signal and the 3rd DP signal.DP signal
The specific connection schematic diagram of output module is as shown in figure 11, and DP signal output module receives the 2nd DP signal there are two being respectively
With the 3rd DP signal, accordingly the 2nd DP signal, the 3rd DP signal are exported to sink equipment by two Second terminal CN4.
The DP signal distribution system based on FPGA of the utility model, sets out in those skilled in the art's angle, is seeing
Figure of description disclosed in it should belong to the protection scope of the present embodiment, and whole electronic component models can be in the accompanying drawings
It views, for the pin on chip, also referred to as pin.
The DP signal distribution system based on FPGA of the utility model, rate-determining steps include that the monitoring of 1. control modules is
It is no to there is the input of DP signal to continue waiting for the input of signal if inputted without signal；If there is input, carry out in next step；2.
Control module detects rear end HPD signal, determines whether there is the access of sink equipment, if so, then reading display correlation
Information and DPCD relevant information, and the correctness of data is verified.Then according to the parameter initialization input read
Module and output module and conversion module access rear module into equipment in next step, is otherwise continued waiting for.3. initializing defeated
After entering module, input module handles DP signal, and DP signal is converted to LVDS signal, is then transferred to LVDS signal
LVDS signal is changed into the signal that multichannel replicates completely all the way and is output to output module by conversion module, conversion module, is entered
In next step；4. after output module detects the LVDS signal from conversion module output, carrying out sampling processing to LVDS signal and sentencing
It is fixed, configuration change is carried out to corresponding module if signal is problematic, re-starts signal conversion, otherwise exports signal to even
The sink equipment connect；5. being in real time monitored the signal of input after signal output, in case of changing, need to re-start
Conversion completes corresponding configuration and completes the re-training to rear end connection equipment；6. persistently whether monitoring rear end equipment
It changes, by the monitoring to rear end equipment HPD signal, judgement is Long HPD or Short HPD, then obtains Link
State, and be arranged accordingly.
The above is only the preferred embodiments of the utility model, and therefore it does not limit the scope of the patent of the utility model, all
Equivalent structure or equivalent flow shift made based on the specification and figures of the utility model, is applied directly or indirectly in
Other related technical areas are also included in the patent protection scope of the utility model.
Claims (6)
1. a kind of DP signal distribution system based on FPGA, which is characterized in that including DP signal input module, DP signal modulus of conversion
Block, FPGA module, the power module being connect with FPGA module, the second conversion module being connect with FPGA module and the second conversion
DP signal output module, the control module being connect with FPGA module and the terminal being connect with control module of module connection, DP letter
The output end of number input module is connect with the input terminal of DP signal conversion module and control module simultaneously, DP signal conversion module
Output end and the input terminal of FPGA module connect.
2. the DP signal distribution system based on FPGA as described in claim 1, which is characterized in that the input of power module terminates 5V
Power supply, power module are used to 5V being transformed into 3.3V to export to FPGA module.
3. the DP signal distribution system based on FPGA as described in claim 1, which is characterized in that DP signal conversion module includes the
Three chips, third pin, four-limbed, the 5th pin and the 6th pin of third chip are connect with DP signal input module,
51st pin of third chip is connect with the 92nd resistance one end and control module simultaneously, and the 52nd of third chip the
Pin is connect with the 120th resistance one end and control module simultaneously.
4. the DP signal distribution system based on FPGA as described in claim 1, which is characterized in that control module includes fourth chip
With the first socket, the 18th pin of fourth chip and the 19th pin are connect with the first socket, and the 30th of fourth chip the
Two pins and the 33rd pin are connect with DP signal conversion module.
5. the DP signal distribution system based on FPGA as described in claim 1, which is characterized in that sink equipment includes display screen.
6. the DP signal distribution system based on FPGA as described in claim 1, which is characterized in that power module includes the 9th core
Piece, the 47th resistance, the 80th capacitor, the 81st capacitor and third inductance coil, the 6th pin of the 9th chip is simultaneously
With feeder ear, the 47th resistance one end, the first pin of the 9th chip, the 81st capacitor one end and the 80th capacitor one end
Connection, the 5th pin of the 9th chip simultaneously with four-limbed, the 8th pin, the 9th pin, the 49th resistance one end, the 8th
The 11 capacitor other ends, the 80th capacitor other end are connected with ground, the 49th resistance other end simultaneously with the 9th chip the
Three pins and the connection of the 50th resistance one end, the 50th resistance other end are connect with the 48th resistance one end, the 48th electricity
Hinder the other end simultaneously with third inductance coil one end, the 82nd capacitor one end, the 83rd capacitor one end, the 5th diode one
End is connected with FPGA module.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920085709.4U CN209120328U (en) | 2019-01-18 | 2019-01-18 | DP signal distribution system based on FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920085709.4U CN209120328U (en) | 2019-01-18 | 2019-01-18 | DP signal distribution system based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109547712A (en) * | 2019-01-18 | 2019-03-29 | 深圳市巨潮科技股份有限公司 | DP signal distribution system based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109547712A (en) * | 2019-01-18 | 2019-03-29 | 深圳市巨潮科技股份有限公司 | DP signal distribution system based on FPGA |
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Address after: 518000 517, building 7, Hengda fashion Huigu building (East District), Fulong Road, Tongsheng community, Dalang street, Longhua District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN BIGTIDE TECHNOLOGY Co.,Ltd. Address before: Building 8, longfu Industrial Zone, 397 Huarong Road, Longhua New District, Shenzhen, Guangdong 518000 Patentee before: SHENZHEN BIGTIDE TECHNOLOGY Co.,Ltd. |