CN207218903U - USB interface circuit and electronic equipment - Google Patents
USB interface circuit and electronic equipment Download PDFInfo
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- CN207218903U CN207218903U CN201721308630.0U CN201721308630U CN207218903U CN 207218903 U CN207218903 U CN 207218903U CN 201721308630 U CN201721308630 U CN 201721308630U CN 207218903 U CN207218903 U CN 207218903U
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- pressure limiting
- limiting circuit
- usb interface
- diode
- circuit
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Abstract
The utility model discloses a kind of USB interface circuit and electronic equipment.The USB interface circuit includes row synchronous pin, field synchronization pin, the first pressure limiting circuit and the second pressure limiting circuit；The row synchronization pin connects the first end of first pressure limiting circuit, the second end ground connection of first pressure limiting circuit；The field synchronization pin connects the first end of second pressure limiting circuit, the second end ground connection of second pressure limiting circuit.The electronic equipment includes above-mentioned USB interface circuit.The utility model can realize the effect for preventing non-standard wire rod from causing I2C data read errors.
Description
Technical field
The utility model embodiment is related to signaling interface technical field, more particularly to a kind of USB interface circuit and electronics are set
It is standby.
Background technology
VGA (Video Graphics Array) Video Graphics Array is that IBM used simulation in one proposed in 1987
The Computer display standard of signal.USB interface is the special purpose interface that computer uses VGA standard output data.It shares 15
It stitch, red, green, blue analog signal and field sync signal, line synchronising signal can be transmitted, be most widely used on current video card
Interface type.But the VGA line material of current part producer is not according to standard production so that row field sync signal line and I2C lines
May adjacent cabling.In this case, row field sync signal can be coupled on I2C signals.If wire rod is long, signal can be caused
Deformity so that the amplitude of line synchronising signal or field sync signal is excessive, and I2C can also be exceeded by being coupled to the signal amplitude on I2C lines
Data are identified as low level maximum, when the signal amplitude that row field sync signal is coupled on I2C lines is excessive, can cause
The low level signal of I2C transmission is read as high level signal so that data read errors.
Utility model content
The utility model embodiment provides a kind of USB interface circuit and electronic equipment, and data read errors are prevented to realize.
In a first aspect, the utility model embodiment provides a kind of USB interface circuit, including the synchronous pin of row, field synchronization are drawn
Pin, the first pressure limiting circuit and the second pressure limiting circuit；
The row synchronization pin connects the first end of first pressure limiting circuit, the second termination of first pressure limiting circuit
Ground；
The field synchronization pin connects the first end of second pressure limiting circuit, the second termination of second pressure limiting circuit
Ground.
Second aspect, the utility model embodiment also provide a kind of electronic equipment, and the electronic equipment includes the utility model
The USB interface circuit that any embodiment provides.
The utility model embodiment by be expert at synchronous pin and field synchronization pin at, increase pressure limiting circuit, it is same to limit row
Signal and the voltage amplitude of field sync signal are walked, so as to limit the signal amplitude for being coupled to I2C lines, it is same to solve prior art row field
The signal amplitude that step signal is coupled on I2C lines crosses the low level signal that conference causes I2C to transmit and is read as high level signal
The problem of, realization prevents non-standard wire rod from causing the effect of data read errors.
Brief description of the drawings
Fig. 1 is the structured flowchart for the USB interface circuit that the utility model embodiment one provides；
Fig. 2 is the structural representation for the USB interface circuit that the utility model embodiment one provides；
Fig. 3 is the structural representation for the USB interface circuit that the utility model embodiment two provides；
Fig. 4 is the structural representation for the electronic equipment that the utility model embodiment three provides.
Embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than to restriction of the present utility model.Further need exist for
It is bright, for the ease of description, the part related to the utility model rather than entire infrastructure are illustrate only in accompanying drawing.
Embodiment one
Referring to Fig. 1, Fig. 1 is the structured flowchart for the USB interface circuit that the utility model embodiment one provides.The USB interface
Circuit includes row synchronous pin VS, field synchronization pin HS, the first pressure limiting circuit 100 and the second pressure limiting circuit 200.The synchronous pin of row
The first end of the first pressure limiting circuit of VS connections 100, the second end ground connection of the first pressure limiting circuit 100；Field synchronization pin HS connections
The first end of two pressure limiting circuits 200, the second end ground connection of the second pressure limiting circuit 200.
Both end voltage can be limited in scope of design by pressure limiting circuit, and therefore, the present embodiment can limit line synchronising signal
With the voltage magnitude of field sync signal so that even if line synchronising signal line or field synchronization in the VGA data wires that USB interface is connected
Signal wire is adjacent with I2C lines, and it is also limited to be coupled to the voltage signal amplitude of I2C lines, will not cause I2C data read errors.
Referring to Fig. 2, Fig. 2 is the structural representation of the present embodiment USB interface circuit, as shown in Fig. 2 the utility model uses
The clamp circuit that double diode is formed is as pressure limiting circuit.Specifically, the first pressure limiting circuit 100 includes the first diode D1, the
Two diode D2 and high level signal connection end VCC；
First diode D1 positive pole connects the second end of the first pressure limiting circuit 100, the first diode D1 negative pole connection
The first end of first pressure limiting circuit 100, the first diode D1 negative pole connect the second diode D2 positive pole, the second diode D2
Negative pole connection high level signal connection end VCC.The operation principle of first pressure limiting circuit 100 is then when the voltage of the synchronous pin of row
Turned on more than high level signal connection end VCC voltages with the second diode D2 during N sum, when row synchronously draws
When the voltage of pin is less than the opposite number of N, then the first diode D1 is turned on, so as to by the electricity of the synchronous pin of row
Pressing tongs position is the opposite number more than N and is less than VCC and conduction voltage drop sum.
Correspondingly, the second pressure limiting circuit 200 includes the 3rd diode D3 and the 4th diode D4.3rd diode D3 is just
Pole connects the second end of the second pressure limiting circuit 200, and the 3rd diode D3 negative pole connects the first end of the second pressure limiting circuit 200,
3rd diode D3 negative pole connects the 4th diode D4 positive pole, and the 4th diode D4 negative pole connects the high level signal
Connection end VCC.The operation principle of second pressure limiting circuit is identical with the first pressure limiting circuit, will not be repeated here.
Further, the USB interface circuit also includes first for connecting interface chip line synchronising signal sending and receiving end
Interface chip connection end VS_IC, first resistor R1, second resistance R2,3rd resistor R3 and the first electric capacity C1；The synchronous pin VS of row
Connect first resistor R1 first end, first resistor R1 the second end connection first interface chip connection end VS_IC；Second resistance
R2 first end connection first resistor R1 first end, second resistance R2 the second end ground connection；3rd resistor R3 first end connects
Connect first resistor R1 the second end, 3rd resistor R3 the second end ground connection；First electric capacity C1 first end connection first interface core
Piece connection end VS_IC, the first electric capacity C1 the second end ground connection.Wherein, the first electric capacity C1 is used to filter, to reduce other electronics member
Part is to the electromagnetic interference of USB interface circuit, the resistance of first resistor R1, second resistance R2 and the synchronous pin of 3rd resistor R3 composition rows
Anti- matching network, improve transimission power.
USB interface circuit also includes the second interface chip connection end for connecting interface chip field sync signal sending and receiving end
HS_IC, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6 and the second electric capacity C2；The resistance R4 of field synchronization pin HS connections the 4th
First end, the 4th resistance R4 the second end connection second interface chip connection end HS_IC；5th resistance R5 first end connection
4th resistance R4 first end, the 5th resistance R5 the second end ground connection；6th resistance R6 first end connects the 4th resistance R4's
Second end, the 6th resistance R3 the second end ground connection；Second electric capacity C2 first end connection second interface chip connection end HS_IC,
Second electric capacity C2 the second end ground connection.Wherein, the second electric capacity C2 is used to filter, to reduce other electronic components to USB interface electricity
The impedance matching network of the electromagnetic interference on road, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 composition field synchronization pins, is carried
Large transmission power.
It should be noted that the first pressure limiting circuit 100 and the second pressure limiting circuit 200 are using same topology in the present embodiment
Two-diode clamp circuit, when it is implemented, on the premise of signal-obtaining and transmission is not influenceed, different limits can also be used
Volt circuit, or other pressure limiting circuits are used, row field signal amplitude is limited in for example with voltage reference IC (such as TL431)
Voltage reference ID reference voltage.
In summary, the technical scheme of the present embodiment, at be expert at synchronous pin and field synchronization pin, increase pressure limiting electricity
Road, the voltage amplitude of line synchronising signal and field sync signal is limited, so as to limit the signal amplitude for being coupled to I2C lines, solved existing
The signal amplitude for having technology row field sync signal to be coupled on I2C lines is crossed the low level signal that conference causes I2C to transmit and is read
For high level signal the problem of, realization prevent non-standard wire rod from causing the effect of data read errors.
Embodiment two
Referring to Fig. 3, Fig. 3 is the structural representation for the USB interface circuit that the utility model embodiment two provides.The VGA connects
Mouth circuit includes row synchronous pin VS, field synchronization pin HS, the first pressure limiting circuit and the second pressure limiting circuit.The synchronous pin VS of row connects
Connect the first end of the first pressure limiting circuit 100, the second end ground connection of the first pressure limiting circuit 100；Field synchronization pin HS connections second limit
The first end of volt circuit 200, the second end ground connection of the second pressure limiting circuit 200.
As shown in figure 3, first pressure limiting circuit 100 of the present embodiment includes the first voltage-regulator diode Dz1, the first pressure limiting circuit
100 first end is the first voltage-regulator diode Dz1 negative pole, and the second end of the first pressure limiting circuit 100 is the first voltage-regulator diode
Dz1 positive pole.
Correspondingly, the second pressure limiting circuit 200 includes the second voltage-regulator diode Dz2；The first end of second pressure limiting circuit 200 is
Second voltage-regulator diode Dz2 negative pole, the second end of the second pressure limiting circuit 200 are the second voltage-regulator diode Dz2 positive pole.
It is that it need not connect power supply as the beneficial effect of pressure limiting circuit using voltage-regulator diode.Embodiment one provides
Two-diode clamp circuit, it is necessary to connect high level signal, obtain high level signal often through connection device power supply (DPS), and
When equipment is not upper electric, when insertion VGA data wires are to USB interface, the row field signal that VGA data wires are carried can pass through height
Level signal connection end is poured in down a chimney onto device power supply (DPS), equipment may be caused to cannot be started up.Therefore the present embodiment uses the pole of voltage stabilizing two
Pipe, without connecting device power supply (DPS), avoids row field signal from pouring in down a chimney to device power supply (DPS) as pressure limiting circuit.
In addition, facilitating adjusting parameter using voltage-regulator diode, the power supply amplitude limited as needed is directly selected and reversely hit
Wear the suitable voltage-regulator diode of voltage.In practical application, finding more than 7V row field signal amplitude can cause to be coupled to
Voltage magnitude on I2C lines is more than identification low level maximum, and the present embodiment is preferably using the voltage stabilizing that breakdown reverse voltage is 5V
Diode, it is ensured that the voltage magnitude that row field signal is coupled on I2C lines, which is less than, identifies low level maximum.
Specifically, the USB interface circuit of the present embodiment also includes and the identical impedance matching network of embodiment one and filtering
Electric capacity.
In summary, the technical scheme of the present embodiment, at be expert at synchronous pin and field synchronization pin, voltage stabilizing two is increased
Pole pipe, the voltage amplitude of line synchronising signal and field sync signal is limited, so as to limit the signal amplitude for being coupled to I2C lines, solved
The signal amplitude that prior art row field sync signal is coupled on I2C lines is crossed the low level signal that conference causes I2C to transmit and read
The problem of being taken as high level signal, realization prevent non-standard wire rod from causing the effect of data read errors.
Embodiment three
Referring to Fig. 4, Fig. 4 is the structural representation for the electronic equipment that the utility model embodiment three provides.The electronic equipment
The USB interface circuit 300 provided including the utility model any embodiment.Specifically, the electronic equipment also includes interface chip,
Row field signal for exporting or receiving to electronic equipment carries out the processing such as digital-to-analogue conversion.The first interface core of USB interface circuit
Piece connection end VS_IC and second interface chip connection end HS_IC connects two I/O mouths of the interface chip respectively.
Specifically, the electronic equipment can be commercial display flat board, intelligent television, Systems for optical inspection or industrial robot
Deng.The synchronous pin of row in electronic equipment is used to connect the line synchronising signal line in VGA data wires, and field synchronization pin is used to connect
Field sync signal line in VGA data wires.The ancillary equipment of these electronic equipments docking is more, due to the wire rod of various ancillary equipment
Difference, there is a situation where to use non-standard wire rod.Line synchronising signal line or field in the VGA data wires of non-standard wire rod
Synchronous signal line may be adjacent with I2C lines.The electronic equipment that the present embodiment provides can be suitably used for non-standard wire rod, therefore, this reality
The commercial of example offer is provided and shows that flat board compatibility is high.
It should be noted that in the case of not conflicting, those skilled in the art will can retouch in this specification
The different embodiments or example and the feature of different embodiments or example stated are combined and combined.
In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint relative importance
Or the implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can be expressed or
Implicitly include at least one this feature.
Pay attention to, above are only preferred embodiment of the present utility model and institute's application technology principle.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, can carried out for a person skilled in the art various bright
Aobvious change, readjust and substitute without departing from the scope of protection of the utility model.Therefore, although passing through above example
The utility model is described in further detail, but the utility model is not limited only to above example, is not departing from
In the case that the utility model is conceived, other more equivalent embodiments can also be included, and the scope of the utility model is by appended
Right determine.
Claims (8)
1. a kind of USB interface circuit, it is characterised in that including the synchronous pin of row, field synchronization pin, the first pressure limiting circuit and second
Pressure limiting circuit；
The row synchronization pin connects the first end of first pressure limiting circuit, the second end ground connection of first pressure limiting circuit；
The field synchronization pin connects the first end of second pressure limiting circuit, the second end ground connection of second pressure limiting circuit.
2. USB interface circuit as claimed in claim 1, it is characterised in that first pressure limiting circuit includes the first voltage stabilizing two
Pole pipe；The first end of first pressure limiting circuit is the negative pole of first voltage-regulator diode, the of first pressure limiting circuit
Two ends are the positive pole of first voltage-regulator diode.
3. USB interface circuit as claimed in claim 2, it is characterised in that the reverse breakdown electricity of first voltage-regulator diode
Press as 5V.
4. USB interface circuit as claimed in claim 1, it is characterised in that first pressure limiting circuit include the first diode,
Second diode and high level signal connection end；
The positive pole of first diode connects the second end of first pressure limiting circuit, the negative pole connection of first diode
The first end of first pressure limiting circuit, the negative pole of first diode connect the positive pole of second diode, and described the
The negative pole of two diodes connects the high level signal connection end.
5. the USB interface circuit as described in any one of claims 1 to 3, it is characterised in that the row synchronization pin is used to connect
Line synchronising signal line in VGA data wires, the field synchronization pin are used to connect the field sync signal line in VGA data wires, institute
It is adjacent with the I2C lines in the VGA data wires to state line synchronising signal line or field sync signal line.
6. USB interface circuit as claimed in claim 2 or claim 3, it is characterised in that second pressure limiting circuit includes the second voltage stabilizing
Diode；The first end of second pressure limiting circuit is the negative pole of second voltage-regulator diode, second pressure limiting circuit
Second end is the positive pole of second voltage-regulator diode.
7. the USB interface circuit as described in any one of claims 1 to 3, it is characterised in that the USB interface circuit also includes
First interface chip connection end, first resistor, second resistance, 3rd resistor and the first electric capacity；
The row synchronization pin connects the first end of the first resistor, and the second end connection described first of the first resistor connects
Mouth chip connection end；The first end of the first end connection first resistor of the second resistance, the second of the second resistance
End ground connection；The first end of the 3rd resistor connects the second end of the first resistor, the second end ground connection of the 3rd resistor；
The first end of first electric capacity connects the first interface chip connection end, the second end ground connection of first electric capacity.
8. a kind of electronic equipment, it is characterised in that the VGA that the electronic equipment is included as described in any one of claim 1 to 7 connects
Mouth circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721308630.0U CN207218903U (en) | 2017-09-30 | 2017-09-30 | USB interface circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721308630.0U CN207218903U (en) | 2017-09-30 | 2017-09-30 | USB interface circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207218903U true CN207218903U (en) | 2018-04-10 |
Family
ID=61820960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721308630.0U Active CN207218903U (en) | 2017-09-30 | 2017-09-30 | USB interface circuit and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207218903U (en) |
-
2017
- 2017-09-30 CN CN201721308630.0U patent/CN207218903U/en active Active
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