CN209119168U

CN209119168U - Embedded capacitor structure, storage device

Info

Publication number: CN209119168U
Application number: CN201920008088.XU
Authority: CN
Inventors: 赵忠强
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-01-03
Filing date: 2019-01-03
Publication date: 2019-07-16
Anticipated expiration: 2029-01-03

Abstract

Present disclose provides a kind of embedded capacitor structures, storage device, belong to technical field of semiconductors.The embedded capacitor structure includes the first supporting course, first electrode, dielectric layer and second electrode, wherein the first supporting course is set to the side of a substrate, and has the first support holes；First electrode is in the form of a column and extending direction is vertical with plane where the substrate；The first electrode has the first end set on the substrate surface and the second end far from the substrate, and the second end is ordinatedly arranged in first support holes；The first electrode is equipped with capacitor slot, and the notch of the capacitor slot is set to the second end；The side of the second end is equipped with opening, and described be open is located at first supporting course between the surface and the substrate of the substrate close to one end of the substrate；Dielectric layer covers the first electrode；Second electrode covers the dielectric layer.The embedded capacitor structure can improve the preparation efficiency and yield of embedded capacitor structure.

Description

Embedded capacitor structure, storage device

Technical field

This disclosure relates to technical field of semiconductors more particularly to a kind of embedded capacitor structure, storage device.

Background technique

Capacitor is a kind of important electric elements, is widely used in the technical fields such as semiconductor.For example, in DRAM In (dynamic random access memory), capacitor can be used as memory element to store information.With the development of semiconductor technology, electricity The size of appearance is smaller and smaller.

When preparing the capacitor of microsize, such as when preparing nanoscale embedded capacitor structure, usually electricity is being obtained Grid-pattern structures are formed by infiltration type exposure machine after holding zanjon, are then filled using capacitance deep and grid-pattern structures Dielectric layer.However, the use cost of infiltration type exposure machine is high, the preparation cost for resulting in capacitor is higher.Moreover, in formation When grid-pattern structures, it is difficult to be effectively aligned with capacitance deep, cause dielectric layer filling difficult, reduce the preparation efficiency of capacitor And yield.

Above- mentioned information disclosed in the background technology part are only used for reinforcing the understanding to the background of the disclosure, therefore it can To include the information not constituted to the prior art known to persons of ordinary skill in the art.

Utility model content

The disclosure is designed to provide a kind of embedded capacitor structure, storage device, reduces embedded capacitor structure Preparation cost improves the preparation efficiency and yield of embedded capacitor structure.

According to the first aspect of the disclosure, a kind of embedded capacitor structure is provided, comprising:

First supporting course set on the side of a substrate, and has the first support holes；

First electrode, is in the form of a column and extending direction is vertical with plane where the substrate；The first electrode, which has, to be set to The second end of the first end of the substrate surface and the separate substrate, and the second end is ordinatedly arranged in described first Bearing bore；The first electrode is equipped with capacitor slot, and the notch of the capacitor slot is set to the second end；The side of the second end Equipped with opening, and described be open is located at surface and institute of first supporting course close to the substrate close to one end of the substrate It states between substrate；

Dielectric layer covers the first electrode；

Second electrode covers the dielectric layer.

In a kind of exemplary embodiment of the disclosure, the material of first supporting course is silicon nitride.

In a kind of exemplary embodiment of the disclosure, first supporting course with a thickness of 60~100 nanometers.

In a kind of exemplary embodiment of the disclosure, the length of the first electrode is 800~1500 nanometers.

In a kind of exemplary embodiment of the disclosure, maximum of the first electrode perpendicular to the section of its extending direction Having a size of 15~50 nanometers.

In a kind of exemplary embodiment of the disclosure, described one end being open close to the substrate and first bearing Layer is 50~100 nanometers close to the distance between surface of the substrate.

In a kind of exemplary embodiment of the disclosure, the embedded capacitor structure further include:

Second supporting course is set between the substrate and first supporting course, and is had and first support holes pair The second support holes answered, the first end are ordinatedly arranged in second support holes.

In a kind of exemplary embodiment of the disclosure, the dielectric layer covers the inner surface of the first electrode and described At least partly region of the outer surface of first electrode.

In a kind of exemplary embodiment of the disclosure, the material of the dielectric layer be aluminium oxide, silica, zirconium oxide and One or more of silicon nitride

According to the second aspect of the disclosure, a kind of storage device is provided, including above-mentioned embedded capacitor structure.

Embedded capacitor structure, the storage device of disclosure offer can formed when preparing embedded capacitor structure After first electrode, the partial region of one end (i.e. the opening portion of first electrode) with preset direction to first electrode far from substrate Ion implanting is carried out, since the extending direction in ion implanting direction and capacitor hole tilts, the opening portion of first electrode Side can not be by injection ion by injection ion, the other side.First electrode is by the region of injection ion, due to being doped with The ion of injection, physicochemical property will change and generate difference with other regions of first electrode, can be gone using the difference Except the first electrode is by the region of injection ion, and then opening is formed on the first electrode.The preparation method is without infiltration Formula exposure machine forms grid-pattern structures, imitates when also avoiding being formed grid-pattern structures with capacitor hole misregistration bring Rate and yield reduce, and can efficiently and accurately form opening on the first electrode, reduce the preparation cost of capacitor, improve The preparation efficiency and yield of capacitor.

Detailed description of the invention

Its example embodiment is described in detail by referring to accompanying drawing, the above and other feature and advantage of the disclosure will become It is more obvious.

Fig. 1 is the preparation method flow diagram of embedded capacitor structure in one embodiment of the disclosure.

Fig. 2 is the schematic diagram that the first supporting layer is formed in one embodiment of the disclosure.

Fig. 3 is the result schematic diagram that capacitor hole is formed in one embodiment of the disclosure.

Fig. 4 is the result schematic diagram that first electrode is formed in one embodiment of the disclosure.

Fig. 5 is the schematic diagram of one embodiment intermediate ion of disclosure injection.

Fig. 6 is the result schematic diagram of one embodiment intermediate ion of disclosure injection.

Fig. 7 is the result schematic diagram that opening is formed in one embodiment of the disclosure.

Fig. 8 is wet-etch rate figure of the silicon nitride under different doping.

Fig. 9 is wet-etch rate figure of the silica under different doping.

Figure 10 is the result schematic diagram that protective layer and photoresist layer are formed in one embodiment of the disclosure.

Figure 11 is the result schematic diagram that the middle layer of peripheral region is exposed in one embodiment of the disclosure.

Figure 12 is the result schematic diagram that protective layer and photoresist layer are removed in one embodiment of the disclosure.

Figure 13 is the result schematic diagram that middle layer is removed in one embodiment of the disclosure.

Figure 14 is the result schematic diagram that dielectric layer is formed in one embodiment of the disclosure.

Figure 15 is the result schematic diagram that second electrode is formed in one embodiment of the disclosure.

Figure 16 is the result schematic diagram that planarization layer is formed in one embodiment of the disclosure.

Figure 17 is the preparation method flow diagram of storage device in one embodiment of the disclosure.

Figure 18 is the schematic top plan view of the first electrode of storage device in one embodiment of the disclosure.

Main element description of symbols includes: in figure

101, substrate；102, planarization layer；103, the first supporting course；104, first electrode；1041, first end；1042, Two ends；105, dielectric layer；106, second electrode；107, the second supporting course；201, middle layer；202, capacitor hole；2021, first Bearing bore；2022, the second support holes；203, first electrode is by the region of injection ion；204, it is open；205, capacitor slot；301, it deposits Storage area domain；302, peripheral region；303, protective layer；304, photoresist layer.

Specific embodiment

Example embodiment is described more fully with reference to the drawings.However, example embodiment can be real in a variety of forms It applies, and is not understood as limited to example set forth herein；On the contrary, these embodiments are provided so that the disclosure will more comprehensively and Completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, structure or characteristic It can be incorporated in any suitable manner in one or more embodiments.In the following description, many details are provided Embodiment of the disclosure is fully understood to provide.

In the figure for clarity, may be exaggerated the thickness of region and layer.The portion size of part dependency structure may be done Enhanced processing, specific size be subject to skilled artisans appreciate that.Identical appended drawing reference indicates phase in figure Same or similar structure, thus the detailed description that them will be omitted.

Described feature, structure or characteristic can be incorporated in any suitable manner in one or more embodiments. In the following description, many details are provided to provide and fully understand to embodiment of the disclosure.However, this field Technical staff will realize can with technical solution of the disclosure without one or more in the specific detail, or Person can be using other methods, constituent element, material etc..In other cases, be not shown in detail or describe known features, material or The major technique intention that person operates to avoid the fuzzy disclosure.

Term "one", " one ", " described " to indicate there are one or more elements/component part/etc.；Term " packet Include " and " having " to indicate the open meaning being included and refer to that the element/component part/in addition to listing waits it Outside also may be present other element/component part/etc..Term " first " and " second " etc. are only used as label, are not to it The quantity of object limits.

A kind of preparation method of embedded capacitor structure is provided in disclosure embodiment, as shown in Figure 1, the embedded-type electric Hold structure preparation method may include:

Step S110 forms middle layer 201 in the side of a substrate 101；

Step S120 forms the first supporting course 103 far from the side of substrate 101 in middle layer 201, as a result as shown in Figure 2；

Step S130 forms capacitor hole 202, and middle layer 201 and the first supporting course 103 are run through in capacitor hole 202, as a result as schemed Shown in 3；

Step S140 forms the first electrode 104 of the inner surface in covering capacitor hole 202, as a result as shown in Figure 4；

Step S150, it is separate to first electrode 104 with preset direction in the first side of the supporting course 103 far from substrate 101 The partial region of one end of substrate 101 carries out ion implanting (ion implantation), the extending direction in preset direction relative capacity hole 202 Inclination, as shown in Figure 5 and Figure 6；

Step S160, removal first electrode is by the region 203 of injection ion, so that first electrode 104 has opening 204, And 204 expose portion middle layers 201 of opening, as a result as shown in Figure 7；

Step S170 removes middle layer 201, as a result as shown in figure 13；

Step S180 forms the dielectric layer 105 of covering first electrode 104, as a result as shown in figure 14；

Step S190 forms the second electrode 106 of covering dielectric layer 105, as a result as shown in figure 15.

The preparation method for the embedded capacitor structure that the disclosure provides, after forming first electrode 104, with preset direction pair The partial region of the one end (i.e. 204 part of opening of first electrode 104) of first electrode 104 far from substrate 101 carries out ion note Enter, since the extending direction in ion implanting direction and capacitor hole 202 tilts, the one of 204 part of opening of first electrode 104 Side can not be by injection ion by injection ion, the other side.First electrode is by the region 203 of injection ion, due to doping The ion of injection, physicochemical property will change and generate difference with other regions of first electrode 104, can using the difference To remove region 203 of the first electrode by injection ion, and then opening 204 is formed in first electrode 104.The preparation method Form grid-pattern structures without infiltration type exposure machine, when also avoiding being formed grid-pattern structures with capacitor hole 202 Misregistration bring efficiency and yield reduce, and can efficiently and accurately form opening 204 in first electrode 104, reduce The preparation cost of capacitor, improves the preparation efficiency and yield of capacitor.

With reference to the accompanying drawing to disclosure embodiment provide embedded capacitor structure preparation method each step into Row is described in detail:

In step s 110, middle layer 201 can be formed on substrate 101 by modes such as deposition, vapor deposition or printings. The material of middle layer 201 can be selected and be determined according to the design requirement of embedded capacitor structure, can be organic insulation Material, or inorganic insulating material, or the mixing material for organic insulating material and inorganic insulating material.Citing and Speech, in one embodiment, the material of middle layer 201 can be one of silica and phosphosilicate glass or two kinds.It can With understanding, middle layer 201 can be one layer of insulation material layer, or the different insulating materials layer stackup of multilayer and At.

The thickness of middle layer 201 can be determined according to the depth in required capacitor hole 202.For example, real one It applies in mode, it is required that the depth in capacitor hole 202 is 800~1500 nanometers, since the depth in capacitor hole 202 depends on substrate The distance between the surface of 101 surface and the first supporting course 103 far from substrate 101, can be according to first supporting course 103 Thickness etc. determines the thickness of middle layer 201.

In the step s 120, the material of the first supporting course 103 can be organic or inorganic insulating material, such as can be Silicon nitride etc..Of course, the first supporting course 103 can be one layer of insulation material layer, or layer by layer by multi-layer insulation It is folded to form.

First supporting course 103 can be formed by the methods of deposition, including but not limited to chemical vapor deposition, physical vapor Deposition etc..The thickness of first supporting course 103 can be 60~100 nanometers, with enough support forces.For example, one In embodiment, the thickness of the first supporting course 103 can be 80 nanometers.

In step s 130, the method combined with etching can be exposed by infiltration type form capacitor hole 202.Such as Fig. 3 institute Show, the size in capacitor hole 202 is determined with the size of the embedded capacitor structure finally needed to form.

The first supporting course 103 is run through in capacitor hole 202, and the part in the first supporting course 103 is the first support holes 2021.

In one embodiment, the size in capacitor hole 202 can be nanoscale or submicron order, and especially less than 50 receive Meter level.For example, the size in capacitor hole 202 can be 15~50 nanometers.

It is understood that conductive contact pad can be set on substrate 101, being formed by capacitor hole 202 can expose to the open air The conductive contact pad at least partly so that first electrode 104 is connect with conductive contact pad.The material of conductive contact pad can be with Including one or more of tungsten, copper, molybdenum, gold, silver and platinum.

In step S140, vapor deposition, chemical vapor deposition, physical vapour deposition (PVD), sputtering or other methods can be passed through Form first electrode 104.It is understood that as shown in Figure 3 and Figure 4,202 inner surface of capacitor hole includes exposed substrate 101 Part and annular inner side wall, therefore the first electrode 104 is to cover exposed 101 part of substrate and annular inner side wall.Institute's shape At first electrode 104 can be in the form of a column, extending direction is consistent with the direction in capacitor hole 202, is each perpendicular to where substrate 101 Plane.First electrode 104 can have first end 1041 and second end 1042, wherein first end 1041 is set to the table of substrate 1 Face, second end 1042 are ordinatedly arranged in the first support holes 2021 far from the substrate 1.As shown in figure 4, first electrode 104 can have capacitor slot 205, and the notch of capacitor slot 205 is opened in second end 1042.In this way, entire first electrode 104 is led Electric part is in tubbiness open at one end.Due to capacitor slot 205, the inner surface of first electrode 104 is capacitor slot 205 Bottom surface and side, the outer surface of first electrode 104 is covered by substrate 1, middle layer 201 and the first supporting course 103.

The material of first electrode 104 can be metal, metal oxide, metal nitride or other conductive materials, sheet It is open not do special restriction to this.For example, in one embodiment, the material of first electrode 104 can for titanium nitride, Titanium or tungsten.

In step S150, as shown in figure 5, can be in the first side of the supporting course 103 far from substrate 101, with default side To progress ion implanting.When ion implanting, ion stream can irradiate entire first supporting layer, so if multiple first electrodes 104 simultaneously in the middle layer 201 and the first supporting course 103, then can simultaneously to multiple and different first electrodes 104 carry out from Son injection.

As shown in figure 5, since the preset direction of ion implanting and the extending direction in capacitor hole 202 tilt, such as Fig. 6 Shown, first electrode 104 will not be by injection ion, the opening of first electrode 104 close to one end (first end 1041) of substrate 101 Hold the side backwards to ion source of (second end 1042) will not be by injection ion, only first electrode 104 is in open end (second End 1042) meet to the partial region of ion source can by injection ion, formed doping.Therefore, which can make It is adulterated relative to other regions in a part of region of the open end (second end 1042) of one electrode 104.Ion doping will Change the physicochemical property of the material of corresponding first electrode 104, so that region and undoped area that first electrode 104 is doped Significant difference occurs for the physicochemical property between domain.Using the difference, the region for being doped first electrode 104 choosing may be implemented Remove to selecting property.

Preset direction can size, the size of the opening 204 needed to form, the first supporting course 103 according to capacitor hole 202 Thickness etc. calculated and determined.In one embodiment, it is required that first electrode is close by the region 203 of injection ion One end of substrate 101 is 50~100 nanometers close to the distance between the surface of substrate 101 h with the first supporting course 103, in this way, institute One end of the close substrate 101 of the opening 204 of formation is close to the distance between the surface of substrate 101 h with the first supporting course 103 50~100 nanometers.In another embodiment, the angle between 202 extending direction of preset direction and capacitor hole is not more than 30 °.

The selected ion of ion implanting can be selected and be determined according to the material of first electrode 104.Different materials Material, after being doped specific ion, physicochemical property will occur it is specific change, such as its etch rate will be promoted or It reduces.For example, Fig. 8 illustrates wet-etch rate of the silicon nitride under different doping, it can be seen that boron, carbon, silicon and The doping of the elements such as germanium can reduce the wet-etch rate of silicon nitride, and the doping of the elements such as oxygen, fluorine, phosphorus, argon and arsenic can mention The wet-etch rate of high silicon nitride.Fig. 9 illustrates wet-etch rate of the silica under different doping, it can be seen that The doping of the elements such as silicon, germanium and arsenic can reduce the wet-etch rate of silica, and the doping of the elements such as nitrogen, fluorine and phosphorus can mention The wet-etch rate of UZM-5 HS.Therefore, after material is doped with different ions, the rate of etching can become Change.

In one embodiment, may be selected that so that 104 material of first electrode to be doped rear etch rate raised Ion, in this way, can be in step S160, as shown in fig. 7, by etching the first electrode 104 that is doped of removal the Opening 204 is formed on one electrode 104.

It is understood that the ion injected can be a kind of ion, or the mixture of different kinds of ions.

It is understood that technical staff can obtain the etching speed of different material doped front and backs by different approach Rate situation of change.In one embodiment, relevant information can be obtained by inquiring existing documents and materials etc..In another implementation In mode, related data can be obtained by experiment.Related experiment may include the etch rate for measuring undoped material, with And the etch rate of the material of the different ions of measurement doping various concentration.For example, can with boron, phosphorus, arsenic, carbon, iron, The material that the ion pair of the difference element such as germanium, indium or argon is different is doped experiment, and obtains related data.

The selected implantation concentration of ion implanting, Implantation Energy etc. can be according to the materials of first electrode 104 and selected Ion be determined, this is not discussed in detail in the disclosure.

In step S160, as shown in fig. 7, first electrode can be removed by the method for etching by the region of injection ion 203, to form opening 204.For example, opening 204 can be formed by wet etching.

In one embodiment, the ion and flow of etching can be Ar (60sccm)/BCl₃(120sccm), biasing is penetrated Frequency power is 50W (Bias RF), and ion source radio-frequency power is 110W (Source RF), and etch period is according to material to be etched Thickness etc. be determined.

It is understood that as shown in figure 18, when multiple embedded capacitor structures are set on same substrate 1, Ge Ge The opening 204 of one electrode 104 is set to the same side of corresponding first electrode 104.

In step S170, as shown in figure 13, by opening 204, removal middle layer 201 can be etched, so that the first electricity The part exposure that the outer surface of pole 104 is covered by middle layer 201.

In step S180, as shown in figure 14, dielectric layer can be formed by the methods of vapor deposition, sputtering or vapor deposition 105, the material of dielectric layer 105 is selected according to the design requirement of embedded capacitor structure, this is not described in detail in the disclosure one by one.

It is understood that dielectric layer 105 can cover first electrode 104, refer to that dielectric layer 105 at least covers first The part of the inner surface and the outer surface exposure of electrode.Dielectric layer can also cover the part of other exposures, such as can cover the The part of one supporting layer 103 and the exposure of substrate 101.The material of the dielectric layer is aluminium oxide, silica, zirconium oxide and silicon nitride One or more of.

In step S180, as shown in figure 15, the second electricity can be formed by the methods of vapor deposition, sputtering or vapor deposition Pole 106, the material and structure of second electrode 106 can be identical as first electrode 104, can not also be identical, the disclosure to this not It is described in detail one by one.

In one embodiment, the lateral surface of dielectric layer 105 can be covered by second electrode completely.The appearance of dielectric layer Face, can refer to dielectric layer and the first supporting course, first electrode, substrate contact surface opposite face.

It is understood that as shown in figure 15, it is each embedded if multiple embedded capacitor structures are set to same substrate The second electrode of capacitance structure can connect as an entire public electrode.

In one embodiment, the preparation method of the embedded capacitor structure can also include:

Step S210, before step S110, as shown in Fig. 2, forming the second supporting course 107 on a substrate 101.Such as This, in step 110, middle layer 201 is formed in the second side of the supporting course 107 far from substrate 101.In step s 130, electric Hold hole 202 and runs through the second supporting course 107.Capacitor hole 202 can be the second support holes 2022 in the part of the second supporting course 107, The first end 1041 of first electrode 104 can be ordinatedly arranged in the second support holes 2022.In this way, in removal middle layer 201 Afterwards, the fixation to first electrode 104 may be implemented in the second supporting layer, it is ensured that complete, the guarantee of 104 position and structure of first electrode The yield of embedded capacitor structure.

In one embodiment, as shown in figure 16, the preparation method of the embedded capacitor structure can also include:

Step S310 forms planarization layer 102 far from the side of substrate 101 in second electrode 106, planarization layer 102 Material can be organic material or inorganic material.In one embodiment, the material of planarization layer 102 can be polysilicon.

It should be noted that although describing each step of method in the disclosure in the accompanying drawings with particular order, This does not require that or implies must execute these steps in this particular order, or have to carry out step shown in whole Just it is able to achieve desired result.Additional or alternative, it is convenient to omit multiple steps are merged into a step and held by certain steps Row, and/or a step is decomposed into execution of multiple steps etc., it is regarded as a part of this disclosure.

The disclosure additionally provides a kind of embedded capacitor structure, such as Figure 15 (illustrating multiple embedded capacitor structures) institute Show, which includes the first supporting course 103, first electrode 104, dielectric layer 105 and second electrode 106, wherein

First supporting course 103 is set to the side of a substrate 101, and has the first support holes 2021 (as shown in Figure 3)；First Electrode 104 (as shown in figure 13) is in the form of a column and extending direction is vertical with 101 place plane of substrate；First electrode, which has, is set to substrate The second end 1042 of the first end 1041 on 101 surfaces and separate substrate 101, and second end 1042 is ordinatedly arranged in the first bearing Hole 2021；First electrode 104 is equipped with capacitor slot 205, and the notch of capacitor slot 205 is set to second end 1042；Second end 1042 Side is equipped with opening 204, and opening 204 is located at the first supporting course 103 close to the surface of substrate 101 close to one end of substrate 101 Between substrate 101；Dielectric layer 105 covers first electrode 104；Second electrode 106 covers dielectric layer 105.

It is understood that first electrode 104 is in the form of a column and has capacitor slot 205 and opening 204, therefore, first electrode 104 have tubbiness jaggy in more specific structure for second end 1042, in the cross section of first end 1041 (perpendicular to prolonging Stretch direction) be a flat surface or annular, between first end 1041 and second end 1042 part (it is non-setting opening 204 portion Point) cross section be one annular；It is a tool annular jaggy in the cross section of the part of setting opening 204.First electrode 104 are in the form of a column, and refer to that first electrode 104 extends along the direction perpendicular to 101 place plane of substrate on the whole.This field skill Art personnel know that the column that first electrode is presented can be the column of non-uniform size, perpendicular to one of extending direction The shape or size of cross section can be not identical as the shape or size of another cross section.

The embedded capacitor structure can be described in the preparation method embodiment by above-mentioned embedded capacitor structure Preparation method prepared, do not need to form grid-pattern structures using infiltration type exposure machine in preparation process, and can be quasi- Opening 204 really and is efficiently formed in first electrode 104, is avoided caused by grid-pattern structures and capacitor hole misregistration The reduction of capacitor preparation efficiency and yield.

In one embodiment, the material of the first supporting course 103 can be silicon nitride.

In one embodiment, the thickness of the first supporting course 103 can be 60~100 nanometers.

In one embodiment, the length of first electrode 104 can be 800~1500 nanometers.The length of first electrode 104 Degree, refers to that first electrode 104 extends along the length and first electrode 104 in direction end face and substrate far from substrate 101 The distance between 101.

In one embodiment, first electrode 104 perpendicular to the section of its extending direction full-size can for 15~ 50 nanometers.

In one embodiment, as shown in fig. 7, opening 204 is close close to one end of substrate 101 and the first supporting course 103 The distance between the surface of substrate 101 h can be 50~100 nanometers.

In one embodiment, embedded capacitor structure further includes the second supporting course 107, and the second supporting course 107 is set to lining Between bottom 101 and the first supporting course 103, and there is second support holes 2022 corresponding with the first support holes 2021, first end 1041 are ordinatedly arranged in the second support holes 2022.

Wherein, dielectric layer 105 can cover the surface of the exposure of first electrode 104, including the covering exposure of first electrode 104 The part that inner surface and the outer surface for covering first electrode 104 expose.Of course, dielectric layer 104 can be with covering part One supporting course 103, substrate 101 or second supporting layer 107 etc..It is understood that since first electrode 104 is in the form of a column and is had Capacitor slot 205, therefore, the inner surface of first electrode 104 refer to forming the surface of capacitor slot 205；The appearance of first electrode 104 Face refers to the surface far from capacitor slot 205.

The material of the dielectric layer can be one or more of aluminium oxide, silica, zirconium oxide and silicon nitride.

Since second electrode 106 covers dielectric layer 105, dielectric layer 105 covers the inner surface and the outer surface of first electrode 104 Partial region, therefore, second electrode 106 can cover the partial region of the inner surface and the outer surface of first electrode 104.It compares In in the prior art, second electrode only forms capacitor, the embedded capacitance knot of the disclosure between the inner surface of first electrode Area is bigger between the pole plate of structure, so that the capacity of capacitor is bigger.

In one embodiment, embedded capacitor structure further includes planarization layer 102, and planarization layer 102 is formed in second Side of the electrode 106 far from substrate.The material of planarization layer 102 can be organic material or inorganic material, such as can be Polysilicon etc..

The disclosure additionally provides a kind of storage device, which may include above-mentioned embedded capacitor structure embodiment party Any embedded capacitor structure described in formula.

The reality of embedded capacitor structure and above-mentioned embedded capacitor structure that the storage device of disclosure embodiment uses The embedded capacitor structure applied in mode is identical, and therefore, beneficial effect having the same, details are not described herein.The storage device It can be DRAM (dynamic random access memory) or other storage devices.

It is understood that as shown in figure 15, storage device may include storage region 301 and peripheral region 302, storage It can be with the multiple embedded capacitor structures of the setting of array in region 301.It in one embodiment, as shown in figure 16, can be according to Following steps form the storage device:

Step S410, as shown in Fig. 2, being formed in covering storage region 301 and peripheral region 302 on a substrate 101 Interbed 201.

Step S420, as shown in Fig. 2, forming covering 301 He of storage region far from the side of substrate 101 in middle layer 201 First supporting course 103 of peripheral region 302.

Step S430, as shown in figure 3, forming the capacitor hole 202 of array setting in storage region 301；Wherein, substrate 101 It can be with each conductive contact pad with the conductive contact pad that is provided with of array, each capacitor hole 202 on 301 surface of storage region The one-to-one conductive contact pad being arranged and exposure is corresponding.

Step S440, as shown in figure 4, forming first electrode 104 in each capacitor hole 202.

Step S450, as shown in Figure 5 and Figure 6, in the first side of the supporting course 103 far from substrate 101, with preset direction pair The partial region of the one end (second end 1042) of each first electrode 104 far from substrate 101 carries out ion implanting, preset direction phase Extending direction inclination to capacitor hole 202.

Step S460, as shown in Fig. 7 and Figure 18, each first electrode is by the region 203 of injection ion, so that each first Electrode 104 has opening 204, and 204 expose portion middle layers 201 of each opening.

Step S470, as shown in Figure 10, the first side of the supporting course 103 far from substrate 101 forms first bearing of covering The protective layer 303 of layer 103.

Step S480 in side of the protective layer 303 far from substrate 101, forms a covering storage region as shown in Figure 10 301 photoresist layer 304.

Step S490 removes protective layer 303 and the first supporting course 103 is not photo-etched the covering of glue-line 304 as shown in figure 11 Part exposes the middle layer 201 of peripheral region 302.

Step S4100 removes photoresist layer 304 and protective layer 303 as shown in figure 12.

Step S4110 removes middle layer 201 as shown in figure 13.

Step S4120 forms the dielectric layer 105 of covering first electrode 104 as shown in figure 14.

Step S4130 forms the second electrode 106 of covering dielectric layer 105 as shown in figure 15.

Wherein, as shown in figure 18, in step S460, the opening 204 of each first electrode 104 is set to corresponding first electricity The same side of pole 104.

Wherein, in step S4120, dielectric can be formed on the surface of each exposure by the methods of chemical vapor deposition Layer 105.Then dielectric layer 105 can cover the surface of the exposure of first electrode 104, the interior table including the covering exposure of first electrode 104 The part that face and the outer surface for covering first electrode 104 expose.Of course, dielectric layer 104 can be first with covering part Layer 103, substrate 101 etc. are held, so that the dielectric layer 105 between different embedded capacitor structures is connected to become an entirety.

It is understood that since first electrode 104 is in the form of a column and has capacitor slot 205, first electrode 104 Inner surface refers to forming the surface of capacitor slot 205；The outer surface of first electrode 104 refers to the table far from capacitor slot 205 Face.

Wherein, in step S4130, second electrode 106 can cover entire dielectric layer 105, so each different embedding Entering the second electrode 106 between formula capacitance structure can connect as an entirety, become a common electrode layer.

In one embodiment, the preparation method of storage device can also include:

Step S4140 forms planarization layer 102 far from the side of substrate in second electrode 106.The material of planarization layer 102 Material can be organic material or inorganic material, such as can be polysilicon etc..

It should be appreciated that the disclosure is not limited in its application to the detailed construction and arrangement of the component of this specification proposition Mode.The disclosure can have other embodiments, and can realize and execute in many ways.Aforesaid deformation form and Modification is fallen within the scope of this disclosure.It should be appreciated that this disclosure and the disclosure of restriction extend in text And/or it is mentioned in attached drawing or all alternative combinations of two or more apparent independent features.It is all these different Combination constitutes multiple alternative aspects of the disclosure.Embodiment described in this specification illustrates to become known for realizing the disclosure Best mode, and those skilled in the art will be enable using the disclosure.

Claims

1. a kind of embedded capacitor structure characterized by comprising

First electrode, is in the form of a column and extending direction is vertical with plane where the substrate；The first electrode has set on described The second end of the first end of substrate surface and the separate substrate, and the second end is ordinatedly arranged in first bearing Hole；The first electrode is equipped with capacitor slot, and the notch of the capacitor slot is set to the second end；The side of the second end is set Have an opening, and it is described be open close to one end of the substrate be located at first supporting course close to the substrate surface with it is described Between substrate；

Dielectric layer covers the first electrode；

Second electrode covers the dielectric layer.

2. embedded capacitor structure according to claim 1, which is characterized in that the material of first supporting course is nitridation Silicon.

3. embedded capacitor structure according to claim 1, which is characterized in that first supporting course with a thickness of 60~ 100 nanometers.

4. embedded capacitor structure according to claim 1, which is characterized in that the length of the first electrode be 800~ 1500 nanometers.

5. embedded capacitor structure according to claim 1, which is characterized in that the first electrode is perpendicular to its extension side To section full-size be 15~50 nanometers.

6. embedded capacitor structure according to claim 1, which is characterized in that described to be open close to one end of the substrate With first supporting course close to the distance between surface of the substrate be 50~100 nanometers.

7. embedded capacitor structure according to claim 1, which is characterized in that the embedded capacitor structure further include:

Second supporting course is set between the substrate and first supporting course, and is had corresponding with first support holes Second support holes, the first end are ordinatedly arranged in second support holes.

8. embedded capacitor structure according to claim 1, which is characterized in that the dielectric layer covers the first electrode Inner surface and the first electrode outer surface at least partly region.

9. embedded capacitor structure according to claim 1, which is characterized in that the material of the dielectric layer be aluminium oxide, One or more of silica, zirconium oxide and silicon nitride.

10. a kind of storage device, which is characterized in that including embedded capacitor structure according to any one of claims 1 to 9.