CN209087830U - Integrated-circuit capacitor array structure and semiconductor memory - Google Patents
Integrated-circuit capacitor array structure and semiconductor memory Download PDFInfo
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- CN209087830U CN209087830U CN201821975221.0U CN201821975221U CN209087830U CN 209087830 U CN209087830 U CN 209087830U CN 201821975221 U CN201821975221 U CN 201821975221U CN 209087830 U CN209087830 U CN 209087830U
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Abstract
It includes: substrate that the utility model, which provides a kind of integrated-circuit capacitor array structure and semiconductor memory, integrated-circuit capacitor array structure,；Lower electrode layer, it is outstanding to be located on substrate, by being formed with capacitor hole in lower electrode layer；Capacitor dielectric layer conformally covers the surface of lower electrode layer；Upper electrode layer conformally covers the surface of capacitor dielectric layer；Capacitor plate, block shape is located on substrate and is formed on upper electrode layer, capacitor plate includes the metallic filler layers being sequentially stacked from the bottom to top and conformally covers the conductive covering layer of metallic filler layers, conductive covering layer is configured to the top surface layer and side surface layer of top electrode structure, so that engagement at least one first interconnection structure is in top surface layer.Integrated-circuit capacitor array structure provided by the utility model is it is possible to prevente effectively from leaky condenser；Meanwhile when forming capacitor plate can only deposited metal filled layer/conductive covering layer as capacitor plate can guarantee low resistance.
Description
Technical field
The utility model belongs to semiconductor devices and manufacturing field, more particularly to a kind of integrated-circuit capacitor array junctions
Structure, organization of semiconductor memory and its manufacturing method.
Background technique
In existing capacitor, due to the limitation of upper electrode layer material and depositing operation, fills and power in capacitor hole
Make to be easy to be formed with cavity in capacitor hole in top electrode structure when the material of pole, so that the resistance value of capacitor has differences, from
And it may cause electric leakage.
In order to improve the above problem, a kind of existing ameliorative way is that capacitor plate is formed at the top of capacitance structure
(PLATE), the capacitor plate can carry out a degree of filling to capacitor inside, reduce that resistance is non-uniform to ask to play
Topic.However, there are thickness is thicker and the problems such as processing step is complicated for existing capacitor plate.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of capacitor arrangement battle arrays
Column, organization of semiconductor memory and preparation method thereof, are had differences with solving resistance value existing for capacitor in the prior art,
So as to leading to electrical leakage problems, and form that capacitor plate thickness existing for capacitor plate is thicker and processing step is complicated asks
Topic.
In order to achieve the above objects and other related objects, the utility model provides a kind of integrated-circuit capacitor array junctions
Structure, the integrated-circuit capacitor array structure include:
Substrate；
Lower electrode layer, it is outstanding to be located on the substrate, by being formed with capacitor hole in the lower electrode layer；
Capacitor dielectric layer conformally covers the surface of the lower electrode layer；
Upper electrode layer conformally covers the surface of the capacitor dielectric layer；
Capacitor plate, block shape are located on the substrate and are formed on the upper electrode layer, and the capacitor plate includes
The metallic filler layers that are sequentially stacked from the bottom to top and the conductive covering layer for conformally covering the metallic filler layers, the conduction are covered
Cap rock is configured to the top surface layer and side surface layer of top electrode structure, so that engagement at least one first interconnection structure is in the top table
In surface layer.
Further include top electrode obturator as a kind of preferred embodiment of the utility model, is located at the upper electrode layer and institute
It states between capacitor plate and the capacitor hole is filled up in imporosity, the top surface of the capacitor plate from the top electrode obturator is prolonged
Extend to the periphery surface that the substrate is located at outside top electrode obturator overlay area.
As a kind of preferred embodiment of the utility model, the top electrode obturator is attached directly to the upper electrode layer
Surface is also formed between the adjacent lower electrode layer, and the top electrode obturator has top surface and side, and the metal is filled out
Fill the top surface and the side that layer is attached directly to the top electrode obturator.
As a kind of preferred embodiment of the utility model, the metallic filler layers are filled in the capacitor hole, with electrical connection
To the upper electrode layer and make to fill up form in the capacitor hole for imporosity.
As a kind of preferred embodiment of the utility model, the metallic filler layers are attached directly to the table of the upper electrode layer
Face, and the metallic filler layers are also formed between the lower electrode layer.
As a kind of preferred embodiment of the utility model, the capacitor hole is filled up in the upper electrode layer imporosity, and is electrically connected
It is connected to the capacitor plate.
It further include base layer support layer, middle support layer and top support layer as a kind of preferred embodiment of the utility model,
It is all formed on the substrate and connects, support the lower electrode layer；The base layer support layer is located at the bottom of the lower electrode layer
Portion periphery, the middle support layer are located at the intermediate position of the lower electrode layer, and the top support layer is located at the lower electrode
The opening periphery of layer.
A kind of preferred embodiment as the utility model, further includes:
Dielectric layer is formed on the substrate, and is covered on the upper surface, side and the substrate of the capacitor plate
Periphery surface；
First interconnection structure, be located at the dielectric layer in and on the capacitor plate, and with the capacitor plate
The conductive covering layer be connected；And
Second interconnection structure in the dielectric layer and is located at outside the overlay area of the capacitor plate, described second
Interconnection structure is longer than first interconnection structure.
As a kind of preferred embodiment of the utility model, several capacitance contact nodes and connection are formed on the substrate
Weld pad, the capacitance contact node are connected with the bottom of the lower electrode layer, the connection weld pad and the described second mutually connection
The bottom of structure is connected.
As a kind of preferred embodiment of the utility model, the upper electrode layer includes the titanium nitride that atomic layer deposition is formed
Layer, the metallic filler layers include tungsten layer, and the conductive covering layer includes tungsten nitride layer.
The utility model also provides a kind of semiconductor memory, and the semiconductor memory includes as in above-mentioned either a program
The integrated-circuit capacitor array structure.
The utility model also provides a kind of integrated-circuit capacitor array structure, the integrated-circuit capacitor array structure
Preparation method include the following steps:
1) substrate is provided；
2) sacrificial layer and supporting layer being alternately superimposed on are formed on Yu Suoshu substrate；
3) Patterned masking layer is formed on the sacrificial layer and supporting layer that Yu Suoshu is alternately superimposed on, in the Patterned masking layer
With multiple apertures, for defining position and the shape in capacitor hole；
4) supporting layer and the sacrificial layer are etched according to the Patterned masking layer, in the supporting layer and described
Capacitor hole is formed in sacrificial layer；
5) lower electrode layer is formed in Yu Suoshu capacitor hole, the supporting layer connects the lower electrode layer；
6) sacrificial layer is removed, wherein the supporting layer retains over the substrate；
7) inner surface of Yu Suoshu lower electrode layer and outer surface form capacitor dielectric layer, and the capacitor dielectric layer conformally covers
Cover the lower electrode layer；
8) surface of Yu Suoshu capacitor dielectric layer forms upper electrode layer, and the upper electrode layer conformally covers the capacitor and is situated between
The surface of matter layer；And
9) capacitor plate is formed on Yu Suoshu upper electrode layer, the capacitor plate block shape is located on the substrate and is formed
In on the upper electrode layer, the capacitor plate includes metallic filler layers being sequentially stacked from the bottom to top and conformally described in covering
The conductive covering layer of metallic filler layers, the conductive covering layer are configured to the top surface layer and side surface layer of top electrode structure, with
For in conjunction at least one first interconnection structure in the top surface layer.
It further include following steps between step 8) and step 9): Yu Suoshu as a kind of preferred embodiment of the utility model
The surface of upper electrode layer forms top electrode obturator, and the capacitor hole, the capacitor are filled up in top electrode obturator imporosity
The top surface of pole plate from the top electrode obturator extends to the week that the substrate is located at outside top electrode obturator overlay area
Side surface.
As a kind of preferred embodiment of the utility model, the top electrode obturator is attached directly to the upper electrode layer
Surface is also formed between the adjacent lower electrode layer, and the top electrode obturator has top surface and side, shape in step 9)
At the metallic filler layers be attached directly to the top surface and the side of the top electrode obturator.
As a kind of preferred embodiment of the utility model, the metallic filler layers formed in step 9) are filled in the electricity
Rong Kong, to be electrically connected to the upper electrode layer and make to be in the form of imporosity is filled up in the capacitor hole.
As a kind of preferred embodiment of the utility model, the metallic filler layers are attached directly to the table of the upper electrode layer
Face, and the metallic filler layers are also formed between the lower electrode layer.
As a kind of preferred embodiment of the utility model, the upper electrode layer imporosity formed in step 8) is filled up described
Capacitor hole, and it is electrically connected to the capacitor plate.
As a kind of preferred embodiment of the utility model, in step 1), several capacitance contacts are formed in the substrate
Node；In step 4), the capacitor hole of formation exposes the capacitance contact node；The supporting layer formed in step 2)
Including top support layer, middle support layer and base layer support layer, the top support layer, the middle support layer and the bottom
Supporting layer is all formed on the substrate, and is respectively positioned in the sacrificial layer, has spacing up and down.
As a kind of preferred embodiment of the utility model, step 9) includes the following steps:
9-1) step 8) resulting structures are placed in a processing chamber, using sputtering technology in the top electrode obturator
Top surface forms the metallic filler layers；And
It 9-2) is passed through nitrogen in Xiang Suoshu processing chamber, and the metallic filler layers are heated to fill out in the metal
The surface for filling layer forms the conductive covering layer.
As a kind of preferred embodiment of the utility model, step 9-2) in, the nitrogen is passed through in Xiang Suoshu processing chamber
Flow be 10 standard milliliters/minute~20 standard milliliters/minute.
As a kind of preferred embodiment of the utility model, it is also formed with connection weld pad in the substrate that step 1) provides,
The connection weld pad is located at outside the overlay area of the capacitor plate, further includes following steps after step 9):
10) dielectric layer is formed in the surface of step 9) resulting structures, the dielectric layer covers the upper table of the capacitor plate
The surface in face, side and the substrate；
11) the first connection through-hole and the second connection through-hole are formed in Yu Suoshu dielectric layer, wherein the first connection through-hole
On the capacitor plate and the conductive covering layer of the part capacitor plate is exposed, the second connection through-hole exposes
The part connection weld pad, the second connection through-hole are longer than the one the first connections through-hole；And
12) the first interconnection structure is formed in the connection of Yu Suoshu first through-hole, and in forming the in the second connection through-hole
Two interconnection structures, first interconnection structure are in contact with the capacitor plate, and second interconnection structure and the connection are welded
Pad is in contact.
As a kind of preferred embodiment of the utility model, in step 8), it is situated between using atom layer deposition process in the capacitor
The surface titanium nitride layer of matter layer is as the upper electrode layer, and the metallic filler layers include tungsten layer, and the conduction is covered
Cap rock includes tungsten nitride layer.
The utility model also provides a kind of preparation method of semiconductor memory, the preparation method of the semiconductor memory
Including preparing IC capacitor using the preparation method of the integrated-circuit capacitor array structure as described in above-mentioned either a program
The step of device array structure.
As described above, the integrated-circuit capacitor array structure and semiconductor memory of the utility model, have with following
Beneficial effect:
Integrated-circuit capacitor array structure provided by the utility model is it is possible to prevente effectively from leaky condenser；Meanwhile
Without depositing SiGe when forming capacitor plate, and only deposited metal filled layer/conductive covering layer can be protected as capacitor plate
Demonstrate,prove low resistance；
Made in integrated-circuit capacitor array structure provided by the utility model using metallic filler layers and conductive covering layer
For capacitor plate, metallic filler layers can be used as the etching barrier layer for forming connection through-hole above it, can be formed in etching
Effectively avoided during connection through-hole over etching perforate or etch it is not in place caused by connection through-hole the problems such as being not switched on
Occur；Meanwhile tungsten has lower resistivity compared to SiGe, the thickness in the case where guaranteeing to obtain required electric property
Can be smaller, so as to reduce the height of connection through-hole, be conducive to the progress of subsequent technique.
Detailed description of the invention
The cross section structure that Fig. 1 is shown as the integrated-circuit capacitor array structure provided in the utility model embodiment one shows
It is intended to.
Fig. 2 is shown as the preparation process stream of the integrated-circuit capacitor array structure provided in the utility model embodiment two
Cheng Tu.
Fig. 3 is shown as the step of the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 1) resulting structures.
Fig. 4 is shown as the step of the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 2) resulting structures.
Fig. 5 is shown as the step of the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 3) resulting structures.
Fig. 6 is shown as the step of the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 4) resulting structures.
Fig. 7 is shown as the step of the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 5) resulting structures.
Fig. 8 is shown as the step of the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 6) resulting structures.
Fig. 9 is shown as the step of the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 7) resulting structures.
Figure 10 to Figure 11 is shown as the integrated-circuit capacitor array structure provided in the utility model embodiment two preparation
The cross section structure schematic diagram of the step 8) resulting structures of method.
Figure 12 is shown as the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram figure of step 9) resulting structures.
Figure 13 is shown as the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram figure of step 10) resulting structures.
Figure 14 is shown as the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram figure of step 11) resulting structures.
Figure 15 is shown as the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment two
The cross section structure schematic diagram figure of step 12) resulting structures.
Figure 16 is shown as the cross section structure of the integrated-circuit capacitor array structure provided in the utility model embodiment three
Schematic diagram.
Figure 17 to Figure 18 is shown as the integrated-circuit capacitor array structure provided in the utility model embodiment four preparation
The cross section structure schematic diagram of the step 8) resulting structures of method.
Figure 19 is shown as the cross section structure of the integrated-circuit capacitor array structure provided in the utility model embodiment five
Schematic diagram.
Figure 20 is shown as the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment six
The cross section structure schematic diagram of step 8) resulting structures.
Figure 21 is shown as the integrated-circuit capacitor array structure preparation method provided in the utility model embodiment six
The cross section structure schematic diagram of step 9) resulting structures.
Component label instructions
10 substrates
111 lower electrode layers
12 capacitor dielectric layers
112 upper electrode layers
13 top electrode obturators
131 top surfaces
132 sides
14 capacitor plates
141 metallic filler layers
142 titanium nitride layers
15 base layer support layers
16 middle support layers
17 top support layers
171 first openings
18 dielectric layers
181 first connection through-holes
182 second connection through-holes
19 first interconnection structures
20 second interconnection structures
21 capacitance contact nodes
211 diffusion barrier layers
22 connection weld pads
23 sacrificial layers
24 Patterned masking layers
241 apertures
25 capacitor holes
S1~S9 step 1)~step 9)
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Fig. 1 is please referred to Figure 15.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
As shown in Figure 1, the utility model provides a kind of integrated-circuit capacitor array structure, the integrated-circuit capacitor
Array structure includes: substrate 10；Lower electrode layer 111, the lower electrode layer 111 is outstanding to be located on the substrate 10, by described
Capacitor hole is formed in lower electrode layer 111；Capacitor dielectric layer 12, the capacitor dielectric layer 12 conformally cover the lower electrode layer
111 surface；Upper electrode layer 112, the upper electrode layer 112 are located on the substrate 10 and conformally cover the capacitor dielectric
The surface of layer 12；And capacitor plate 14, the 14 block shape of capacitor plate are located on the substrate 10 and are formed in described power on
On pole layer 112, the capacitor plate 14 includes the metallic filler layers 141 being sequentially stacked from the bottom to top and conformally covers the gold
Belong to the conductive covering layer 142 on filled layer, the conductive covering layer 142 is configured to top surface layer and the side surface of top electrode structure
Layer, in conjunction at least one first interconnection structure 19 in the top surface layer.
As best illustration, the design of the aperture more downsizing suitable for capacitor hole, 112 imporosity of upper electrode layer
The capacitor hole is filled up, and is electrically connected to the capacitor plate 14.Integrated-circuit capacitor array junctions provided by the utility model
The upper electrode layer 112 in structure specifically can be is filled titanium nitride and is formed with non-porous be filled in the capacitor hole, so as to
Effectively to avoid leaky condenser；Meanwhile the upper electrode layer 112 is formed with non-porous filling, forming the capacitor plate 14
Shi Wuxu deposits the semiconductors hole packing materials such as SiGe, and only deposits the metallic filler layers 141 and the conductive covering
Layer 142 can guarantee low resistance as the capacitor plate 14；Integrated-circuit capacitor array structure provided by the utility model
It is middle to be used as the capacitor plate 14, the metallic filler layers using the metallic filler layers 141 and the conductive covering layer 142
141 can be used as the etching barrier layer for forming connection through-hole above it, can form the process for connecting through-hole in etching
In effectively avoid over etching perforate or etch it is not in place caused by connection through-hole the problems such as being not switched on generation；Meanwhile tungsten phase
There is lower resistivity compared with SiGe, in the case where guaranteeing to obtain required electric property, thickness can be smaller, thus
The height that connection through-hole can be reduced, is conducive to the progress of subsequent technique.
As an example, the ground of the substrate 10 can be the semiconductor material of such as silicon, surface could be formed with memory
Array transistor arrangement and dielectric layer, the memory array structure may include several capacitors being located in memory array structure
Contact node 21 and several connection weld pads 22, the capacitance contact node 21 may include tungsten pad, the connection pad 22
It also may include tungsten pad.The memory array structure can also include transistor wordline (Word line) and bit line
(Bitline), the bottom of the capacitance contact node 21 is electrically connected the transistor source in the memory array structure, described
The top of capacitance contact node 21 is connected with the bottom of the lower electrode layer 111.The bottom of the capacitance contact node 21 or/
And the surface of side can form diffusion barrier layer (211)；Specifically, the diffusion barrier layer has the shape in U-shaped section.
As an example, the capacitance contact node 21 can with but be not limited only in six square arrays arrange, the capacitance contact
Node 21 can be corresponding with the capacitor arrangement in the integrated-circuit capacitor array structure.
As an example, between the capacitance contact node 21, between the connection weld pad 22 and the capacitance contact node
It can be isolated by isolation structure between 21 and the connection welding 22, the material of the isolation structure may include nitridation
At least one of silicon, silica and aluminium oxide.
As an example, the lower electrode layer 111 may include one or both of metal nitride and metal silicide
It is formed by conductive compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), silicon
Change nickel (Titanium Silicide), silicon titanium nitride (TiSixNy).In the present embodiment, the lower electrode layer 111 may include atom
The titanium nitride layer that layer deposition (ALD) is formed.The shape of the lower electrode layer 111 can protrude from the substrate with elongated tubular product
10.The arrangement of the lower electrode layer 111 of multiple tubuloses can arrange in six square arrays.
As an example, the capacitor dielectric layer 12 can be high-K dielectric layer, to improve the capacitor of unit-area capacitance device
Value comprising ZrOx、HfOx、ZrTiOx、RuOx、SbOx、AlOxOne of or the formed group of above-mentioned material in two kinds with
On be formed by lamination.The capacitor dielectric layer 12 specifically conformally cover lower electrode layer 111 described in tubulose expose to it is described
The inner surface of substrate 10 and outer surface.
As an example, the upper electrode layer 112 may include one or both of metal nitride and metal silicide
It is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide
(Titanium Silicide), silicon titanium nitride (TiSixNy).Preferably, in the present embodiment, the upper electrode layer 112 includes original
Sublayer deposits the titanium nitride layer that (ALD) is formed.Outer profile of the upper electrode layer 112 particularly along the lower electrode layer 111
It is attached directly to the surface of the capacitor dielectric layer 12.
As an example, the metallic filler layers 141 may include tungsten layer, the conductive covering layer 142 may include nitridation
Tungsten layer.
As an example, the metallic filler layers 141 can directly be electrically connected the upper electrode layer 112.
As an example, the top surface of the capacitor plate 14 from the upper electrode layer 112 extends to the surface of the substrate 10,
To coat capacitor array.
As an example, the integrated-circuit capacitor array structure further include base layer support layer 15, middle support layer 16 and
Top support layer 17 is all formed on the substrate 10 and connects, supports the lower electrode layer 111；The base layer support layer 15
Positioned at the bottom periphery of the lower electrode layer 111, the middle support layer 16 is located at the intermediate position of the lower electrode layer 111,
The top support layer 17 is located at the opening periphery of the lower electrode layer 111, and perpendicular to the U-shaped of the lower electrode layer 111
Side wall extending direction.
As an example, 17 parallel interval of the base layer support layer 15, the middle support layer 16 and the top support layer
Arrangement.
As an example, the base layer support layer 15, the middle support layer 16 and the top support layer 17 can wrap
It includes but is not limited only to silicon nitride layer.
As an example, the array of capacitors structure further can also include: dielectric layer 18, the first interconnection structure 19 and
Second interconnection structure 20；The dielectric layer 18 is formed on the substrate 10, and be covered in the capacitor plate 14 upper surface,
Periphery surface on side and the substrate 10；First interconnection structure 19 is located in the dielectric layer 18 and in the capacitor
On pole plate 14, and it is connected with the conductive covering layer 142 of the capacitor plate 14,14 electricity of capacitor plate is drawn
Out, specifically, first interconnection structure 19 can be connected with the upper surface of the capacitor plate 14；Described second mutually connection
Structure 20 is located in the dielectric layer 18, and be located at the capacitor plate 14 overlay area outside, second interconnection structure 20 compared with
It is longer than first interconnection structure 19, the bottom of second interconnection structure 20 is connected with the connection weld pad 22, by institute
Connection 22 electricity of weld pad is stated to draw.
As an example, the dielectric layer 18 may include but be not limited only to silicon oxide layer or silicon nitride layer.Described first mutually
The material of connection structure 19 and second interconnection structure 20 may include but be not limited only to tungsten (W), copper (Cu), nickel (Ni), gold
(Au) or silver-colored (Ag) etc..The form of first interconnection structure 19 and second interconnection structure 20 can be embolism.
Embodiment two
Incorporated by reference to Fig. 2, the utility model also provides a kind of preparation method of integrated-circuit capacitor array structure, the collection
Preparation method at circuit capacitor array structure includes the following steps:
1) substrate is provided；
2) sacrificial layer and supporting layer being alternately superimposed on are formed on Yu Suoshu substrate；
3) Patterned masking layer is formed on the sacrificial layer and supporting layer that Yu Suoshu is alternately superimposed on, in the Patterned masking layer
With multiple apertures, for defining position and the shape in capacitor hole；
4) supporting layer and the sacrificial layer are etched according to the Patterned masking layer, in the supporting layer and described
Capacitor hole is formed in sacrificial layer；
5) lower electrode layer is formed in Yu Suoshu capacitor hole, the supporting layer connects the lower electrode layer；
6) sacrificial layer is removed, wherein the supporting layer retains over the substrate；
7) inner surface of Yu Suoshu lower electrode layer and outer surface form capacitor dielectric layer, and the capacitor dielectric layer conformally covers
Cover the lower electrode layer；
8) surface of Yu Suoshu capacitor dielectric layer forms upper electrode layer, and the upper electrode layer covers the capacitor dielectric layer
Surface；And
9) capacitor plate is formed on Yu Suoshu upper electrode layer, the capacitor plate block shape is located on the substrate and is formed
In on the upper electrode layer, the capacitor plate includes metallic filler layers being sequentially stacked from the bottom to top and conformally described in covering
The conductive covering layer of tungsten layer, the conductive covering layer is configured to the top surface layer and side surface layer of top electrode structure, for combining
At least one first interconnection structure is in the top surface layer.
In step 1), S1 step and Fig. 3 in Fig. 2 are please referred to, a substrate 10 is provided.
As an example, could be formed with memory array structure in the substrate 10, the memory array structure be may include
Several are located at capacitance contact node 21 in memory array structure and several connection weld pads 22, and the connection pad 22 can be with
Including tungsten pad.The memory array structure can also include transistor wordline (Word line) and bit line (Bitline), institute
The bottom for stating capacitance contact node 21 is electrically connected transistor source in the memory array structure, the capacitance contact node
21 top is connected with the bottom of the lower electrode layer 111.
As an example, the capacitance contact node 21 can with but be not limited only in six square arrays arrange, the capacitance contact
Node 21 can be corresponding with the capacitor arrangement in the integrated-circuit capacitor array structure.
As an example, between the capacitance contact node 21, between the connection weld pad 22 and the capacitance contact node
It can be isolated by isolation structure between 21 and the connection welding 22, the material of the isolation structure may include nitridation
At least one of silicon, silica and aluminium oxide.
In step 2), S2 step and Fig. 4 in Fig. 2 are please referred to, forms the sacrifice being alternately superimposed on Yu Suoshu substrate 10
Layer 23 and supporting layer 15,16,17.
As an example, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition
Technique (Chemical Vapor Deposition) forms the sacrificial layer 23 and supporting layer 15,16,17.
As an example, the sacrificial layer 23 is different from the material of the supporting layer, using described in same etching processing procedure
The etch rate of sacrificial layer 23 is different from the etch rate of the supporting layer, is embodied in subsequent same wet etching system
The etch rate of Cheng Zhong, the sacrificial layer 23 are far longer than the etch rate of the supporting layer, so that working as 23 quilt of sacrificial layer
When completely removing, the supporting layer 15,16,17 can be almost fully retained (as shown in Figure 8).
Preferably, in the present embodiment, the sacrificial layer 23 can be polysilicon layer or boron-phosphorosilicate glass (Boro
Phospho Silicate Glass, BPSG), the supporting layer can be silicon nitride layer.
As an example, the supporting layer includes top support layer 17, the middle support layer 16 and base layer support layer 15, institute
It states top support layer 17, the middle support layer 16 and the base layer support layer 15 to be all formed on the substrate 10, and mutually
Between supporting layer can the sacrificial layer 23 separate, so that the supporting layer is mutually separated with spacing up and down.
In step 3), S3 step and Fig. 5 in Fig. 2, the sacrificial layer 23 and supporting layer that Yu Suoshu is alternately superimposed on are please referred to
15, Patterned masking layer 24 is formed on 16,17, there are multiple apertures 241 in the Patterned masking layer 24, for defining electricity
Hold position and the shape in hole 25.
As an example, firstly, forming photoresist conduct in the upper surface of the sacrificial layer 23 and supporting layer being alternately superimposed on
Mask layer can also form the mask layer (for example, silicon nitride hard mask layer etc.) of other materials certainly in other examples；
Then, using photoetching process that the mask layer is graphical, to obtain that there is the Patterned masking layer of the aperture 241
24。
As an example, the opening 241 can arrange along the surface of the Patterned masking layer 24 in six square arrays, it can be right
The quasi- capacitance contact node 21.
It should be noted that the opening 241 in the Patterned masking layer 24 also defines capacitor array periphery
The shape in region and position.
In step 4), S4 step and Fig. 6 in Fig. 2 are please referred to, etches the branch according to the Patterned masking layer 24
Layer and the sacrificial layer 23 are supportted, to form capacitor hole 25 in the supporting layer and the sacrificial layer 23.
As an example, step 4) method particularly includes: dry etch process can be used according to the Patterned masking layer 24
Or plasma strengthening dry etch process etches the supporting layer and the sacrificial layer 23, in the supporting layer and the sacrifice
The capacitor hole 25 up and down is formed in layer 23, the capacitor hole 25 exposes the capacitance contact node 21, such as Fig. 6 institute
Show.
It should be noted that when the opening 241 in the Patterned masking layer 24 also defines capacitor array periphery
Region shape and when position, the also removal supporting layer and the sacrifice that are located at the capacitor array periphery in the step
Layer 23.
It should be further noted that the base layer support layer 15 positioned at capacitor array peripheral region can after step 4)
To retain as shown in Figure 8, can also be removed in step 4).
In steps 5), S5 step and Fig. 7 in Fig. 2 are please referred to, forms lower electrode layer 111 in Yu Suoshu capacitor hole 25,
The supporting layer 15,16,17 connects the lower electrode layer 111.
As an example, firstly, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor
The side wall in the Yu Suoshu capacitor hole 25 depositing operation (Chemical Vapor Deposition) and bottom and the sacrificial layer
Lower electrode material layer is deposited on 23, the lower electrode material layer includes one or both of metal nitride and metal silicide
It is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide
(Titanium Silicide), silicon titanium nitride (TiSixNy)；Then, then using etching technics removal it is located at the sacrificial layer 23
On the lower electrode material layer, reservation positioned at the side wall in the capacitor hole 25 and the lower electrode material layer, that is, shape of bottom
As the lower electrode layer 111.
In step 6), S6 step and Fig. 8 in Fig. 2 are please referred to, wet-etching technology or combinations thereof removal institute can be used
State sacrificial layer 23, wherein the supporting layer 15,16,17 is retained on the substrate 10.
As an example, step 6) specifically may include following steps:
6-1) prior to forming the first opening 171 in the top support layer 17, first opening 171 exposes described sacrificial
First part of the domestic animal layer 23 between the top support layer 17 and the middle support layer 16；
6-2) by first opening 171, the sacrificial layer 23 is removed using wet-etching technology and is located at the top layer
The first part between supporting layer 17 and the middle support layer 16；
6-3) for forming the second opening, second opening in the first opening 171, Yu Suoshu middle support layer 16
Expose second part of the sacrificial layer 23 between the middle support layer 16 and the substrate 10；
It 6-4) is open by described second, the sacrificial layer 23 is removed using wet-etching technology and is located at the intermediate supports
The second part between layer 26 and the substrate 10.
As an example, step 6-2) and step 6-3) between further include in the top support layer 17 upper surface deposition branch
The step of supportting layer material, the top support layer 17 is thickened.This is because during step 6-2), the top layer branch
Support layer 17 can be removed a part, and the top support layer 17 is cut through during subsequent corrosion in order to prevent, and ensures institute
Top support layer 17 is stated with enough support strengths, is needed in step 6-2) and step 6-3) between add in the top layer branch
The step of supportting the upper surface depositing support layer material of layer 17.
As an example, step 6-1) in, first opening 171 can be handed over only with 25 part of capacitor hole
It folds, or/and first opening 171 is overlapping with multiple 25 parts of capacitor holes simultaneously；Step 6-2) in, one
Second opening can be only overlapping with 25 part of the capacitor hole, or/and second opening simultaneously with
Multiple 25 parts of the capacitor hole are overlapping.
It in step 7), please refers to shown in S7 step and Fig. 9 in Fig. 2, the inner surface of Yu Suoshu lower electrode layer 111 and outer
Surface forms capacitor dielectric layer 12, and the capacitor dielectric layer 12 conformally covers the lower electrode layer 111.
As an example, the material of the capacitor dielectric layer 12 can be selected as high K dielectric material, to improve unit area electricity
The capacitance of container comprising one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or above-mentioned material group are in groups
Two or more in group are formed by lamination.
In step 8), the S8 step and Figure 10 to Figure 11 in Fig. 2, the surface shape of Yu Suoshu capacitor dielectric layer 12 are please referred to
At upper electrode layer 112, the upper electrode layer 112 covers the surface of the capacitor dielectric layer 12.
As an example, the upper electrode layer 112 can fill up the capacitor hole 25 with imporosity, and described for being electrically connected to
Capacitor plate 14.
As an example, the surface cvd nitride of atom layer deposition process (ALD) Yu Suoshu capacitor dielectric layer 12 can be used
Titanium layer is as the upper electrode layer 112.
As an example, the upper electrode layer 112 can also be covered in capacitor battle array at the beginning of the upper electrode layer 112 is formed
Region except column, and also it is covered in the region (as shown in Figure 10) where the connection weld pad 22；At this point, also needing to execute removal
The step of positioned at the upper electrode layer 112 of the exterior domain of capacitor array, resulting structures are as shown in figure 11 after removal.
In step 9), S9 step and Figure 12 in Fig. 2 are please referred to, forms capacitor plate on Yu Suoshu upper electrode layer 112
14, the 14 block shape of capacitor plate is located on the substrate 10 and is formed on the upper electrode layer 112, the capacitor plate
14 include the metallic filler layers 141 being sequentially stacked from the bottom to top and the conductive covering for conformally covering the metallic filler layers 141
Layer 142, the conductive covering layer 142 is configured to the top surface layer and side surface layer of top electrode structure, for combining at least 1 the
One interconnection structure is in the top surface layer.
As an example, step 9) includes the following steps:
9-1) step 8) resulting structures are placed in a processing chamber, using sputtering technology in the upper electrode layer 112
Surface forms the metallic filler layers 141；And
It 9-2) is passed through nitrogen in Xiang Suoshu processing chamber, and the metallic filler layers 141 are heated in the gold
The surface for belonging to filled layer 141 forms the conductive covering layer 142.
As an example, step 9-2) in, the flow that the nitrogen is passed through in Xiang Suoshu processing chamber can be 10 standards milli
Liter/min~20 standard milliliters/minute.
As an example, the top surface of the capacitor plate 14 from the upper electrode layer 112 extends to the surface of the substrate 10,
To coat capacitor array.
As an example, the metallic filler layers 141 are electrically connected the upper electrode layer 112 in the lower electrode layer 111
Part and the part between the lower electrode layer 111.
As an example, the metallic filler layers 141 may include tungsten layer, the conductive covering layer 142 may include nitridation
Titanium layer.
It using the metallic filler layers 141 and described is led in integrated-circuit capacitor array structure provided by the utility model
Electric coating 142 is used as the capacitor plate 14, and the metallic filler layers 141 can be used as forms connection through-hole above it
Etching barrier layer, can effectively be avoided during etching forms the connection through-hole over etching perforate or etch it is not in place and
The generation for the problems such as caused connection through-hole is not switched on；Meanwhile tungsten has lower resistivity compared to SiGe, is guaranteeing to obtain
Thickness can be smaller in the case where obtaining required electric property, so as to reduce the height of connection through-hole, is conducive to subsequent work
The progress of skill.
Further include following steps after step 9) as an example, please referring to Figure 13 to Figure 15:
10) dielectric layer 18 is formed in the surface of step 9) resulting structures, the dielectric layer 18 covers the capacitor plate 14
Upper surface, side and the substrate 10 surface；Specifically, physical gas-phase deposition, chemical vapor deposition can be used
Technique or atom layer deposition process are in the substrate of the upper surface of the capacitor plate 14 and side and array region periphery
10 surface forms the dielectric layer 18, as shown in figure 13；The dielectric layer 18 may include but be not limited only to silicon oxide layer or
Silicon nitride layer；
11) the first connection through-hole 181 and the second connection through-hole 182 are formed in Yu Suoshu dielectric layer 18, wherein described first
Connection through-hole 181 is located on the capacitor plate 14, and exposes the conductive covering layer of the part capacitor plate 14
142, the second connection through-hole 182 exposes the part connection weld pad 22, and the second connection through-hole 182 is longer than described
First connection through-hole 181, as shown in figure 14；Specifically, first connection can be formed using photoetching and dry etch process
Through-hole 181 and the second connection through-hole 182；And
12) the first interconnection structure 19 is formed in the connection of Yu Suoshu first through-hole 181, and in the second connection through-hole 182
The second interconnection structure 20 of interior formation, first interconnection structure 19 are in contact with the capacitor plate 14, the described second mutually connection
Structure 20 is in contact with the connection weld pad 22, as shown in figure 15；Specifically, can be using techniques such as plating, depositions described the
Deposits tungsten (W), copper (Cu), nickel (Ni), gold (Au) or silver (Ag) etc. in one connection through-hole 181 and the second connection through-hole 182
Deng to form first interconnection structure 19 and second interconnection structure 20.
Embodiment three
Figure 16 and control reference Fig. 1 are please referred to, the utility model also provides a kind of integrated-circuit capacitor array structure, this
Integrated-circuit capacitor array structure as described in the examples and integrated-circuit capacitor array structure described in implementation one are big
Cause identical, the difference of the two is: the capacitor hole is filled up in 112 imporosity of the upper electrode layer in embodiment one；This implementation
In the unfilled capacitor hole of the upper electrode layer 112, compared to embodiment one, integrated circuit described in the present embodiment electricity
Vessel array structure further includes top electrode obturator 13, and the top electrode obturator 13 is located at the upper electrode layer 112 and described
The capacitor hole is filled up between capacitor plate 114 and imporosity, and the capacitor plate 14 is from the top electrode obturator 13
Top surface extends to the periphery surface that the substrate 10 is located at outside 13 overlay area of top electrode obturator, is suitable for the capacitor
The biggish design in the aperture in hole.
As an example, the surface that the top electrode obturator 13 is attached directly to the upper electrode layer 112 is also formed into phase
Between the adjacent lower electrode layer 111, the top electrode obturator 13 3 has top surface 131 and side 132, the metal filling
Layer 141 is attached directly to the top surface 131 and the side 132 of the top electrode obturator 13.
As an example, the top electrode obturator 13 may include but be not limited only to polysilicon layer or SiGe (SiGe)
Layer.The upper surface of the top electrode obturator 13 is higher by 10nm~100nm compared to the top of the capacitor dielectric layer 12.
Collection described in the other structures Yu embodiment one of integrated-circuit capacitor array structure described in the present embodiment
It is identical at corresponding structure in circuit capacitor array structure, referring specifically to embodiment one, it is not repeated herein.
Example IV
Figure 17 to Figure 18 is please referred to, the utility model also provides a kind of preparation side of integrated-circuit capacitor array structure
Method, corresponding diagram 2 is to Figure 15 institute in the preparation method Yu embodiment two of integrated-circuit capacitor array structure described in this implementation
The preparation method for the integrated-circuit capacitor array structure stated is roughly the same, and the difference of the two is: step 8) in embodiment two
The capacitor hole 25 is filled up in 112 imporosity of the upper electrode layer of middle formation；And formed in step 8) in this implementation it is described on
The unfilled capacitor hole 25 of electrode layer 112, and further include following steps between step 8) and step 9): Yu Suoshu upper electrode layer
112 surface forms top electrode obturator 13, and the capacitor hole 25, the capacitor are filled up in 13 imporosity of top electrode obturator
The top surface of pole plate 14 from the top electrode obturator 13 extends to the substrate 10 and is located at 13 area of coverage of top electrode obturator
Overseas periphery surface.
As an example, the surface that the top electrode obturator 13 is attached directly to the upper electrode layer 112 is also formed into phase
Between the adjacent lower electrode layer 111, the top electrode obturator 13 has top surface 131 and level 132；The institute formed in step 9)
State the top surface 131 and the side 132 that metallic filler layers 141 are attached directly to the top electrode obturator 13.
As an example, the top electrode obturator 13 may include but be not limited only to titanium nitride obturator.The top electrode
The upper surface of obturator 13 is higher by 10nm~100nm compared to the top of the capacitor dielectric layer 12.
In other steps and embodiment two of the preparation method of integrated-circuit capacitor array structure described in this implementation
Corresponding step is identical in the preparation method of the integrated-circuit capacitor array structure, referring specifically to embodiment two, this
Place is not repeated.
Embodiment five
Figure 19 and control reference Fig. 1 are please referred to, the utility model also provides a kind of integrated-circuit capacitor array structure, this
Integrated-circuit capacitor array structure as described in the examples and integrated-circuit capacitor array structure described in implementation one are big
Cause identical, the difference of the two is: the capacitor hole is filled up in 112 imporosity of the upper electrode layer in embodiment one；This implementation
In the unfilled capacitor hole of the upper electrode layer 112, the metallic filler layers 141 in the present embodiment are filled in the electricity
Hold in hole, to be electrically connected to the upper electrode layer 112 and make to be in the form of imporosity is filled up, to be suitable for the electricity in the capacitor hole
Hold the design of the aperture size moderate in hole.
As an example, the metallic filler layers 141 are attached directly to the surface of the upper electrode layer 112, and the metal
Filled layer 141 is also formed between the lower electrode layer 111.
Collection described in the other structures Yu embodiment one of integrated-circuit capacitor array structure described in the present embodiment
It is identical at corresponding structure in circuit capacitor array structure, referring specifically to embodiment one, it is not repeated herein.
Embodiment six
Incorporated by reference to Fig. 2 to Figure 15 refering to Figure 20 to Figure 21, the utility model also provides a kind of integrated-circuit capacitor array
The preparation method of structure, described in the preparation method Yu embodiment two of integrated-circuit capacitor array structure described in this implementation
Integrated-circuit capacitor array structure preparation method it is roughly the same, the difference of the two is: in embodiment two in step 8)
The capacitor hole 25 is filled up in 112 imporosity of the upper electrode layer formed；And the described of formation powers in step 8) in this implementation
The pole 112 unfilled capacitor hole 25 of layer, the middle metallic filler layers 141 formed of step 9) are filled in the capacitor hole 25
It is interior, to be electrically connected the upper electrode layer 112, and make to fill up form in the capacitor hole 25 for imporosity, i.e., the described metal filling
The capacitor hole 25 is filled up in 141 imporosity of layer.
As an example, the metallic filler layers 141 are attached directly to the surface of the upper electrode layer 112, and the metal
Filled layer 141 is also formed between the lower electrode layer 111.
In other steps and embodiment two of the preparation method of integrated-circuit capacitor array structure described in this implementation
Corresponding step is identical in the preparation method of the integrated-circuit capacitor array structure, referring specifically to embodiment two, this
Place is not repeated.
Embodiment seven
Please continue to refer to Fig. 1, Figure 16 and 19, the present embodiment also provides a kind of semiconductor memory, the semiconductor storage
Device includes using the integrated-circuit capacitor array structure as described in any in embodiment one, embodiment three or embodiment five.Institute
The specific structure for stating integrated-circuit capacitor array structure please refers to embodiment one, embodiment three and embodiment five, herein no longer
It is tired to state.
As an example, wherein, the organization of semiconductor memory further includes transistor arrangement, each storage unit is usually wrapped
Include capacitor and transistor；The grid of the transistor is connected with wordline, the drain electrode of the transistor is connected with bit line, the crystalline substance
The source electrode of body pipe is connected with capacitor；Voltage signal in the wordline can control opening or closing for the transistor, into
And the data information of storage in the capacitor is read by the bit line, or data information is written to by electricity by the bit line
It is stored in container.
Embodiment eight
Please continue to refer to Fig. 2 to Figure 15, Figure 17 to Figure 18 and Figure 20 to Figure 21, the present embodiment also provides a kind of semiconductor and deposits
The preparation method of reservoir, the preparation method of the semiconductor memory include using such as embodiment two, example IV and embodiment
The preparation method of any integrated-circuit capacitor array structure prepares the step of integrated-circuit capacitor array structure in six
Suddenly, the preparation method of the integrated-circuit capacitor array structure please refers to embodiment two, example IV and embodiment six, herein
It is not repeated.
In conclusion the utility model provides a kind of integrated-circuit capacitor array structure and semiconductor memory, it is described
Integrated-circuit capacitor array structure includes: substrate；Lower electrode layer, it is outstanding to be located on the substrate, by the lower electrode layer
Inside it is formed with capacitor hole；Capacitor dielectric layer conformally covers the surface of the lower electrode layer；Upper electrode layer conformally covers institute
State the surface of capacitor dielectric layer；Capacitor plate, block shape are located on the substrate and are formed on the upper electrode layer, the electricity
Hold pole plate to include the metallic filler layers being sequentially stacked from the bottom to top and conformally cover the conductive covering layer of the metallic filler layers,
The conductive covering layer is configured to the top surface layer and side surface layer of top electrode structure, for engaging at least one first interconnection structure
In in the top surface layer.Integrated-circuit capacitor array structure provided by the utility model is it is possible to prevente effectively from capacitor leaks
Electricity；Meanwhile when forming capacitor plate without depositing SiGe, and only deposited metal filled layer/conductive covering layer is as capacitor
Pole plate can guarantee low resistance；Metallic filler layers are used in integrated-circuit capacitor array structure provided by the utility model and are led
For electric coating as capacitor plate, metallic filler layers can be used as the etching barrier layer for forming connection through-hole above it, can be with
Etching formed connection through-hole during effectively avoid over etching perforate or etch it is not in place caused by connection through-hole do not beat
The generation for the problems such as opening；Meanwhile tungsten has lower resistivity compared to SiGe, the electric property needed for guaranteeing to obtain
In the case of thickness can be smaller, so as to reduce connection through-hole height, be conducive to the progress of subsequent technique.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (11)
1. a kind of integrated-circuit capacitor array structure characterized by comprising
Substrate；
Lower electrode layer, it is outstanding to be located on the substrate, by being formed with capacitor hole in the lower electrode layer；
Capacitor dielectric layer conformally covers the surface of the lower electrode layer；
Upper electrode layer conformally covers the surface of the capacitor dielectric layer；
Capacitor plate, block shape are located on the substrate and are formed on the upper electrode layer, and the capacitor plate includes under
The supreme metallic filler layers being sequentially stacked and the conductive covering layer for conformally covering the metallic filler layers, the conductive covering layer
It is configured to the top surface layer and side surface layer of top electrode structure, so that engagement at least one first interconnection structure is in the top surface layer
On.
2. integrated-circuit capacitor array structure according to claim 1, which is characterized in that further include top electrode filling
Body, between the upper electrode layer and the capacitor plate and capacitor hole is filled up in imporosity, and the capacitor plate is certainly
The top surface of the top electrode obturator extends to the periphery surface that the substrate is located at outside top electrode obturator overlay area.
3. integrated-circuit capacitor array structure according to claim 2, which is characterized in that the top electrode obturator is straight
It connects and is attached at the surface of the upper electrode layer and is also formed between the adjacent lower electrode layer, the top electrode obturator has
Top surface and side, the metallic filler layers are attached directly to the top surface and the side of the top electrode obturator.
4. integrated-circuit capacitor array structure according to claim 1, which is characterized in that the metallic filler layers filling
In the capacitor hole, to be electrically connected to the upper electrode layer and make to be in the form of imporosity is filled up in the capacitor hole.
5. integrated-circuit capacitor array structure according to claim 4, which is characterized in that the metallic filler layers are direct
It is attached at the surface of the upper electrode layer, and the metallic filler layers are also formed between the lower electrode layer.
6. integrated-circuit capacitor array structure according to claim 1, which is characterized in that the upper electrode layer imporosity
The capacitor hole is filled up, and is electrically connected to the capacitor plate.
7. integrated-circuit capacitor array structure according to claim 1, which is characterized in that further include base layer support layer,
Middle support layer and top support layer are all formed on the substrate and connect, support the lower electrode layer；The base layer support
Layer is located at the bottom periphery of the lower electrode layer, and the middle support layer is located at the intermediate position of the lower electrode layer, the top
Layer supporting layer is located at the opening periphery of the lower electrode layer.
8. integrated-circuit capacitor array structure according to claim 1, which is characterized in that further include:
Dielectric layer is formed on the substrate, and the week being covered on the upper surface, side and the substrate of the capacitor plate
Side surface；
First interconnection structure is located in the dielectric layer and on the capacitor plate, and the institute with the capacitor plate
Conductive covering layer is stated to be connected；And
Second interconnection structure in the dielectric layer and is located at outside the overlay area of the capacitor plate, second interconnection
Structure is longer than first interconnection structure.
9. integrated-circuit capacitor array structure according to claim 8, which is characterized in that if being formed on the substrate
Dry capacitance contact node and connection weld pad, the capacitance contact node are connected with the bottom of the lower electrode layer, the company
Weld pad is connect to be connected with the bottom of second interconnection structure.
10. integrated-circuit capacitor array structure according to any one of claim 1 to 9, which is characterized in that on described
Electrode layer includes the titanium nitride layer that atomic layer deposition is formed, and the metallic filler layers include tungsten layer, and the conductive covering layer includes
Tungsten nitride layer.
11. a kind of semiconductor memory, which is characterized in that the semiconductor memory includes as described in claim 1 integrated
Circuit capacitor array structure.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113394162A (en) * | 2020-03-12 | 2021-09-14 | 长鑫存储技术有限公司 | Capacitor array structure and forming method thereof |
| WO2021179926A1 (en) * | 2020-03-12 | 2021-09-16 | 长鑫存储技术有限公司 | Capacitor array structure and forming method therefor |
| US11925012B2 (en) | 2020-03-12 | 2024-03-05 | Changxin Memory Technologies, Inc. | Capacitor array structure and method for forming the same |
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