CN209070992U - Realize the digital circuit of clock cycle - Google Patents
Realize the digital circuit of clock cycle Download PDFInfo
- Publication number
- CN209070992U CN209070992U CN201822277722.8U CN201822277722U CN209070992U CN 209070992 U CN209070992 U CN 209070992U CN 201822277722 U CN201822277722 U CN 201822277722U CN 209070992 U CN209070992 U CN 209070992U
- Authority
- CN
- China
- Prior art keywords
- clock
- clock cycle
- dll
- configurable
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Logic Circuits (AREA)
- Pulse Circuits (AREA)
Abstract
The utility model discloses a kind of digital circuits for realizing the clock cycle, including register and configurable digital dll, the clock of the end the CK connection DDR controller of the register, the output end of the configurable digital dll of the end the D connection of the register;The clock of the input terminal connection DDR controller of the configurable digital dll.It to realize the calculating of a clock cycle, and realizes the clock of a quarter delay, can solve the design Transplanting Problem between different process, reduce the difficulty in design, reduce design time.
Description
Technical field
The technical field calculated the utility model relates to the clock cycle.
Background technique
In high speed DDR (Double Data Rate synchronous DRAM) interface circuit, in order to guarantee that better data are adopted
Sample, JEDEC (the leader standards body that solid state technology association is microelectronic industry) protocol requirement are to require DQS sending data
The rising edge or failing edge of (data sampling signal) need must be placed in the middle position of DQ (data-signal).Similarly, it is connecing
It is also required to need must be placed in the middle position of DQ for the rising edge of DQS or failing edge when receiving data to guarantee preferably
Sampling is received, existing technology is that the mode of analog circuit is usually used to realize a quarter clock cycle, for difference
The portability of technique just becomes poor.
Utility model content
The purpose of this utility model is to provide the digital circuits for realizing the clock cycle, come real by the way of digital circuit
The calculating of an existing clock cycle, and realize the clock of a quarter delay.
Realizing the technical solution of above-mentioned purpose is:
A kind of digital circuit for realizing the clock cycle, including register and configurable digital dll (digital loop
Locked, digital phase-locked loop),
The clock of the end the CK connection DDR controller of the register, the configurable number of the end the D connection of the register
The output end of DLL;
The clock of the input terminal connection DDR controller of the configurable digital dll.
Preferably, the series of the configurable digital dll is the period series of DDR clock cycle.
Preferably, the adjustment of the configurable digital dll series is controlled by state machine (STATE control).
The beneficial effects of the utility model are: the utility model realizes a clock cycle by the way of digital circuit
Calculating, and realize the clock of a quarter delay, can solve the design Transplanting Problem between different process, reduce design
On difficulty, reduce design time.
Detailed description of the invention
Fig. 1 is the structure chart of the digital circuit of the utility model.
Specific embodiment
Below in conjunction with attached drawing, the utility model is described in further detail.
Referring to Fig. 1, the digital circuit of the realization clock cycle of the utility model, is based on DDR, including register 1 and can
The digital dll 2 of configuration.
The clock DDR_CLK of the end the CK connection DDR controller of register 1, the configurable number of the end the D connection of register 1
The output end of DLL 2.The clock DDR_CLK of the input terminal connection DDR controller of configurable digital dll 2.Configurable number
The adjustment of 2 series of word DLL is controlled by state machine 3.
The composition of configurable digital dll 2 is realized by the digital gate cell NAND (NAND gate) of fixed delay, level-one
Delay be two NAND delay, series be 256 grades (can be modified according to actual DDR running frequency, if guarantee
A DDR operation clock cycle may be implemented with regard to there is no problem in maximum DLL series).In the present embodiment, configurable number
The series of DLL 2 is the period series of DDR clock cycle.
By the continuous increase of configurable 2 series of digital dll, postpones the clock DDR_CLK of DDR controller, work as deposit
The rising edge at the end D is adopted at the end CK of device 1, and the series of configurable digital dll 2 is just treated as a DDR clock cycle at this time
Period series.The judgment mode that CK adopts at end the rising edge at the end D is: exporting 1 at the end Q of register 1, is continuously increased configurable
The series of digital dll 2 stops increasing the series of configurable digital dll 2, can match at this time when the end Q of register 1 exports 0
The series for the digital dll 2 set is the period series of DDR clock cycle.
Finally, realizing that the mode of a quarter clock is exactly with similarly configurable number when period frequency has been determined
DLL 2, a quarter for being set as period series can realize a quarter delay of DDR controller clock, at this time
The data and original clock of the register 1 of clock driving are formed clock source in the middle position of data, also just meet DDR control
The timing requirements of device.
Above embodiments are only for illustration of the utility model, rather than limitations of the present invention, related technical field
Technical staff can also make various transformation or modification in the case where not departing from the spirit of the utility model, therefore it is all
Equivalent technical solution also should belong to the scope of the utility model, should be limited by each claim.
Claims (3)
1. a kind of digital circuit for realizing the clock cycle, which is characterized in that including register and configurable digital dll,
The clock of the end the CK connection DDR controller of the register, the configurable digital dll of the end the D connection of the register
Output end;
The clock of the input terminal connection DDR controller of the configurable digital dll.
2. the digital circuit according to claim 1 for realizing the clock cycle, which is characterized in that the configurable number
The series of DLL is the period series of DDR clock cycle.
3. the digital circuit according to claim 2 for realizing the clock cycle, which is characterized in that the configurable number
The adjustment of DLL series is controlled by state machine.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201822277722.8U CN209070992U (en) | 2018-12-29 | 2018-12-29 | Realize the digital circuit of clock cycle |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201822277722.8U CN209070992U (en) | 2018-12-29 | 2018-12-29 | Realize the digital circuit of clock cycle |
Publications (1)
Publication Number | Publication Date |
---|---|
CN209070992U true CN209070992U (en) | 2019-07-05 |
Family
ID=67102550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201822277722.8U Active CN209070992U (en) | 2018-12-29 | 2018-12-29 | Realize the digital circuit of clock cycle |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN209070992U (en) |
-
2018
- 2018-12-29 CN CN201822277722.8U patent/CN209070992U/en active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11115179B2 (en) | Signaling system with adaptive timing calibration | |
KR100507877B1 (en) | Rdll circuit for reduction of area | |
US7342838B1 (en) | Programmable logic device with a double data rate SDRAM interface | |
CN111338426B (en) | DDR (double data Rate) read data-based fractional clock cycle synchronization system and method | |
US7542371B2 (en) | Memory controller and memory system | |
KR100668854B1 (en) | Data latch controller of a synchronous memory device | |
TWI508067B (en) | Electronic apparatus, dram controller, and dram | |
KR20200088650A (en) | Signal generation circuit synchronized with clock signal and semiconductor apparatus using the same | |
US9058898B1 (en) | Apparatus for reducing read latency by adjusting clock and read control signals timings to a memory device | |
TWI722869B (en) | Memory access interface device | |
TWI523037B (en) | Memory device | |
US11848071B2 (en) | Systems and methods involving write training to improve data valid windows | |
US11348633B2 (en) | Selectively controlling clock transmission to a data (DQ) system | |
CN109800192A (en) | Electronic equipment, fpga chip and its interface circuit | |
US7173878B2 (en) | Apparatus for driving output signals from DLL circuit | |
CN209070992U (en) | Realize the digital circuit of clock cycle | |
CN109830252A (en) | The method realized the digital circuit of clock cycle and realize a quarter clock cycle | |
TWI466114B (en) | Memory control circuit and memory control mothod | |
CN105577173B (en) | A kind of delay phase-locked loop and duty cycle circuit for rectifying for detecting final clock output | |
KR100776740B1 (en) | Data Output Apparatus and Method of Semiconductor Memory | |
CN102280129A (en) | Flash memory and readout circuit thereof | |
CN103050146A (en) | High-duty-ratio DDR2 (double data rate) digital delay chain circuit | |
CN208424339U (en) | A kind of ddr interface circuit of adjust automatically signal dutyfactor | |
CN205407781U (en) | It corrects and postpones phase -locked delay phase -locked loop circuit to realize duty cycle simultaneously | |
TW201714173A (en) | Double data rate gating method and apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP03 | Change of name, title or address |
Address after: 201200 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai Patentee after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 6th floor, building 2, Lide international, 1158 Zhangdong Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Patentee before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |
|
CP03 | Change of name, title or address |