CN209070992U

CN209070992U - Realize the digital circuit of clock cycle

Info

Publication number: CN209070992U
Application number: CN201822277722.8U
Authority: CN
Inventors: 王亮
Original assignee: BRITE SEMICONDUCTOR (SHANGHAI) Corp
Current assignee: Canxin semiconductor (Shanghai) Co.,Ltd.
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2019-07-05
Anticipated expiration: 2028-12-29

Abstract

The utility model discloses a kind of digital circuits for realizing the clock cycle, including register and configurable digital dll, the clock of the end the CK connection DDR controller of the register, the output end of the configurable digital dll of the end the D connection of the register；The clock of the input terminal connection DDR controller of the configurable digital dll.It to realize the calculating of a clock cycle, and realizes the clock of a quarter delay, can solve the design Transplanting Problem between different process, reduce the difficulty in design, reduce design time.

Description

Realize the digital circuit of clock cycle

Technical field

The technical field calculated the utility model relates to the clock cycle.

Background technique

In high speed DDR (Double Data Rate synchronous DRAM) interface circuit, in order to guarantee that better data are adopted Sample, JEDEC (the leader standards body that solid state technology association is microelectronic industry) protocol requirement are to require DQS sending data The rising edge or failing edge of (data sampling signal) need must be placed in the middle position of DQ (data-signal).Similarly, it is connecing It is also required to need must be placed in the middle position of DQ for the rising edge of DQS or failing edge when receiving data to guarantee preferably Sampling is received, existing technology is that the mode of analog circuit is usually used to realize a quarter clock cycle, for difference The portability of technique just becomes poor.

Utility model content

The purpose of this utility model is to provide the digital circuits for realizing the clock cycle, come real by the way of digital circuit The calculating of an existing clock cycle, and realize the clock of a quarter delay.

Realizing the technical solution of above-mentioned purpose is:

A kind of digital circuit for realizing the clock cycle, including register and configurable digital dll (digital loop Locked, digital phase-locked loop),

The clock of the end the CK connection DDR controller of the register, the configurable number of the end the D connection of the register The output end of DLL；

The clock of the input terminal connection DDR controller of the configurable digital dll.

Preferably, the series of the configurable digital dll is the period series of DDR clock cycle.

Preferably, the adjustment of the configurable digital dll series is controlled by state machine (STATE control).

The beneficial effects of the utility model are: the utility model realizes a clock cycle by the way of digital circuit Calculating, and realize the clock of a quarter delay, can solve the design Transplanting Problem between different process, reduce design On difficulty, reduce design time.

Detailed description of the invention

Fig. 1 is the structure chart of the digital circuit of the utility model.

Specific embodiment

Below in conjunction with attached drawing, the utility model is described in further detail.

Referring to Fig. 1, the digital circuit of the realization clock cycle of the utility model, is based on DDR, including register 1 and can The digital dll 2 of configuration.

The clock DDR_CLK of the end the CK connection DDR controller of register 1, the configurable number of the end the D connection of register 1 The output end of DLL 2.The clock DDR_CLK of the input terminal connection DDR controller of configurable digital dll 2.Configurable number The adjustment of 2 series of word DLL is controlled by state machine 3.

The composition of configurable digital dll 2 is realized by the digital gate cell NAND (NAND gate) of fixed delay, level-one Delay be two NAND delay, series be 256 grades (can be modified according to actual DDR running frequency, if guarantee A DDR operation clock cycle may be implemented with regard to there is no problem in maximum DLL series).In the present embodiment, configurable number The series of DLL 2 is the period series of DDR clock cycle.

By the continuous increase of configurable 2 series of digital dll, postpones the clock DDR_CLK of DDR controller, work as deposit The rising edge at the end D is adopted at the end CK of device 1, and the series of configurable digital dll 2 is just treated as a DDR clock cycle at this time Period series.The judgment mode that CK adopts at end the rising edge at the end D is: exporting 1 at the end Q of register 1, is continuously increased configurable The series of digital dll 2 stops increasing the series of configurable digital dll 2, can match at this time when the end Q of register 1 exports 0 The series for the digital dll 2 set is the period series of DDR clock cycle.

Finally, realizing that the mode of a quarter clock is exactly with similarly configurable number when period frequency has been determined DLL 2, a quarter for being set as period series can realize a quarter delay of DDR controller clock, at this time The data and original clock of the register 1 of clock driving are formed clock source in the middle position of data, also just meet DDR control The timing requirements of device.

Above embodiments are only for illustration of the utility model, rather than limitations of the present invention, related technical field Technical staff can also make various transformation or modification in the case where not departing from the spirit of the utility model, therefore it is all Equivalent technical solution also should belong to the scope of the utility model, should be limited by each claim.

Claims

1. a kind of digital circuit for realizing the clock cycle, which is characterized in that including register and configurable digital dll,

The clock of the end the CK connection DDR controller of the register, the configurable digital dll of the end the D connection of the register Output end；

2. the digital circuit according to claim 1 for realizing the clock cycle, which is characterized in that the configurable number The series of DLL is the period series of DDR clock cycle.

3. the digital circuit according to claim 2 for realizing the clock cycle, which is characterized in that the configurable number The adjustment of DLL series is controlled by state machine.