CN209069963U - A kind of different hardware board power-on time sequence control circuit in test macro - Google Patents
A kind of different hardware board power-on time sequence control circuit in test macro Download PDFInfo
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- CN209069963U CN209069963U CN201821741910.5U CN201821741910U CN209069963U CN 209069963 U CN209069963 U CN 209069963U CN 201821741910 U CN201821741910 U CN 201821741910U CN 209069963 U CN209069963 U CN 209069963U
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Abstract
The utility model discloses the different hardware board power-on time sequence control circuits in a kind of test macro, hardware board is inserted in the slot of test macro difference slot position, power-on time sequence control circuit is arranged in hardware board, circuit includes power on-off control circuit and delays time to control unit, the power supply on and off of power on-off control circuit control hardware board, the delay output of delays time to control unit connects the control input of the power on-off control circuit, the input of delays time to control unit is separately connected slot position number signal and hardware board type signal, slot position number signal comes from slot encoder, hardware board type signal is from the type coders being arranged in hardware board.The utility model makes each piece of board respectively be independently determined delay to power on, and without carrying out maintenance work to system software, solves that system electrification speed is slow, and if delay inaccuracy equally exist the risk problem of power supply transient error, power-up speeds are fast.
Description
Technical field
The utility model is more particularly to the different hardware board power-on time sequence control circuit in a kind of test macro.
Background technique
In hardware testing system, if hardware resource type and quantity are relatively more, when system boot operation just
Will appear a problem: system power supply powered on moment powers on if muti-piece hardware board is also turned on, and system power supply is come
It says, this is a biggish load, and moment exports a very big electric current, the limit of this electric current power-supply system if more than
Condition, power-supply system would be possible to be damaged.For this purpose, at present system runs phase by the way of soft start in PC machine
The system software answered successively powers on instruction to the transmission of all types of hardware boards by PC machine, to limit the load electricity of powered on moment
Stream is come generation the case where avoiding transient state overcurrent, but there is also following defects for which:
Firstly, for the different hardware boards in test macro, delay time after power-up is different, such as
The delay time that FOVI board needs after power-up is 100ms, and FPVI 200ms, CBit are 50ms etc., is controlled by PC machine
Hardware board, which powers on, needs PC machine and hardware system to be communicated, and identifies to hardware board type present in system, so
Instruction is powered on according to successively sending to the pre-set delay time of every piece of hardware board afterwards, which can only serially carry out,
And delay time is influenced not so accurately by PC machine and hardware system communication, therefore uses which not only system electrification
Speed is slow, and if the inaccurate risk for equally existing power supply transient error of delay；
Secondly, the corresponding testing system software that needs to rely in such a way that PC machine Control card powers on, only when with
Under conditions of family operation testing system software and system power supply power on the two conditions while meeting, the board in test macro is
It can power on.And client is when actually using test macro, it usually needs first preheating 15min or more is carried out to test macro, to protect
Hardware board in card system is in a stable state, undoubtedly makes operating process more in such a way that PC Control card powers on
It is cumbersome；
In addition, controlling this mode powered on, every hardware board for increasing a kind of new type, it is necessary to be for PC machine
Increase the control to the hardware board in system software, increases the maintenance work to system software.
Summary of the invention
The purpose of this utility model is the different hardware board power-on time sequence control circuit proposed in a kind of test macro, is led to
The delay control circuit for crossing setting solves the problems, such as muti-piece hardware board while powering on power supply transient error.The control circuit for
All hardware boards are all applicable in hardware testing system.
To achieve the goals above, the technical solution of the utility model is:
A kind of different hardware board power-on time sequence control circuit in test macro, hardware board are inserted in test macro difference
In the slot of slot position, power-on time sequence control circuit is arranged in hardware board, wherein the power-on time sequence control circuit includes electricity
Source switch control circuit and delays time to control unit, power on-off control circuit control the power supply on and off of hardware board, prolong
When control unit delay output connect the control input of the power on-off control circuit, the input difference of delays time to control unit
Link slot bit number signal and hardware board type signal, slot position number signal come from slot encoder, hardware board type letter
Number from the type coders being arranged in hardware board.
Scheme is further: the delays time to control unit is realized by FPGA circuitry, including delay time computing module
And delay circuit, delay time computing module slot position number and hardware board type signal when calculating delay based on the received
Between, and an enabling signal is sent out to power on-off control circuit after delay time is sent to delay circuit delay.
Scheme is further: the slot encoder is arranged by slot, and slot encoded signal is drawn by lead from slot
Enter onto hardware board；Or in the slot encoder setting hardware board, slot position is set when hardware board is inserted into slot
Number.
Scheme is further: the power on-off control circuit is electromagnetic switch control circuit either electronic switch control
Circuit.
Scheme is further: the electromagnetic switch control circuit be by control relay realize power switch connection with
Shutdown；The electronic switch control circuit is the connection for driving field effect transistor switch pipe to realize power switch by photoelectric isolating circuit
With shutdown.
The utility model is avoided by system software by the power-on time sequence control circuit of Control card to muti-piece hardware plate
Block the cumbersome problem of central controlled operating process, without carrying out maintenance work to system software, it is slow to solve system electrification speed,
And if delay inaccuracy equally exists the risk problem of power supply transient error.Each piece of board is respectively independently determined delay and powers on,
It avoids muti-piece board while powering on, solve the problems, such as muti-piece board while powering on power supply transient error, power-up speeds are fast；Simultaneously
It also provides board and powers on the fault detection means after there is exception.
The utility model is described in detail with reference to the accompanying drawings and examples.
Detailed description of the invention
Fig. 1 the utility model hardware board power-on time sequence control circuit block diagram representation；
Fig. 2 the utility model delays time to control unit functional block diagram schematic diagram；
Fig. 3 the utility model electromagnetic switch control circuit schematic diagram；
Fig. 4 the utility model electronic switch control circuit schematic diagram.
Specific embodiment
A kind of different hardware board power-on time sequence control circuit in test macro, is a kind of hardware board self-contr ol
Power-on time sequence control circuit, hardware board are inserted in the slot of test macro difference slot position, such as are inserted on a bottom plate and are set
In the slot for the multiple and different slot positions set, power-on time sequence control circuit is arranged in hardware board, that is to say, that each slot
In hardware board have respective power-on time sequence control circuit, powered on described in the present embodiment refer to hardware board test circuit from
Body powers on, and after in a slot of hardware board insertion test macro difference slot position, electricity is controlled to electrifying timing sequence first
Road provides control power supply, such as 3.3 volts or 5 volts of DC power supply, and the main power source of hardware board needs to pass through electrifying timing sequence
The power switch of control circuit control is connected；Wherein, as shown in Figure 1, the power-on time sequence control circuit includes power switch control
Circuit 1 and delays time to control unit 2 processed, power on-off control circuit control the on and off of the power switch 3 of hardware board, prolong
When control unit delay output connect the control input of the power on-off control circuit, the input difference of delays time to control unit
Link slot bit number signal and hardware board type signal, such as FOVI board, FPVI board and CBit board signal, slot position
Number signal comes from slot encoder 4, and hardware board type signal is from the board type coders being arranged in hardware board
5.Also, the slot encoder, which can be, to be arranged by slot, and slot encoded signal introduces hardware from slot by lead
On board；Or the slot encoder is also possible to be arranged in hardware board, sets slot position when hardware board is inserted into slot
Number.
Wherein: the delays time to control unit is can be completed by microprocessor, and the present embodiment is by FPGA circuitry reality
Existing, FPGA(Field-Programmable Gate Array field programmable gate array) circuit includes that delay time calculates
Module 201 and delay circuit 202, slot position number and hardware board type signal calculate delay time computing module based on the received
Delay time out, and send out an enabling signal 203 to power switch after delay time is sent to delay circuit delay and control electricity
Road.
In embodiment: the power on-off control circuit is electromagnetic switch control circuit either electronic switch control electricity
Road.
Wherein: the electromagnetic switch control circuit is the on and off that power switch is realized by control relay, such as
Shown in Fig. 3, circuit includes electromagnetic relay 101, and the contact of electromagnetic relay 101 is power switch 3, and the both ends of contact connect respectively
110 volts of power supplys and board circuit are connect, the electromagnetic wire packet of electromagnetic relay connects the drain electrode output of a field effect transistor switch pipe 102,
The enabling signal 203 that the control grid connection delays time to control unit 2 of field effect transistor switch pipe 102 exports, when delay circuit delay is arrived
When, the enabling signal driving field effect transistor switch pipe 102 of submitting is connected, and the contact of electromagnetic relay 101 is attracted, power switch connects
It is logical.
Wherein: the electronic switch control circuit is that field effect transistor switch pipe is driven to realize that power supply is opened by photoelectric isolating circuit
The on and off of pass, as shown in figure 4, circuit includes concatenated photoelectrical coupler 103, concatenated photoelectric coupling, 103 shine
Diode cathode is separately connected DC power supply VCC by resistance R1 and R2, and it is defeated that light emitting diode cathode connects delays time to control unit 2
Enabling signal 203 out, 103 coupling diode of photoelectrical coupler connect a RC circuit, and RC circuit includes being connected to series connection coupling
The resistance R3 at diode both ends is closed, resistance R3 is connected in parallel the series circuit of a capacitor C and resistance R4, two concatenated field effects
(source electrode of a field-effect tube connects the drain electrode of another field-effect tube) should be managed and form the power switch 3, capacitor C and
The control grid of series connection point two concatenated field-effect tube of connection of resistance R4, capacitor C are connected with the tie point of resistance R3
The series connection point of two concatenated field-effect tube.After delay circuit delay, which reaches, powers on required delay time, it can be held
The light emitting diode for closing the photoelectrical coupler 103 of control circuit sends low level control signal (enabling signal), light photoelectric coupling
Device MOS drive circuit forms a voltage drive signals, the RC net that voltage drive signals are formed by R4 and C at the both ends resistance R3
Network, driving metal-oxide-semiconductor field effect transistor switch, connects 110V power supply for board.The RC network of R4 and C composition plays that power supply electrifying is soft to be opened
Dynamic effect.
Be according to the specific different hardware board power-on time sequence control method of above system: setting one is according to different hardware
The preferential time-delay table that board type is formulated, the slot position number and board type signal of slot where obtaining hardware board, utilizes
Calculation formula N × △ t+Pt, which is calculated, determines the different hardware board delayed time,
Wherein:
N is slot position number；
△ t is delay time as defined in hardware board itself；
Pt is the delay of board priority, is the delay data obtained from preferential time-delay table according to board type signal；
Different hardware board is powered on according to respectively determining delayed time delays.
When muti-piece hardware board powers on simultaneously, FPGA can be according to the slot number locating for board come the certain time that is successively delayed
The power supply for connecting each board later completes powering on for the board.After a period of time, all boards are all sequentially completed
It powers on, avoids transient state overcurrent.
As described in embodiment 1: the delays time to control unit is to be realized by FPGA circuitry, including delay time calculates mould
Block and delay circuit, delay time computing module slot position number and hardware board type signal when calculating delay based on the received
Between, and an enabling signal is sent out to power on-off control circuit after delay time is sent to delay circuit delay.
Wherein: the slot encoder is arranged by slot, and slot encoded signal introduces hardware from slot by lead
On board；Or in the slot encoder setting hardware board, the setting slot bit number when hardware board is inserted into slot is used
Such structure can be arranged identical according to the priority of board.
In the above method: by hardware board, locating position number determines board slot position number N in systems；For different type
Hardware board, veneer delay t be also not quite similar；Board priority delay Pt determined by the type of board, each type
Hardware board all corresponds to the priority powered on, and the high board of priority is first powered on, the more low then priority of the numerical value of Pt
Higher, using in slot encoder setting hardware board, this feature of setting slot bit number when hardware board is inserted into slot can
It same groove bit number is arranged according to the priority of same board, and then power on the board of equal priority can simultaneously,
Such as power board FOVI is identical with the priority of non-power board CBit, can be powered on simultaneously.
The method further includes upper electrosemaphore is arranged in hardware board, upper electrosemaphore is set after board normally powers on
" 0 ", while indicator light is powered on board panel as green；When exception, which occurs, in board to fail normally to power on, upper electrosemaphore is set
" 1 ", while indicator light is powered on board panel as red.
That is: when veneer normally powers on, can be arranged automatically in the register inside board and power on effective marker position
0, while indicator light is powered on board panel as green；It, can be in register when exception, which occurs, in veneer to fail normally to power on
In automatically setting power on invalid flag position 1, while on board panel power on indicator light for red.In addition, the self-test to board
Process also can readback board storage inside power-up state register value, in self-detection result prompt user's board power on appearance
Failure, to carry out troubleshooting to board in time.
Claims (5)
1. the different hardware board power-on time sequence control circuit in a kind of test macro, hardware board are inserted in test macro different slots
In the slot of position, power-on time sequence control circuit is arranged in hardware board, which is characterized in that the power-on time sequence control circuit packet
Power on-off control circuit and delays time to control unit are included, the power supply that power on-off control circuit controls hardware board is connected and closed
Disconnected, the delay output of delays time to control unit connects the control input of the power on-off control circuit, delays time to control unit it is defeated
Enter to be separately connected slot position number signal and hardware board type signal, slot position number signal comes from slot encoder, hardware board
Type signal is from the type coders being arranged in hardware board.
2. power-on time sequence control circuit according to claim 1, which is characterized in that the delays time to control unit is by FPGA
What circuit was realized, including delay time computing module and delay circuit, delay time computing module based on the received number by slot position
Delay time is calculated with hardware board type signal, and sends out a starting letter after delay time is sent to delay circuit delay
Number to power on-off control circuit.
3. power-on time sequence control circuit according to claim 1, which is characterized in that the slot encoder is arranged in slot
Side, slot encoded signal are introduced into hardware board by lead from slot；Or hardware board is arranged in the slot encoder
On, the setting slot bit number when hardware board is inserted into slot.
4. power-on time sequence control circuit according to claim 1, which is characterized in that the power on-off control circuit is electricity
Magnetic switch control circuit either electronic switch control circuit.
5. power-on time sequence control circuit according to claim 4, which is characterized in that the electromagnetic switch control circuit is logical
Cross the on and off that control relay realizes power switch；The electronic switch control circuit is driven by photoelectric isolating circuit
Dynamic field effect transistor switch pipe realizes the on and off of power switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821741910.5U CN209069963U (en) | 2018-10-26 | 2018-10-26 | A kind of different hardware board power-on time sequence control circuit in test macro |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821741910.5U CN209069963U (en) | 2018-10-26 | 2018-10-26 | A kind of different hardware board power-on time sequence control circuit in test macro |
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| CN209069963U true CN209069963U (en) | 2019-07-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109188030A (en) * | 2018-10-26 | 2019-01-11 | 北京华峰测控技术股份有限公司 | Different hardware board power-on time sequence control circuit and method in a kind of test macro |
| CN112373022A (en) * | 2020-11-30 | 2021-02-19 | 深圳市创想三维科技有限公司 | Starting protection circuit with self-checking function and 3D printer |
| CN114995262A (en) * | 2022-08-05 | 2022-09-02 | 成都万创科技股份有限公司 | Power supply time sequence control method and system of X86 platform |
-
2018
- 2018-10-26 CN CN201821741910.5U patent/CN209069963U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109188030A (en) * | 2018-10-26 | 2019-01-11 | 北京华峰测控技术股份有限公司 | Different hardware board power-on time sequence control circuit and method in a kind of test macro |
| CN112373022A (en) * | 2020-11-30 | 2021-02-19 | 深圳市创想三维科技有限公司 | Starting protection circuit with self-checking function and 3D printer |
| CN112373022B (en) * | 2020-11-30 | 2022-06-14 | 深圳市创想三维科技股份有限公司 | Starting protection circuit with self-checking function and 3D printer |
| CN114995262A (en) * | 2022-08-05 | 2022-09-02 | 成都万创科技股份有限公司 | Power supply time sequence control method and system of X86 platform |
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