CN209029381U

CN209029381U - Semiconductor device structure

Info

Publication number: CN209029381U
Application number: CN201821453972.6U
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-06
Filing date: 2018-09-06
Publication date: 2019-06-25
Anticipated expiration: 2028-09-06

Abstract

The utility model provides a kind of semiconductor device structure, it include: semiconductor substrate, inside it is formed with several active areas and isolation structure, each active area includes the first contact zone and the second contact zone, and several gate trench structures are formed in active area bottom, to separate the first contact zone and the second contact zone, gate trench structures include ditch groove body and the micro- ditch structure for being connected to lower section, and the depth of gate trench structures is less than the depth of isolation structure；And buried gate word line structure, it is filled in gate trench structures, buried gate wordline includes the gate dielectric layer for being formed in gate trench structures inner surface, and is filled in gate electrode layer in gate trench structures.The utility model is differently formed special micro- ditch structure by the etching selection ratio between different materials, simplify preparation process, improve preparation precision, on the basis of keeping original device size, channel area is set to be increased, the width that transmission channel can be further increased improves the device performance of field effect transistor.

Description

Semiconductor device structure

Technical field

The utility model belongs to ic manufacturing technology field, more particularly to a kind of semiconductor device structure.

Background technique

With the evolution of manufacture of semiconductor, feature sizes of semiconductor devices it is continuous miniature, for field effect transistor, by In short-channel effect, subthreshold current is big and grid leak is electric the problems such as so that transistor has been difficult to meet the needs of to device performance. More and more focus focus on fin formula field effect transistor (Fin FET) now.

Transistor is used for many different types of integrated circuits, common are: logical device, memory device and simulation electricity Road, wherein memory device accounts for sizable ratio in IC products, and memory basic structure is that a transistor adds One capacitance structure, used transistor are embedded structure to increase channel length.

However, further reducing with device size, the device performance of existing memory transistor is difficult to meet higher Requirement, need to be optimized transistor arrangement, to further increase device performance, especially solution short-channel effect, Asia The driving voltage of memory transistor and conducting electric current decline etc. in the caused memory of the problems such as threshold current is big and grid leak is electric Problem.

Therefore, a kind of semiconductor device structure how is provided to be necessary to solve the above problem in the prior art.

Utility model content

In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of junction of semiconductor device Structure, for solving the problems such as transistor performance in the prior art is difficult to meet demand and driving voltage, conducting electric current decline.

In order to achieve the above objects and other related objects, the utility model also provides a kind of semiconductor device structure, comprising:

Semiconductor substrate is formed with the isolation junction of several active areas and the isolation active area in the semiconductor substrate Structure, each active area includes the first contact zone and the second contact zone, and several grid ditches are formed in the active area bottom Slot structure, to separate first contact zone and second contact zone, the gate trench structures include ditch groove body and connection Micro- ditch structure below the ditch groove body, and the depth of the gate trench structures is less than the depth of the isolation structure；With And

Buried gate wordline is filled in the gate trench structures, and the buried gate wordline includes being formed in institute The gate dielectric layer of gate trench structures inner surface is stated, and is filled in gate electrode layer in the gate trench structures.

As a kind of optinal plan of the utility model, the semiconductor device structure further includes insulating layer, is located at described The surface of gate dielectric layer and the upper surface for being located at the gate electrode layer, the insulating layer and the gate electrode layer fill the full grid Groove structure.

As a kind of optinal plan of the utility model, the maximum height of micro- ditch structure is greater than the gate dielectric layer Thickness.

As a kind of optinal plan of the utility model, several wire casing structures are also formed in the isolation structure, The wire casing structure is connected with the gate trench structures along predetermined column direction, constitutes wordline groove structure, the wordline ditch The active area and the isolation structure of the slot structure on the predetermined column direction.

As a kind of optinal plan of the utility model, the depth of the wire casing structure is greater than the gate trench structures Depth capacity, the depth of the wire casing structure are less than the depth of the isolation structure.

As a kind of optinal plan of the utility model, micro- ditch structure includes the center Wei Gou and is located in micro- ditch Several micro- ditch units of heart periphery, and it is described on the extending direction of the extending direction of the active area and the wordline groove The arrangement of micro- ditch unit be generally in just as.

As a kind of optinal plan of the utility model, the cross sectional shape of micro- ditch structure is selected from arc-shaped, V-arrangement, U Any one in shape, rectangle and irregular shape.

As a kind of optinal plan of the utility model, the maximum height of micro- ditch structure is between the ditch groove body Between the 5%-30% of height.

As described above, the semiconductor device structure and preparation method thereof of the utility model, has the advantages that

The utility model provides a kind of semiconductor device structure, passes through the not similar shape of the etching selection ratio between different materials At special micro- ditch structure, simplify preparation process, and improves preparation precision, thus on the basis of keeping original device size, The problems such as making channel area be increased, the width of transmission channel can be further increased, improve the short-channel effect of device architecture, Improve the driving voltage of short-channel effect, memory transistor in the problems such as subthreshold current is big and grid leak is electric caused memory The problem of with conducting electric current decline, greatly improve the device performance of field effect transistor.

Detailed description of the invention

Fig. 1 is shown as the process flow chart of the semiconductor device structure preparation of the utility model.

Fig. 2-4 is shown as providing the structural schematic diagram of semiconductor substrate in the preparation of the utility model semiconductor device structure, Fig. 2 is shown as top view, and Fig. 3 is shown as the sectional view in the direction A-A ' in Fig. 2, and Fig. 4 is shown as the section in the direction B-B ' in Fig. 2 Figure.

Fig. 5-7 is shown as forming the structural schematic diagram of gate trench structures in the preparation of the utility model semiconductor device structure, Fig. 5 is shown as top view, and Fig. 6 is shown as the sectional view in the direction A-A ' in Fig. 5, and Fig. 7 is shown as the section in the direction B-B ' in Fig. 5 Figure.

Fig. 8-10 is shown as forming the structural schematic diagram of etching mask layer in the utility model embodiment one, and Fig. 8 is shown as Top view, Fig. 9 are shown as the sectional view in the direction A-A ' in Fig. 8, and Figure 10 is shown as the sectional view in the direction B-B ' in Fig. 8.

Figure 11-13 is shown as a kind of structural schematic diagram for forming the first, second dielectric layer of embodiment in the utility model, Figure 11 is shown as top view, and Figure 12 is shown as the sectional view in the direction A-A ' in Figure 11, and Figure 13 is shown as the direction B-B ' in Figure 11 Sectional view.

Figure 14-16 is shown as removing the structural schematic diagram of excess dielectric layer, Tu14Xian in the utility model embodiment one It is shown as top view, Figure 15 is shown as the sectional view in the direction A-A ' in Figure 14, and Figure 16 is shown as the sectional view in the direction B-B ' in Figure 14.

Figure 17-19 is shown as the utility model embodiment one and etches the structural schematic diagram for forming gate trench structures, Tu17Xian It is shown as top view, Figure 18 is shown as the sectional view in the direction A-A ' in Figure 17, and Figure 19 is shown as the sectional view in the direction B-B ' in Figure 17.

Figure 20-22 is shown as forming the structural schematic diagram of hard mask layer in the utility model embodiment two, and Figure 20 is shown as Top view, Figure 21 are shown as the sectional view in the direction A-A ' in Figure 20, and Figure 22 is shown as the sectional view in the direction B-B ' in Figure 20.

Figure 23-25 is shown as forming the structural schematic diagram of the first groove in the utility model embodiment two, and Figure 23 is shown as Top view, Figure 24 are shown as the sectional view in the direction A-A ' in Figure 23, and Figure 25 is shown as the sectional view in the direction B-B ' in Figure 23.

Figure 26-28 is shown as forming the structural schematic diagram of injected media layer in the utility model embodiment two, and Figure 26 is shown For top view, Figure 27 is shown as the sectional view in the direction A-A ' in Figure 26, and Figure 28 is shown as the sectional view in the direction B-B ' in Figure 26.

Figure 29-31 is shown as carrying out the structural schematic diagram of the first ion implanting, Tu29Xian in the utility model embodiment two It is shown as top view, Figure 30 is shown as the sectional view in the direction A-A ' in Figure 29, and Figure 31 is shown as the sectional view in the direction B-B ' in Figure 29.

Figure 32-34 is shown as carrying out the structural schematic diagram of the second ion implanting, Tu32Xian in the utility model embodiment two It is shown as top view, Figure 33 is shown as the sectional view in the direction A-A ' in Figure 32, and Figure 34 is shown as the sectional view in the direction B-B ' in Figure 32.

Figure 35-37 is shown as forming the structural schematic diagram of oxidation injected media layer, Figure 35 in the utility model embodiment two It is shown as top view, Figure 36 is shown as the sectional view in the direction A-A ' in Figure 35, and Figure 37 is shown as the section in the direction B-B ' in Figure 35 Figure.

Figure 38-40 is shown as forming the structural schematic diagram of gate trench structures in the utility model embodiment two, and Figure 38 is shown For top view, Figure 39 is shown as the sectional view in the direction A-A ' in Figure 38, and Figure 40 is shown as the sectional view in the direction B-B ' in Figure 38.

Figure 41-43 is shown as forming the structural schematic diagram of hard mask layer in the utility model embodiment three, and Figure 41 is shown as Top view, Figure 42 are shown as the sectional view in the direction A-A ' in Figure 41, and Figure 43 is shown as the sectional view in the direction B-B ' in Figure 41.

Figure 44-46 is shown as forming the structural schematic diagram of over etching groove in the utility model embodiment three, and Figure 44 is shown For top view, Figure 45 is shown as the sectional view in the direction A-A ' in Figure 44, and Figure 46 is shown as the sectional view in the direction B-B ' in Figure 44.

Figure 47-49 is shown as forming the structural schematic diagram of etch media layer in the utility model embodiment three, and Figure 47 is shown For top view, Figure 48 is shown as the sectional view in the direction A-A ' in Figure 47, and Figure 49 is shown as the sectional view in the direction B-B ' in Figure 47.

Figure 50-52 is shown as returning the structural schematic diagram for carving etch media layer in the utility model embodiment three, and Figure 50 is shown For top view, Figure 51 is shown as the sectional view in the direction A-A ' in Figure 50, and Figure 52 is shown as the sectional view in the direction B-B ' in Figure 50.

Figure 53-55 is shown as forming the structural schematic diagram of compensating material layer in the utility model embodiment three, and Figure 53 is shown For top view, Figure 54 is shown as the sectional view in the direction A-A ' in Figure 53, and Figure 55 is shown as the sectional view in the direction B-B ' in Figure 53.

Figure 56-58 is shown as forming the structural schematic diagram of etched sidewall layer and filling part in the utility model embodiment three, Figure 56 is shown as top view, and Figure 57 is shown as the sectional view in the direction A-A ' in Figure 56, and Figure 58 is shown as the direction B-B ' in Figure 56 Sectional view.

Figure 59-61 is shown as forming the structural schematic diagram of gate trench structures in the utility model embodiment three, and Figure 59 is shown For top view, Figure 60 is shown as the sectional view in the direction A-A ' in Figure 59, and Figure 61 is shown as the sectional view in the direction B-B ' in Figure 59.

Figure 62-64 is shown as forming the structural schematic diagram of wordline groove and grid structure, figure in the utility model embodiment three 62 are shown as top view, and Figure 63 is shown as the sectional view in the direction A-A ' in Figure 62, and Figure 64 is shown as section in the direction B-B ' in Figure 62 Face figure.

Component label instructions

100	Semiconductor substrate	204	First groove
				101	Active area	205	Injected media layer
101a	First contact zone	206	Structure sheaf after the injection of injected media layer
				101b	Second contact zone	206a	First injection region
102	Isolation structure	206b	Second injection region
				103	Gate trench structures	206c	Unimplanted area
103a	Ditch groove body	207	Aoxidize injected media layer
				103b	Micro- ditch structure	208	Hard mask layer etches rest layers
104	Hard mask layer	301	Hard mask layer
				105	Photoresist layer	301a	Over etching window
106	Gate groove window	302	Photoresist layer
				107	First dielectric layer	303	Over etching groove
108	Second dielectric layer	304	Etch media layer
				109	Etch body portion	305	Etch media layer rest layers
110	Etch auxiliary layer	306	Fill compensating material layer
				110a	Etch side	307	Etched sidewall layer
110b	Etching bottom	308	Filling part
				111	Hard mask layer etches rest layers	400	Wire casing structure
112	Etching mask layer	401	Gate dielectric layer
				201	Hard mask layer	402	Gate electrode layer
202	Photoresist layer	403	Insulating layer
				203	Etching window	S1~S3	Step 1) is to step 3)

Specific embodiment

Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer With carrying out various modifications or alterations under the spirit without departing from the utility model.

Fig. 1 is please referred to Figure 64.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind Become, and its assembly layout form may also be increasingly complex.

As shown in Figure 1, a kind of preparation method of semiconductor device structure of the utility model, the preparation method includes as follows Step:

1) semi-conductive substrate is provided, and is formed with several active areas in the semiconductor substrate and is isolated described active The isolation structure in area, each active area include the first contact zone and the second contact zone；

2) based on etching selection ratio different between different materials in forming several gate trench structures in the active area, To separate first contact zone and second contact zone, wherein the gate trench structures include ditch groove body and are connected to Micro- ditch structure below the ditch groove body, and the depth capacity of the gate trench structures is less than the depth of the isolation structure； And

3) inner surface of Yu Suoshu gate trench structures forms gate dielectric layer, and in filling gate electrode in the gate trench structures Layer, to form buried gate word line structure.

The preparation process of the semiconductor device structure of the utility model is described in detail below in conjunction with attached drawing.

Firstly, carrying out step 1) shown in S1 and Fig. 2-4 as shown in figure 1, providing semi-conductive substrate 100, partly led described The isolation structure 102 of several active areas 101 and the isolation active area 101, each active area are formed in body substrate 100 101 include the first contact zone 101a and the second contact zone 101b.

Specifically, offer semi-conductive substrate 100, the semiconductor substrate 100 can be silicon lining first in the step Bottom, silicon-on-insulator substrate and germanium substrate etc. are selected according to actual demand.In addition, also being formed in the semiconductor substrate 100 There are the active area 101 and isolation structure 102, wherein the isolation structure 102 can be fleet plough groove isolation structure (STI), Material used in usual fleet plough groove isolation structure is silica, and but not limited to this, in one example, the depth of the isolation structure Degree is between 350nm-450nm, and width is between 20nm-25nm；In addition, source electrode can be set in semiconductor active region 101 And drain electrode, about the structure of the parts such as the source electrode of memory buried transistor device, drain electrode, drift region, material, production work Skill, principle have been that those skilled in the art are known, and and therefore not to repeat here, source electrode, drain electrode in the utility model device architecture, Drift region etc. part can use any suitable structure, material and manufacture craft, the utility model to this with no restriction.This Outside, the formation process of the active area 101 and the isolation structure 102 can be using works such as existing ion implanting and etchings Skill is not particularly limited.In one example, described active as shown in Fig. 2, being shown as the top view of the semiconductor substrate 100 The shape in area 101 includes strip, and there are two the second contact zone 101b and one described first to connect for the tool of active area 101 Area 101a is touched, the first contact zone 101a is located at centre, and for carrying out bit line connection, two the second contact zone 101b divide Not Wei Yu two sides, for carrying out capacitance connection, the example arrangement in, every a line (such as the direction A-A ') include several as described in have Source region 101, the isolation structure are located at 101 periphery of active area.In addition, Fig. 3 is shown as the section in the direction A-A ' in Fig. 2 Figure, Fig. 4 are shown as the sectional view in the direction B-B ' in Fig. 2.

Then, shown in S2 and Fig. 5-7 as shown in figure 1, step 2) is carried out, based on etching selection different between different materials Than in forming several gate trench structures 103 in the active area 101, to separate the first contact zone 101a and described second Contact zone 101b, wherein the gate trench structures 103 include ditch groove body 103a and are connected to below the ditch groove body 103a Micro- ditch structure 103b, and the depth capacity of the gate trench structures 103 be less than the isolation structure 102 depth.

The gate groove that filling forms grid structure is subsequently used for specifically, being formed in this step, in Yu Suoshu active area 101 Structure 103, in the utility model, different based on the etching selection ratio between different materials, etching forms the gate trench structures 103, including ditch groove body 103a and micro- ditch structure 103b, so as to which the gate groove knot is prepared by simple technique Structure 103, further, micro- ditch structure 103b are further deep into the semiconductor substrate relative to the ditch groove body Portion can increase the channel area of transistor, increase the channel of electron-transport, and the short-channel effect etc. for improving device architecture is asked Topic improves the driving of short-channel effect, memory transistor in the problems such as subthreshold current is big and grid leak is electric caused memory The problem of voltage and conducting electric current decline, improves the performance of semiconductor device structure, wherein with the evolution of DRAM processing procedure, bury The channel length for entering formula grid can be corresponding shorter and shorter, and short channel can be easier to leak electricity, and has voltage to be added or have in very little When very little electric current passes through, transistor is turned on, and grid is caused not have on-off action.

Specifically, for the shape of micro- ditch structure 103b, cross sectional shape can be arc-shaped, V-arrangement, U-shaped, rectangular At least one of shape and irregular shape can increase the channel area of transistor, in addition, the bottom of micro- ditch structure 103b Shape, layout can be improved according to concrete technology.In one example, the depth capacity of the gate trench structures 103 between Between 180nm-200nm, the width of the gate trench structures is between 18nm-23nm；The depth of the isolation structure between Between 350nm-450nm, the width of the isolation structure is between 20nm-25nm, wherein signified in the utility model " between ... between " refer to the numberical range including endpoint value, in addition, signified " depth " refers to from the semiconductor substrate table Refer to towards the size extended in semiconductor substrate, such as depth of gate trench structures from semiconductor substrate surface to semiconductor substrate The size of the gate trench structures bottom is inside extended to, signified " width " refers to where a certain semiconductor substrate surface Plane in a direction size, such as width on the direction that the active area extends, in this example, gate trench structures Width refer to the width of the gate trench structures on 101 extending direction of active area.

Finally, carrying out step 3), the inner surface of Yu Suoshu gate trench structures 103 shown in S3 and Figure 61-63 as shown in figure 1 Gate dielectric layer 401 is formed, and in filling gate electrode layer 402 in the gate trench structures, to form buried gate word line structure.

Specifically, be filled in the gate trench structures of formation in the step, to form grid structure, formation The material layer of grid structure is filled in the ditch groove body 103a and micro- ditch structure 103b of the groove structure simultaneously, the embedment of formation The channel area of formula grid word line structure is increased, to further increase the width of transmission channel, improves device junction The problems such as short-channel effect of structure, improves the caused memory of the problems such as short-channel effect, subthreshold current are big and grid leak is electric In memory transistor driving voltage and conducting electric current decline the problem of, greatly improve the device performance of field effect transistor.

In one example, between step 2) and step 3), further comprise the steps of: between the active area 101 described in every From formation wire casing structure 400 in structure 102, wherein the wire casing structure 400 is with the gate trench structures 103 along predetermined Column direction is connected, and constitutes wordline groove structure, and the wordline groove structure is described active on the predetermined column direction Area 101 and the isolation structure 102, the predetermined column direction intersect with the extending direction of the active area.

Specifically, further including forming conductor trench 400 after forming the gate trench structures 103 in one example Step, and the two is interconnected to constitute the wordline groove, wherein the side predetermined column direction B-B ' as shown in Figure 61 To the active area 101 and the isolation structure 102 through interval, that is to say, that in this example, by two-step process system Standby wordline groove structure, i.e., the gate trench structures 103 being first formed simultaneously in each active area 101, then be formed simultaneously it is described every From the conductor trench structure 400 in structure 102, it is based on above-mentioned generation type, is on the one hand conducive to a certain groove structure (grid ditch Slot structure, wire casing structure) technology controlling and process on the other hand can contribute in the auxiliary for retaining complete isolation structure 102 In the case where define micro- ditch structure divisions of the gate trench structures 103 along the shape on the predetermined column direction, from And be conducive to carry out the layout setting of the shape of micro- ditch structure, be conducive to based on micro- ditch structural improvement device performance.

In addition, the gate dielectric layer 401 is formed simultaneously in the word during forming the buried gate wordline The inner surface of line trenches, the gate electrode layer 402 is filled in the entire wordline groove, i.e., in the described conductor trench 400 Filling simultaneously and identical material layer in the gate trench structures 103, to form conductor structure in the conductor trench structure, Wherein, the conductor structure and buried gate word line structure are the integral structure being formed simultaneously.It is described in an optional example For the thickness of gate dielectric layer 401 between 1-3nm, material includes silica, and the height of the gate electrode layer 402 is between 120- Between 150nm, for the width of the gate electrode layer between 14-18nm, material includes tungsten.As an example, in the grid One layer of work-function layer is also formed between dielectric layer 401 and gate electrode layer 402, such as titanium nitride (TiN) layer.

As an example, micro- ditch structure 103b include the center Wei Gou and positioned at micro- ditch central periphery several are micro- Ditch unit, and the arrangement of micro- ditch unit is general on the extending direction of the extending direction of the active area and the wordline groove In just as.

Specifically, in one example, micro- ditch structure 103b is made of two-part structure, i.e., the described center Wei Gou and institute State micro- ditch unit, wherein the shape of the center Wei Gou and micro- ditch unit is obtained according to actual demand, in an optional example In, micro- ditch unit is arranged in the periphery at the center Wei Gou, and makes micro- ditch unit in active area extending direction (such as A-A ' Direction) it is identical as the arrangement of wordline groove extending direction (such as direction B-B '), thus be conducive to the maximization of device performance promotion, And further such that the homogeneity of device architecture is improved, the stability of device performance is improved.

As an example, the depth of the wire casing structure 400 is greater than the depth capacity of the gate trench structures 103, it is described The depth of wire casing structure 400 is less than the depth of the isolation structure 102.

Specifically, in one example, the depth of the conductor trench structure 400 of preparation and the gate trench structures 103 Depth, i.e., the described wordline groove is different from the depth in the active area 101 in the isolation structure 102, optional one In embodiment, the depth of the wire casing structure 400 be greater than the depth capacity of the gate trench structures 103 and be less than it is described every Depth from structure 102, to be conducive to increase the knot of the grid structure and conductor structure of subsequent filling in the wordline groove Structure intensity.

As an example, further comprised the steps of: after step 3) in filling insulating layer 403 in the gate trench structures 103, In, the insulating layer 403 is formed in the surface of the gate dielectric layer 401 and is located at the upper surface of the gate electrode layer 402, described Insulating layer 403 and the gate electrode layer 402 fill the full gate trench structures 103.

As an example, the maximum height of micro- ditch structure 103b is greater than the thickness of the gate dielectric layer 401, and described micro- The maximum height of ditch structure 103b is less than the thickness of the insulating layer 403.

Specifically, further including filling an insulating layer 403, the insulation in the gate trench structures 103 in one example For the height of layer 403 between 50-60nm, width, can be using insulation materials such as silicon oxide or silicon nitrides between 14-18nm Material, when being formed with the wire casing structure composition wordline groove, the insulating layer 403 is formed simultaneously in the conducting wire ditch In slot structure, as shown in Figure 62.Further, in an optional example, the height of micro- ditch structure 103b is controlled greater than described The thickness of gate dielectric layer 401 prevents so that can fill the gate electrode structure in micro- ditch structure in micro- ditch The gate dielectric layer 401 is filled up completely in structure 103b, so as to be conducive to the promotion of device performance.

As an example, between the 5%-30% of height of the maximum height of micro- ditch structure between the ditch groove body. Control micro- ditch structure maximum height be greater than the ditch groove body height 5%, preferably greater than 10%, to be conducive to It states micro- ditch structure and plays its effect, the maximum height of control micro- ditch structure is less than the 30% of the height of the ditch groove body, Preferably smaller than 20%, to be conducive to the formation of micro- ditch structure.

The gate trench structures 103 of micro- ditch structure 103b, which are lifted, to be included the steps that formation in the utility model below Example explanation.

Embodiment one:

As shown in Fig. 8-19, the present embodiment provides a kind of forming method of gate trench structures 103, forming step is specific Include:

As seen in figs. 8-10, step 2-1 is carried out), etching mask layer 112, and institute are formed in Yu Suoshu semiconductor substrate 100 It states and is formed with several gate groove windows 106 on etching mask layer, the gate groove window 106 exposes the active area 101 And define the position of the gate trench structures 103；Specifically, defining the gate trench structures 103 first described active Position in area 101 is correspondingly formed on each active area 101 there are two the gate groove window 106 in one example, Between adjacent the first contact zone 101a and the second contact zone 101b.

As an example, the etching mask layer 112 includes the hard mask layer being sequentially formed in the semiconductor substrate 100 104 and photoresist layer 105, between 80nm-120nm, the thickness of the photoresist layer 105 is situated between the thickness of the hard mask layer 501 Between 80nm-120nm, with along the photoresist layer 105, etching forms the gate trench structures 103 downwards.

As figs 11-13, step 2-2 is carried out), etching auxiliary layer 110 is formed in Yu Suoshu gate groove window 106 and is carved Lose body portion 109, wherein the etching auxiliary layer 110 includes the etching bottom 110b positioned at the bottom of the gate groove window 106 And the etching side 110a positioned at 106 side wall of gate groove window, the etching body portion 109 are located at the etching bottom The surface 110b and have between the etching side 110a, and between the etching auxiliary layer 110 and the etching body portion 109 There is different etching selection ratios；

As an example, the step of forming the etching auxiliary layer 110 and etching body portion 109 includes:

2-2-1) etching of the bottom of Yu Suoshu gate groove window 106, side wall and the gate groove thereabout is covered Film surface forms the first dielectric layer 107, and forms the second dielectric layer 108, institute in 107 surface of the first dielectric layer The second dielectric layer 108 is stated to fill the full gate groove window 106 and extend over described the of the gate groove thereabout One dielectric layer 107, and selected between first dielectric layer 107 and second dielectric layer 108 with different etchings Select ratio；

2-2-3) remove first dielectric layer 107 and second dielectric layer on the etching mask layer 112 108, wherein remaining first dielectric layer 107 for being formed in 106 side wall of gate groove window constitutes the etching side Portion 110a, remaining first dielectric layer 107 for being formed in 106 bottom of gate groove window constitute the etching bottom 110b, remaining second dielectric layer 108 being filled in the gate groove window 106 constitute the etching body portion 109.

Specifically, two kinds of material layers with different etching selection ratio are formed in the step, to form institute for subsequent etching It states micro- ditch structure 103b and structure basis is provided, wherein have not between the etching auxiliary layer 110 and the etching body portion 109 Same etching selection ratio, refers to during performing etching, and the two has different etch rates to identical etching gas. In one example, the etching auxiliary layer and the etching body portion are formed by way of forming two different dielectric layers. In one example, first dielectric layer 107 includes silicon oxide layer, and between 5nm-8nm, deposition method can be thickness Chemical vapor deposition (CVD), high density plasma CVD (HDPCVD), atomic layer vapor phase deposition (ALD) etc., institute Stating the second dielectric layer 108 includes silicon nitride layer, and deposition method can be chemical vapor deposition (CVD), high-density plasma Chemical vapor deposition (HDPCVD), atomic layer vapor phase deposition (ALD) etc..

Specifically, carrying out planarization process, 112 conduct of etching mask layer to the structure for forming two layers of dielectric layer Stop-layer when the etching mask layer 112 includes the photoresist layer 105, deposits first dielectric layer in one example Still retain the photoresist layer 105 before 107, the photoresist layer 105, such as can be using change as the stop-layer planarized in the step The excess dielectric on mechanical polishing (CMP) removal etching mask is learned, the electricity finally only retained in the gate groove window 106 is situated between Matter layer, first dielectric layer including reservation, i.e. the first dielectric layer etch rest layers, constitute the etching auxiliary layer 110, it further includes being located at the quarter that it includes etching side 110a and etching bottom 110b that the first dielectric layer, which etches rest layers 110, Lose remaining second dielectric layer on the 110b of bottom, i.e., the described etching body portion 109.

As in figs. 17-19, step 2-3 is carried out), the structure that step 2-2) is obtained is performed etching, in the grid ditch The gate trench structures 103 are formed in the active area 101 of 106 corresponding position of slot window, wherein assist based on the etching Different etching selection ratios forms micro- ditch structure 103b, micro- ditch structure 103b between layer 110 and the etching body portion In micro- ditch that micro- ditch unit of formation including the correspondence etching side 110a and the corresponding etching body portion 109 are formed The heart.

Specifically, in this step, dry etching is carried out to the structure that step 2-3) is obtained, due to the etching body portion 109 have different etching selection ratios from the etching side 110b, to can finally obtain difference during etching The structure of etching depth, it can the pattern of micro- ditch structure 103b is obtained, thus in its bottom on the basis of U-shaped channel Etch micro- ditch structure, wherein etch period and the finally formed etching body portion 109 and the etching can be passed through The pattern for micro- ditch structure that ratio between the 110a of side adjusts, that is, the micro- ditch unit adjusted with it is described The size and layout at the center Wei Gou, finally, removal etching after remaining hard mask layer with obtain include micro- ditch structure gate groove Structure, for example, the hard mask layer can be removed using wet-etching technology.

As an example, step 2-2) in, the thickness of first dielectric layer 107 of formation is between the gate groove window Between the 20%-40% of 106 width.Specifically, in this example, controlling the thickness of first dielectric layer 107 of formation The relationship of degree and the width of the gate groove window 106, to form first layer dielectric and the second layer in gate groove window Dielectric, wherein the first dielectric has faster etch rate, controls its thickness to reasonably control micro- ditch structure of formation Pattern be selected as 30% in this example, so as to based on the etching body portion formed the center Wei Gou, and based on formation The micro- ditch unit for being located at micro- ditch central periphery is formed in the etching side of the etching body portion periphery.

Embodiment two:

As shown in Figure 20-39, the present embodiment provides the forming method of another gate trench structures, forming step is specific Include:

As illustrated in figs 20-22, step 2-1 is carried out), hard mask layer 201, and institute are formed in Yu Suoshu semiconductor substrate 100 It states and is formed with several etching windows 203 on hard mask layer, the etching window 203 exposes the active area 101 and defines The position of the gate trench structures 103 out；Specifically, defining the gate trench structures 103 first in the active area 101 Position be correspondingly formed on each active area 101 there are two the gate groove window 106, be located at adjacent in one example The first contact zone 101a and the second contact zone 101b between.

As an example, the hard mask layer 201 is formed based on a photoresist layer 202, to etch downwards along the photoresist layer 202 Form the gate trench structures 103, wherein the thickness of the hard mask layer 201 is between 80nm-120nm, the photoresist layer 202 thickness is between 80nm-120nm.

As shown in figs. 23-25, step 2-2 is carried out), it is corresponded to and is carved in the active area 101 based on the etching window 203 Erosion forms several the first grooves 204；Specifically, the first groove 204 is initially formed in the active area 101 in the step, The depth of first groove 204 is less than the depth capacity of the gate trench structures 103, in an optional example, described first The depth of groove is less than or equal to the depth of the ditch groove body, in addition, further including removal after forming first groove 204 The step of photoresist layer 202, first groove 204 form the gate trench structures 103 for assisting.

As shown in Figure 26-34, step 2-3 is carried out), bottom, side wall and the etched recesses of Yu Suoshu etched recesses 104 Around the hard mask layer on formed injected media layer 205, and to the injected media layer 205 carry out ion implanting, in At least one injection region and at least one unimplanted area are formed on the bottom of the etched recesses；

As an example, the mode for forming the injection region and the unimplanted area includes: along first direction to the injection Dielectric layer 205 carries out the first ion implanting, so that the side less than 204 bottom of the first groove forms the first injection region 206a carries out the second ion implanting to the injected media layer 205 in a second direction, so that it is less than 204 bottom of the first groove The opposite other side in portion forms the second injection region 206b, and the first injection region 206a and the second injection region 206b it Between be formed with unimplanted area 206c.

As an example, the acute angle formed between 100 surface of the first direction and the semiconductor substrate is between 0 ° -90 ° Between, the acute angle formed between 100 surface of the second direction and the semiconductor substrate is based on hiding between 0 ° -90 ° It covers effect and forms the unimplanted area 206c in the injection dielectric layer 205 of 204 bottom of the first groove；

Specifically, in the step, be initially formed the injected media layer 205, the thickness of the injected media layer 205 between Between 2nm-5nm, material, which can choose, then carries out ion to the injected media layer 205 of formation for polysilicon or monocrystalline silicon Injection, forms at least one injection region and at least one unimplanted area with the bottom in first groove 204, wherein passes through After the ion implanting, there is different etching selection ratios, thus in subsequent dry etching between injection region and unimplanted area In the process, different depth are etched in injection region position corresponding from the unimplanted area, wherein injection can make The etch rate in region for receiving injection becomes larger, and can also be so that the etch rate in region inject becomes smaller, in one example, infuses The ion entered specifically can be boron element, in addition, for the positional relationship of the injection region and the unimplanted area, it can foundation The shape of the micro- ditch structure needed is selected, and such as be can be the unimplanted area and is located at center, injection region is distributed in institute The periphery in unimplanted area is stated, it certainly, can also be in the bottom of first groove for the quantity of injection region and unimplanted area Two or more unimplanted areas and two or more injection regions are formed in the injected media floor.

In addition, in one example, as shown in Figure 30 and Figure 33, carrying out not Tongfang to the injected media layer 205 of formation To ion implanting, with formed ion implanting dielectric layer injection after structure sheaf 206, wherein including receive ion implanting ion Injection region, i.e., the described first injection region 206a and the second injection region 206b, preferably the two are recessed at least formed at described first The opposite two sides of the injected media layer of trench bottom, and the non-injection regions 206c for not receiving ion implanting is formed, in the example, institute It states first direction to intersect with the second direction, simultaneously described when injection is formed on the bottom of first groove 204 Ion implanting is formed in the injection dielectric layer 205 around the side wall of first groove 204 and the first groove 204, is subsequent quarter Erosion forms micro- ditch structure and provides structure basis.In an optional example, the first direction and 100 surface of semiconductor substrate Between the acute angle that is formed between 82 ° -85 °, formed between 100 surface of the second direction and the semiconductor substrate sharp Between 82 ° -85 °, the two is injected from the left and right sides respectively at angle, so that the first bottom portion of groove middle section Unimplanted area is formed based on shadowing effect, thereby may be ensured that the structure accuracy for the micro- ditch structure to be formed.

As illustrated in figs. 38-40, step 2-4 is carried out), the structure that step 2-3) is obtained is performed etching, in described first The second groove is formed in the active area of 204 corresponding position of groove, described in first groove and second groove are constituted Gate trench structures 103, and second groove includes micro- ditch structure 103b, wherein based on described in progress ion implanting What different etching selection ratios was formed between injected media layer and the injection dielectric layer for not carrying out ion implanting is described micro- Ditch structure 103b, micro- ditch structure include the corresponding injection region (such as described first injection region 206a and second injection Area 206b) center Wei Gou that is formed micro- ditch unit for being formed and the corresponding unimplanted area 206c.

Specifically, in this step, dry etching is carried out based on the obtained structure of step 2-3), due to the injection region (such as described first injection region 206a and the second injection region 206b) from the unimplanted area 206c there are different etchings to select Ratio is selected, so that the structure of different etching depth can be finally obtained during etching, it can obtain micro- ditch structure Pattern, wherein the ratio between etch period and the finally formed injection region and the unimplanted area can be passed through Adjust the pattern of obtained micro- ditch structure, that is, the size and cloth of the micro- ditch unit and the center Wei Gou that adjust Office.

As an example, the first injection region 206a and the second injection region 206b is relative to the unimplanted area 206c In symmetry arrangement, and the width of the unimplanted area 206c is between the 5%-30% of the first bottom portion of groove width, In, the width of the unimplanted area 206c is controlled, the height of micro- ditch structure can be rationally controlled, so that advantageously ensuring that institute State micro- ditch structure be conducive to be formed by techniques such as etchings while guaranteeing that certain height can increase channel length it is described Micro- ditch structure, to further reasonably control the pattern of micro- ditch structure of formation.

Specifically, providing the layout relationship of a kind of injection region and the unimplanted area, including two parts in the example The region of ion implanting and the unimplanted region among the two, the width of the unimplanted area 206c are preferably between described Between the 20%-25% of one bottom portion of groove width, so as to further increase channel area.

As shown in figs. 35-37, as an example, step 2-3) and step 2-4) between further comprise the steps of: to carry out it is described from The injected media layer 205 after son injection is aoxidized to form oxide isolation layer 207, and the oxide isolation layer 207 wraps The unimplanted oxide isolation floor for including the injection oxide isolation floor formed by the injection region and being formed by the unimplanted area, step Rapid 2-4) in etching specifically include:

First time etching 2-4-1) is carried out using the injection oxide isolation layer and the unimplanted oxide isolation layer as exposure mask, To remove the injection oxide isolation layer, and expose the hard mask layer 201；And

It 2-4-2) carries out second with the hard mask layer and the unimplanted oxide isolation layer to etch, in described first Second groove is formed in the active area of 204 corresponding position of groove.

Specifically, in the step to injected media layer injection after structure sheaf carry out oxidation form oxide isolation layer, realize from Son injection after region compared to non-ion implanting region formed oxide isolation layer have different etching rate, so as into One step improves the difference of the etching selection ratio between the injection region and the unimplanted area, improves the controllable of micro- ditch structure and morphology Property.Wherein, using the technique of twice etching, in one example, the injected media layer 205 can be monocrystalline silicon or polysilicon, The silica of injection doping and the silica of unimplanted doping are formed after then being aoxidized, and are etched removal injection by first time and are mixed Miscellaneous silica, then the silica based on unimplanted doping and original hard mask layer are that exposure mask carries out second of etching.Wherein, In one example, first time etching includes that dry etching etches, and second of etching includes dry etching, and described the The secondarily etched etching selection ratio to the unimplanted oxide isolation layer and the hard mask layer is greater than 5:1, selects in this example For 8:1.

As an example, step 2-2) in, the depth of first groove 204 is maximum deep between the gate trench structures 103 Between the 5%-30% of degree.Specifically, the depth for first groove 204 that control is initially formed, so as to be conducive to control The size relationship of micro- the ditch structure and the gate trench structures that are formed is made, the depth of first groove 204 is controlled, it can be reasonable The height for controlling micro- ditch structure allows and advantageously ensures that micro- ditch structure increases channel in the certain height of guarantee Be conducive to form micro- ditch structure by techniques such as etchings while length, to further reasonably control micro- ditch of formation The pattern of structure.In one example, the depth of first groove 204 is preferably between 20nm- between 10nm-60nm Between 40nm.

Embodiment three:

As shown in Figure 41-61, the present embodiment provides the forming method of gate trench structures described in another, forming step is specific Include:

As shown in Figure 41-43, step 2-1 is carried out), hard mask layer 301, and institute are formed in Yu Suoshu semiconductor substrate 100 It states and is formed with several over etching windows 301a on hard mask layer 301, the over etching window 301a exposes the active area 100 and define the positions of the gate trench structures 103；Specifically, define the gate trench structures 103 first has described Position in source region 101 is correspondingly formed on each active area 101 there are two the gate groove window in one example 106, between adjacent the first contact zone 101a and the second contact zone 101b.

As an example, the hard mask layer 301 is formed based on a photoresist layer 302, to etch downwards along the photoresist layer 302 Form the gate trench structures 103, wherein the thickness of the hard mask layer 301 is between 80nm-120nm, the photoresist layer 302 thickness is between 80nm-120nm.

As shown in figures 44-46, step 2-2 is carried out), it is right in the active area 101 based on the over etching window 301a It should etch to form several over etching grooves 303；

Specifically, being initially formed over etching groove 303 in the active area 101 in the step, carved forming described cross Further include the steps that removing the photoresist layer 302 after erosion groove 303, can be dry or wet etch, the over etching is recessed Slot 303 forms the gate trench structures 103 for assisting.In one example, the over etching groove is formed using dry etching 303, the depth of the over etching groove can be the 105%~130% of the depth of the ditch groove body 103a, in an example In, the depth of the over etching groove can reach required for etching between 200nm-260nm by adjusting etch period Depth.

As shown in Figure 47-52, step 2-3 is carried out), bottom, side wall and the over etching of Yu Suoshu over etching groove 303 Etch media layer 304 is formed on the hard mask layer 301 of groove vicinity, and the etch media layer 304 carve, shape Returned at etch media layer and carve layer 305, with expose the over etching groove 303 bottom and the over etching groove vicinity The hard mask layer 301；

Specifically, in this step, being formed for etching the first layer of auxiliary material for forming micro- ditch knot 103b, i.e., to institute It states etch media layer 304 and carries out the etch media layer time quarter layer 305 that Hui Kehou is obtained, the etch media layer, which returns, carves 305, layer In on the inner sidewall of the over etching groove 303.The thickness of the etch media layer 304 is between 7nm-9nm, the etching The material of dielectric layer can be silicon oxide or silicon nitride, and the method for depositing the etch media layer can use chemical vapor deposition (CVD), high density plasma CVD (HDPCVD), atomic layer deposition (ALD) etc..

As illustrated in figs. 53-55, step 2-4 is carried out), Yu Suoshu over etching groove is interior to fill compensating material layer 306, the benefit It repays material layer 306 and extends to 301 surface of hard mask layer；Specifically, filling forms micro- ditch structure for etching in the step Second of layer of auxiliary material of 103b, i.e., the described compensating material layer 306, in an optional example, the compensating material layer 306 with The material of the active area 101 is selected as identical material, to advantageously ensure that the stability of device architecture.The compensating material Layer 306 material can be polysilicon or monocrystalline silicon, the method used can for chemical vapor deposition (CVD), high density etc. from Daughter chemical vapor deposition (HDPCVD), atomic layer deposition (ALD) etc..

As shown in Figure 56-58, step 2-5 is carried out), the structure that step 2-4) is obtained is performed etching, the etching is based on Different etching selection ratios forms etching in the over etching groove 303 between dielectric layer 304 and the compensating material layer 306 Side wall layer 307 and filling part 308, wherein the etched sidewall layer 307 is located on the side wall of the over etching groove 303, described Etched sidewall 307 based on the etch media layer 304 formation, the filling part 308 be located at the bottom of the etched recesses 303 and Between the etched sidewall layer 307, the filling part 308 is based on the compensating material layer 306 formation；

Specifically, performing etching in the step to the structure for being filled with the compensating material layer 306, etched sidewall is formed Layer 307 and filling part 308, thus as the structure basis for being subsequently formed micro- ditch structure and morphology, wherein be based on the etch media Different etching selection ratios, can etch to obtain not during carrying out dry etching between layer 304 and the compensating material layer 306 Same depth, it can obtain the pattern of micro- ditch structure, wherein etch period and finally formed institute can be passed through The pattern for micro- ditch structure that the ratio between injection region and the unimplanted area adjusts is stated, that is, what is adjusted is described The size and layout of micro- ditch unit and the center Wei Gou.

As shown in Figure 59-61, step 2-6 is carried out), the etched sidewall layer 307 is removed, can such as be gone using wet etching It removes, to form the gate trench structures 103, wherein the part over etching groove 303 around the filling part 308 is constituted Micro- ditch structure 103b, micro- ditch structure 103b include the micro- ditch unit and be based on that the corresponding etched sidewall layer is formed The center Wei Gou that the filling part is formed.Specifically, after removing the etched sidewall layer 307, with the upper table of the filling part 308 Face is boundary, and the part under 308 upper surface of filling part constitutes micro- ditch structure 103b.

As an example, step 2-2) in, the maximum of the depth of the over etching groove 303 and the gate trench structures 103 Depth is generally in identical.Specifically, defining institute's gate groove to be formed while forming over etching groove 303 in the example The depth of structure 103 not only increases gate trench structures position control without being controlled in subsequent technique again Accuracy also simplifies subsequent technique, improves process efficiency.

As an example, step 2-5) in, the height of the filling part 308 of formation is controlled between the over etching groove The 5%-30% of depth；20%-40% of the width for the filling part that control is formed between the width of the over etching groove Between.

Specifically, in this step, the height and width of micro- ditch structure 103b are defined by etching technics, it is excellent Selection of land, the 15%-25% of the height of the filling part 308 between the depth of the over etching groove, the width of the filling part Between the 25%-35% of the width of the over etching groove, in one example, the height of the filling part 308 is between 10- Between 60nm.

In addition, the utility model also provides a kind of semiconductor device structure, the semiconductor device structure preferably uses this The preparation method of the semiconductor device structure of utility model is prepared, and the semiconductor device structure includes:

Semiconductor substrate 100 is formed with several active areas 101 and the isolation active area in the semiconductor substrate 101 isolation structure 102, each active area 101 includes the first contact zone 101a and the second contact zone 101b, and described is had Several gate trench structures 103 are also formed in source region bottom, to separate the first contact zone 101a and second contact zone 101b, the gate trench structures 103 include the ditch groove body 103a and micro- ditch structure 103b being connected to below the ditch groove body, And the depth of the gate trench structures 103 is less than the depth of the isolation structure 102；And

Buried gate wordline is filled in the gate trench structures 103, and the buried gate wordline includes being formed in The gate dielectric layer 401 of the gate trench structures inner surface, and it is filled in gate electrode layer 402 in the gate trench structures.

Specifically, the semiconductor substrate 100 can be silicon substrate, silicon-on-insulator substrate and germanium substrate etc., foundation Actual demand selection.In addition, the active area 101 and isolation structure 102 are also formed in the semiconductor substrate 100, In, the isolation structure 102 can be fleet plough groove isolation structure (STI), and material used in usual fleet plough groove isolation structure is oxygen SiClx, but not limited to this, and in one example, the depth of the isolation structure is between 350nm-450nm, and width is between 20nm- Between 25nm；In addition, source electrode and drain electrode can be set in semiconductor active region 101.In one example, as shown in Fig. 2, display Shape for the top view of the semiconductor substrate 100, the active area 101 includes strip, and there are two the tools of active area 101 The second contact zone 101b and the first contact zone 101a, the first contact zone 101a are located at centre, are used for Bit line connection is carried out, two the second contact zone 101b are located at two sides, for carrying out capacitance connection, arrange in the example In, every a line (such as direction A-A ') includes several described active areas 101, and the isolation structure is located at outside the active area 101 It encloses.In addition, Fig. 3 is shown as the sectional view in the direction A-A ' in Fig. 2, Fig. 4 is shown as the sectional view in the direction B-B ' in Fig. 2.

In addition, the gate trench structures 103, including ditch groove body 103a and micro- ditch structure 103b, micro- ditch structure 103b is further deep into the inside of the semiconductor substrate 100 relative to the ditch groove body 103a, can increase transistor Channel area, the problems such as increasing the channel of electron-transport, improve the short-channel effect of device architecture, improve short-channel effect, The driving voltage of memory transistor in the caused memory of the problems such as subthreshold current is big and grid leak is electric and conducting electric current decline The problem of, improve the performance of semiconductor device structure.Specifically, for the shape of micro- ditch structure 103b, cross sectional shape It can be at least one of arc-shaped, V-arrangement, U-shaped, rectangle and irregular shape, the channel area of transistor can be increased, separately Outside, the shape of the bottom of micro- ditch structure 103b, layout can be improved according to concrete technology.In one example, the grid ditch The depth capacity of slot structure 103 is between 180nm-200nm, and the width of the gate trench structures is between 18nm-23nm； The depth of the isolation structure is between 350nm-450nm, and the width of the isolation structure is between 20nm-25nm

In addition, the gate dielectric layer 401 is formed simultaneously in the word during forming the buried gate wordline The inner surface of line trenches, the gate electrode layer 402 is filled in the entire wordline groove, i.e., in the described conductor trench 400 Filling simultaneously and identical material layer in the gate trench structures 103, to form conductor structure in the conductor trench structure, Wherein, the conductor structure and buried gate word line structure are the integral structure being formed simultaneously.It is described in an optional example For the thickness of gate dielectric layer 401 between 1-3nm, material includes silica, and the height of the gate electrode layer 402 is between 120- Between 150nm, for the width of the gate electrode layer between 14-18nm, material includes tungsten.

As an example, one layer of total function layer is also formed between the gate dielectric layer 401 and gate electrode layer 402.

As an example, the semiconductor device structure further includes insulating layer 403, the insulating layer is located at the gate dielectric layer Surface and be located at the upper surface of the gate electrode layer, the insulating layer and the gate electrode layer fill the full gate groove knot Structure.

Specifically, in one example, an insulating layer 403, the insulating layer are also filled up in the gate trench structures 103 For 403 height between 50-60nm, width, can be using insulation materials such as silicon oxide or silicon nitrides between 14-18nm Material, when being formed with the wire casing structure composition wordline groove, the insulating layer 403 is formed simultaneously in the conducting wire ditch In slot structure, as shown in Figure 62.Further, in an optional example, the height of micro- ditch structure 103b is controlled greater than described The thickness of gate dielectric layer 401 prevents so that can fill the gate electrode structure in micro- ditch structure in micro- ditch The gate dielectric layer is filled up completely in structure 103b, so as to be conducive to the promotion of device performance.

As an example, being also formed with several wire casing structures 400, the wire casing structure in the isolation structure 102 400 are connected with the gate trench structures 103 along predetermined column direction, constitute wordline groove structure, and the wordline groove structure passes through Wear the active area 101 and the isolation structure 102 on the predetermined column direction.

Specifically, further including the conductor trench 400 being formed in the isolation structure, the metallic channel in one example Structure and the gate trench structures are interconnected to constitute the wordline groove, wherein the predetermined column direction such as institute in Figure 61 The direction B-B ' shown, the active area 101 and the isolation structure 102 through interval.

As an example, between the 5%-30% of height of the maximum height of micro- ditch structure between the ditch groove body.

In conclusion the utility model provides a kind of semiconductor device structure, pass through the etching selection between different materials Ratio is differently formed special micro- ditch structure, simplifies preparation process, and improves preparation precision, thus keeping original device size On the basis of, so that channel area is increased, the width of transmission channel can be further increased, greatly improve field effect transistor Device performance.So the utility model effectively overcomes various shortcoming in the prior art and has high industrial utilization value.

The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.

Claims

1. a kind of semiconductor device structure characterized by comprising

Semiconductor substrate is formed with the isolation structure of several active areas and the isolation active area in the semiconductor substrate, Each active area includes the first contact zone and the second contact zone, and several gate groove knots are formed in the active area bottom Structure, to separate first contact zone and second contact zone, the gate trench structures include ditch groove body and are connected to institute Micro- ditch structure below ditch groove body is stated, and the depth of the gate trench structures is less than the depth of the isolation structure；And

Buried gate word line structure is filled in the gate trench structures, and the buried gate wordline includes being formed in institute It states the gate dielectric layer of gate trench structures inner surface, the gate electrode layer being filled in the gate trench structures and is located at the grid and be situated between Work-function layer between matter layer and the gate electrode layer.

2. semiconductor device structure according to claim 1, which is characterized in that the semiconductor device structure further includes exhausted Edge layer, the insulating layer be located at the surface of the gate dielectric layer and be located at the gate electrode layer upper surface, the insulating layer with The gate electrode layer fills the full gate trench structures；The maximum height of micro- ditch structure is greater than the thickness of the gate dielectric layer Degree.

3. semiconductor device structure according to claim 1, which is characterized in that the maximum height of micro- ditch structure is greater than The thickness of the gate dielectric layer.

4. semiconductor device structure according to claim 1, which is characterized in that be also formed in the isolation structure several A wire casing structure, the wire casing structure are connected with the gate trench structures along predetermined column direction, constitute wordline groove knot Structure, the active area and the isolation structure of the wordline groove structure on the predetermined column direction.

5. semiconductor device structure according to claim 4, which is characterized in that the depth of the wire casing structure is greater than institute The depth capacity of gate trench structures is stated, the depth of the wire casing structure is less than the depth of the isolation structure.

6. semiconductor device structure according to claim 4, which is characterized in that micro- ditch structure include the center Wei Gou and Positioned at several micro- ditch units of micro- ditch central periphery, and along the extending direction of the active area and the wordline groove On extending direction the arrangement of micro- ditch unit be generally in just as.

7. semiconductor device structure according to claim 1, which is characterized in that the cross sectional shape of micro- ditch structure is selected from Any one in arc-shaped, V-arrangement, U-shaped and rectangle.

8. semiconductor device structure according to any one of claims 1-7, which is characterized in that micro- ditch structure Maximum height is between the 5%-30% of the height of the ditch groove body.