CN209029362U - Chip cooling structure, chip structure, circuit board and supercomputer equipment - Google Patents
Chip cooling structure, chip structure, circuit board and supercomputer equipment Download PDFInfo
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- CN209029362U CN209029362U CN201821942991.5U CN201821942991U CN209029362U CN 209029362 U CN209029362 U CN 209029362U CN 201821942991 U CN201821942991 U CN 201821942991U CN 209029362 U CN209029362 U CN 209029362U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to a kind of chip cooling structure, chip structure, circuit board and supercomputer equipment, which includes: the coating being covered on the wafer of the chip；Wherein, coating includes the first metal layer set gradually, second metal layer and third metal layer.Increase by three metal layers by way of physical sputtering at the top of chip, so as to which radiator is welded on the metal layer by solder layer, and then the top by radiator fixed to chip；The main component of solder layer is metallic tin, and the epoxy resin glue material that metal layer is mounted relative to traditional heat sinks has higher thermal coefficient, to solve the problems, such as the heat dissipation bottleneck of glue material in chip；The heat dissipation effect that chip can be promoted prevents a large amount of heat loss chip.
Description
Technical field
This application involves the field of radiating of chip more particularly to a kind of chip cooling structure, chip structure, circuit boards and super
Calculate equipment.
Background technique
In current calculating equipment, usually by heat-conducting glue pasted at the top of chip radiator in the way of come on circuit board
Chip radiate.
But the thermal coefficient of conventional thermal conductive glue is generally lower than 2 watts/ meter Du (W/ (mC)), leads to the heat dissipation of chip
The effect is unsatisfactory.
Utility model content
The application provides a kind of chip cooling structure, chip structure, circuit board and supercomputer equipment, to solve existing chip
The unsatisfactory problem of heat dissipation effect.
The embodiment of the present application provides a kind of chip cooling structure, is arranged on chip, the chip cooling structure includes:
The coating being covered on the wafer of the chip；
Wherein, the coating includes the first metal layer set gradually, second metal layer and third metal layer.
Further, the chip cooling structure further include: the radiator being connect with the coating.
Further, the first metal layer is covered on the wafer, and the second metal layer is covered on described first
On metal layer, the third metal layer is covered in the second metal layer.
Further, the chip includes the wafer and plastic package structure, and the upper surface of the wafer is exposed.
Further, the area of the coating is identical as the area of the upper surface of the wafer.
Further, the first metal layer is titanium coating.
Further, the first metal layer with a thickness of 1000 angstroms.
Further, the second metal layer is nickel-vanadium alloy metal layer.
Further, the second metal layer with a thickness of 3500 angstroms.
Further, the third metal layer is made of gold.
Further, the third metal layer with a thickness of 1000 angstroms.
Further, the area of the first metal layer, the area of the second metal layer and the third metal layer
Area three is identical.
Further, the radiator is welded on the coating by solder layer.
Further, the solder in the solder layer is tin.
Further, the solder layer with a thickness of 0.1-0.15 millimeters.
Further, the area of the solder layer is identical as the area of the coating, alternatively, the area of the solder layer with
The area of the lower surface of the radiator is identical.
Further, the upper surface of the coating is flushed with the upper surface of the plastic package structure, alternatively, under the coating
Surface is flushed with the upper surface of the plastic package structure.
The embodiment of the present application also provides a kind of chip structures, including chip body and setting are on the chip body
Described in any item chip cooling structures as above.
The embodiment of the present application also provides a kind of circuit board, at least one core as described above is provided on the circuit board
Chip architecture.
The embodiment of the present application also provides a kind of supercomputer equipment, at least one is provided in the supercomputer equipment as described above
Circuit board.
In above various aspects, by providing the chip cooling structure being made of coating, chip cooling structure is for setting
It sets on chip, coating is covered on the wafer of chip, and radiator is connect with coating；Wherein, coating includes set gradually
One metal layer, second metal layer and third metal layer；Furthermore, it is possible to connect radiator on coating.Pass through at the top of chip
The mode of physical sputtering increases by three metal layers, so as to which radiator is welded on the metal layer by solder layer, and then will
Radiator is fixed to the top of chip；The main component of solder layer is metallic tin, and metal layer is mounted relative to traditional heat sinks
Epoxy resin (epoxy) glue material has higher thermal coefficient, to solve the problems, such as the heat dissipation bottleneck of glue material in chip；
The heat dissipation effect that chip can be promoted prevents a large amount of heat loss chip.
Detailed description of the invention
One or more embodiments are illustrated by corresponding attached drawing, these exemplary illustrations and attached drawing
The restriction to embodiment is not constituted, the element with same reference numbers label is shown as similar element in attached drawing, and attached drawing is not
Composition limitation, and wherein:
Fig. 1 is a kind of structural schematic diagram one of chip cooling structure provided by the embodiments of the present application；
Fig. 2 is a kind of structural schematic diagram two of chip cooling structure provided by the embodiments of the present application；
Fig. 3 is a kind of structural schematic diagram three of chip cooling structure provided by the embodiments of the present application；
Fig. 4 is the structural schematic diagram one of radiator provided by the embodiments of the present application；
Fig. 5 is the structural schematic diagram two of radiator provided by the embodiments of the present application；
Fig. 6 is the structural schematic diagram one of another chip cooling structure provided by the embodiments of the present application；
Fig. 7 is the structural schematic diagram two of another chip cooling structure provided by the embodiments of the present application；
Fig. 8 is the structural schematic diagram three of another chip cooling structure provided by the embodiments of the present application；
Fig. 9 is the structural schematic diagram four of another chip cooling structure provided by the embodiments of the present application；
Figure 10 is the structural schematic diagram five of another chip cooling structure provided by the embodiments of the present application；
Figure 11 is the structural schematic diagram six of another chip cooling structure provided by the embodiments of the present application；
Figure 12 is the structural schematic diagram seven of another chip cooling structure provided by the embodiments of the present application；
Figure 13 is the structural schematic diagram eight of another chip cooling structure provided by the embodiments of the present application；
Figure 14 is the structural schematic diagram nine of another chip cooling structure provided by the embodiments of the present application；
Figure 15 is the structural schematic diagram of wafer provided by the embodiments of the present application；
Figure 16 is the structural schematic diagram of the wafer after cutting provided by the embodiments of the present application；
Figure 17 is the process flow diagram one of chip provided by the embodiments of the present application；
Figure 18 is the process flow diagram two of chip provided by the embodiments of the present application；
Figure 19 is the process flow diagram three of chip provided by the embodiments of the present application；
Figure 20 is the structural schematic diagram one of chip structure provided by the embodiments of the present application；
Figure 21 is the structural schematic diagram two of chip structure provided by the embodiments of the present application；
Figure 22 is the structural schematic diagram of circuit board provided by the embodiments of the present application；
Figure 23 is the structural schematic diagram of supercomputer equipment provided by the embodiments of the present application.
Appended drawing reference:
Specific embodiment
The embodiment of the present application is applied in chip.It should be noted that the scheme when the embodiment of the present application is applied to now
Chip or the future may appear chip when, the title of each structure may change, but this have no effect on the application implementation
The implementation of example scheme.
It should be pointed out that noun involved in the embodiment of the present application or term can be referred to mutually, repeat no more.
In the prior art, dew die encapsulation is carried out to wafer, refers to wafer is exposed, and then can achieve better heat dissipation
Purpose, wherein Silicon Wafer can be referred to as wafer.It is glued at the top of chip while revealing die encapsulation using traditional heat-conducting glue
Radiator is pasted, but the thermal coefficient of conventional thermal conductive glue is generally lower than 2W/ (mC), and then leads to the heat dissipation effect of chip not
It is good, become system radiating bottleneck.In order to reach better heat dissipation effect, the solder (solder) with high thermal conductivity, which becomes, is led
The thermal coefficient of the ideal alternative materials of hot glue, solder is higher than 60W/ (mC), is capable of dissipating for the improvement chip of high degree
The thermal efficiency.But solder can not be welded well with the plastic package structure of wafer and chip.
Chip cooling structure, chip structure, circuit board and supercomputer equipment provided by the present application, it is intended to solve the prior art
Technical problem as above.
The characteristics of in order to more fully hereinafter understand the embodiment of the present application and technology contents, with reference to the accompanying drawing to this Shen
Please the realization of embodiment be described in detail, appended attached drawing purposes of discussion only for reference is not used to limit the embodiment of the present application.
In technical description below, for convenience of explanation for the sake of, disclosed embodiment is fully understood with providing by multiple details.
However, one or more embodiments still can be implemented in the case where without these details.It in other cases, is simplification
Attached drawing, well known construction and device can simplify displaying.
Fig. 1 is a kind of structural schematic diagram one of chip cooling structure provided by the embodiments of the present application, and Fig. 2 is the application implementation
A kind of structural schematic diagram two for chip cooling structure that example provides, Fig. 3 are a kind of chip cooling knot provided by the embodiments of the present application
The structural schematic diagram three of structure, as shown in Figure 1-Figure 3, the chip cooling structure are arranged on chip, which includes:
The coating 1 being covered on the wafer 9 of chip；Wherein, coating 1 includes the first metal layer 3,4 and of second metal layer set gradually
Third metal layer 5.
Illustratively, chip cooling structure provided by the present application can be set on chip.Wherein, chip includes wafer
9, plastic package structure 11 and substrate 12；Groove is opened up on plastic package structure 11, wafer 9 can be arranged in groove, and then plastic packaging
Wafer 9 is packaged by structure 11, and the upper surface of wafer 9 be it is exposed, as dew die structure；By plastic package structure
11 are fixed on a side of substrate 12；Furthermore it is also possible to which at least one is arranged on another side of substrate 12
Tin ball 13, tin ball 13 are fixed on circuit boards for connecting with circuit board, and then by chip.
As foregoing description, since solder can not be welded well with wafer 9, the application by
One layer of coating 1 is covered on wafer 9, to realize connection chip by welding and external radiator 2.
The shape of wafer 9 can be circle or be rectangle or be square or be trapezoidal or be other
Regular shape or be other irregular shapes；For the shape of wafer 9, the application is with no restrictions.For the material of wafer 9,
The application is with no restrictions.
For the shape of plastic package structure 11, the application is with no restrictions, it is only necessary to which plastic package structure 11 can mould wafer 9
Envelope.For the material of plastic package structure 11, the application is with no restrictions.
Coating 1 includes the first metal layer 3, second metal layer 4 and the third metal layer 5 set gradually；The first metal layer 3,
Material used by second metal layer 4 and third metal layer 5 is different.Wherein, the first metal layer 3, second metal layer 4 and
The thickness of three metal layers 5 can be identical or different；The face of the first metal layer 3, second metal layer 4 and third metal layer 5
Product can be identical or different.
Optionally, coating 1 can be latticed, i.e., the first metal layer 3 is latticed, second metal layer 4 be it is latticed, the
Three metal layers 5 be it is latticed, the cost of coating 1 can be saved.
In another embodiment, chip cooling structure further includes radiator 2, wherein coating 1 is covered on chip, i.e.,
Coating 1 is covered on wafer 9；Radiator 2 is connect with coating 1.Wherein, it is carried out between radiator 2 and coating 1 by welding manner
Connection.
For shape, the size etc. of radiator 2, the application is with no restrictions.
For example, Fig. 4 is the structural schematic diagram one of radiator provided by the embodiments of the present application, as shown in figure 4, radiator
2 are made of egative film 6 and at least one radiating fin 7, each radiating fin 7 is fixedly connected with egative film 6, and egative film 6 and plating
It is welded on the surface of layer 1.
Again for example, Fig. 5 is the structural schematic diagram two of radiator provided by the embodiments of the present application, as shown in figure 5, may be used also
To be provided with an interconnecting piece 8 on radiator 2, the first plate and the second plate are constituted interconnecting piece 8 by including, and the first plate and the
It is in predetermined angle between two plates, which can be in the range of 180 degree be to 90 degree；Also, each fixation of radiating fin 7 is set
It sets in the upper surface of interconnecting piece 8, egative film 6 is fixed at the lower surface of interconnecting piece 8；In addition, one of them in radiator 2 dissipates
A handgrip can be set on hot fin 7.
The present embodiment, by providing the chip cooling structure being made of coating 1, chip cooling structure is for being arranged in chip
On, coating 1 is covered on the wafer 9 of chip, and radiator 2 is connect with coating 1；Wherein, coating 1 includes the first gold medal set gradually
Belong to layer 3, second metal layer 4 and third metal layer 5；Furthermore, it is possible to on coating 1 connect radiator 2.Pass through at the top of chip
The mode of physical sputtering increases by three metal layers, so as to which radiator 2 is welded on the metal layer by solder layer, and then will
Radiator 2 is fixed to the top of chip；The main component of solder layer is metallic tin, and metal layer is mounted relative to traditional heat sinks
Epoxy glue material has higher thermal coefficient, to solve the problems, such as the heat dissipation bottleneck of glue material in chip；Core can be promoted
The heat dissipation effect of piece prevents a large amount of heat loss chip.
Fig. 6 is the structural schematic diagram one of another chip cooling structure provided by the embodiments of the present application, and Fig. 7 is that the application is real
The structural schematic diagram two that another chip cooling structure of example offer is provided, on the basis of embodiment shown in Fig. 1, such as Fig. 6 and Fig. 7
Shown, the first metal layer 3 is covered on wafer 9, and second metal layer 4 is covered on the first metal layer 3, and third metal layer 5 covers
In second metal layer 4.
Optionally, the area of coating 1 is identical as the area of the upper surface of wafer 9.
Optionally, the first metal layer 3 is titanium coating.The first metal layer 3 with a thickness of 1000 angstroms.
Optionally, second metal layer 4 is nickel-vanadium alloy metal layer.Second metal layer 4 with a thickness of 3500 angstroms.
Optionally, third metal layer 5 is made of gold.Third metal layer 5 with a thickness of 1000 angstroms.
Optionally, area three's phase of the area of the first metal layer 3, the area of second metal layer 4 and third metal layer 5
Together.
Optionally, radiator 2 is welded on coating 1 by solder layer 10.Solder in solder layer 10 is tin.Solder layer 10
With a thickness of 0.1-0.15 millimeters.
Optionally, the area of solder layer 10 is identical as the area of coating 1, alternatively, the area of solder layer 10 and radiator 2
The area of lower surface is identical.
Optionally, the upper surface of coating 1 is flushed with the upper surface of plastic package structure 11, alternatively, the lower surface of coating 1 and plastic packaging
The upper surface of structure 11 flushes.
Illustratively, on the basis of embodiment shown in Fig. 1, the first metal layer 3 is covered on the upper surface of wafer 9,
Second metal layer 4 is covered on the upper surface of the first metal layer 3, third metal layer 5 is covered on to the upper table of second metal layer 4
On face.
In the present embodiment, the material of the first metal layer 3 is titanium (Ti), i.e., the first metal layer 3 is titanium coating；Second metal
The material of layer 4 is nickel-vanadium alloy (NiV), i.e., second metal layer 4 is nickel-vanadium alloy metal layer；The material of third metal layer 5 is gold
(Au).In turn, titanium coating is covered on the upper surface of wafer 9, and nickel-vanadium alloy is covered on the upper surface of titanium coating, golden
Metal layer is covered on the upper surface of nickel-vanadium alloy metal layer.
In order to be conducive to the connection of above three metal layer Yu chip, radiator 2, and be conducive to above three metal layer
Carry out thermally conductive and radiate to chip, can be set above three metal layer with a thickness of following parameter；The first metal layer 3
With a thickness of 1000 angstroms, second metal layer 4 with a thickness of 3500 angstroms, third metal layer 5 with a thickness of 1000 angstroms.
In the present embodiment, one layer of solder layer is set on coating 1, i.e., one layer of solder layer 10 is set on third metal layer 5；
Radiator 2 is welded with solder layer 10.The material of solder layer 10 is tin.Optionally, solder layer 10 with a thickness of 0.1-0.15
Millimeter；Preferably, solder layer 10 with a thickness of 0.13 millimeter.10 thermal coefficient of solder layer is higher than 60W/ (mC), can be improved
The heat dissipation effect of chip.
In the present embodiment, the area of coating 1 is identical as the area of the upper surface of wafer 9, at this point, the face of the first metal layer 3
Product is identical as the area of the upper surface of wafer 9.As shown in fig. 6, the area of the area of the first metal layer 3, second metal layer 4 and
The area of three metal layers 5, three are identical.Alternatively, Fig. 8 is another chip cooling structure provided by the embodiments of the present application
Structural schematic diagram three, as shown in figure 8, the face of the area of the first metal layer 3, the area of second metal layer 4 and third metal layer 5
Product, three is different.Alternatively, Fig. 9 is the structural representation of another chip cooling structure provided by the embodiments of the present application
Figure four, as shown in figure 9, having in the area of the area of the first metal layer 3, the area of second metal layer 4 and third metal layer 5
It is identical, some differences, for example, the area of the first metal layer 3 is identical as the area of third metal layer 5, the area of the first metal layer 3
It is different from the area of second metal layer 4.
In the present embodiment, the area of solder layer 10 provides following methods.
The first embodiment of the area of solder layer 10: as shown in fig. 7, the area of the first metal layer 3, second metal layer
4 area and the area three of third metal layer 5 are identical, also, the area of solder layer 10 is identical as the area of coating 1,
The area of coating 1 is identical as the area of the upper surface of wafer 9.
Second of embodiment of the area of solder layer 10: Figure 10 is another chip cooling provided by the embodiments of the present application
The structural schematic diagram five of structure, as shown in Figure 10, the area of the first metal layer 3, the area of second metal layer 4 and third metal layer
5 area three is identical, also, the area of solder layer 10 and the area of coating 1 are different, for example, solder layer 10
Area is greater than the area of coating 1；The area of coating 1 is identical as the area of the upper surface of wafer 9.
The third embodiment of the area of solder layer 10: Figure 11 is another chip cooling provided by the embodiments of the present application
The structural schematic diagram six of structure, as shown in figure 11, the area of the first metal layer 3, the area of second metal layer 4 and third metal layer
5 area three is identical, also, the area of solder layer 10 and the area of the lower surface of radiator 2 are identical；Wherein, it welds
The area of the bed of material 10 is different from the area of coating 1, and the area of coating 1 is identical as the area of the upper surface of wafer 9.Solder layer 10
Area is identical as the base area of radiator 2, is conducive to radiator 2 and solder layer 10 carrying out good connection.
4th kind of embodiment of the area of solder layer 10: Figure 12 is another chip cooling provided by the embodiments of the present application
The structural schematic diagram seven of structure, as shown in figure 12, the area of the first metal layer 3, the area of second metal layer 4 and third metal layer
5 area three is identical, also, the area of solder layer 10 and the area of the lower surface of radiator 2 are identical；Wherein, it welds
The area of the bed of material 10 is identical as the area of coating 1, and the area of coating 1 is identical as the area of the upper surface of wafer 9.
5th kind of embodiment of the area of solder layer 10: the area of the lower surface of the area and radiator 2 of solder layer 10
When identical, the area three of the area of the first metal layer 3, the area of second metal layer 4 and third metal layer 5 can each phase
With or part it is identical.
The positional relationship of coating 1 and plastic package structure 11 includes following several embodiments.
The first embodiment of the positional relationship of coating 1 and plastic package structure 11: Figure 13 is provided by the embodiments of the present application
Another structural schematic diagram eight of chip cooling structure, as shown in figure 13, the upper surface of coating 1 and the upper surface of plastic package structure 11
It flushes, i.e., the upper surface of third metal layer 5 is flushed with the upper surface of plastic package structure 11.
Second of embodiment of the positional relationship of coating 1 and plastic package structure 11: Figure 14 is provided by the embodiments of the present application
Another structural schematic diagram nine of chip cooling structure, as shown in figure 14, the lower surface of coating 1 and the upper surface of plastic package structure 11
It flushes, i.e., the lower surface of the first metal layer 3 is flushed with the upper surface of plastic package structure 11.
In the present embodiment, the technical process for obtaining chip cooling structure is following procedure.
The first step, metal layer setting.
Figure 15 is the structural schematic diagram of wafer provided by the embodiments of the present application, as shown in figure 15, first at the back side of wafer 9
Electroplating processes are carried out, the first metal layer 3 are electroplated on the back side of wafer 9；Then, second metal layer 4 is electroplated onto the first gold medal
Belong on layer 3；Then, third metal layer 5 is electroplated onto second metal layer 4.
Second step, wafer cutting.
Figure 16 be cutting provided by the embodiments of the present application after wafer structural schematic diagram, as shown in figure 16, to wafer 9 into
Row cutting, the wafer 9 after obtaining cutting as shown in figure 15.
Third step, wafer attachment.
Figure 17 is the process flow diagram one of chip provided by the embodiments of the present application, as shown in figure 17, after cutting
Wafer 9 is mounted respectively on the substrate 12 of each chip.
4th step, chip plastic packaging.
Figure 18 is the process flow diagram two of chip provided by the embodiments of the present application, as shown in figure 18, to each base
Wafer 9 on plate 12 carries out plastic packaging processing, i.e., encapsulates wafer 9 using plastic package structure 11.
5th step, separating treatment.
Figure 19 is the process flow diagram three of chip provided by the embodiments of the present application, as shown in figure 19, to shown in Figure 18
Each chip carry out band-like separation (Strip Singulation) and handle, obtain each chip.
6th step, solder welding.
Solder layer 10 can be set on the third metal layer 5 of coating 1, then weld radiator 2 and solder layer 10
It connects.
The present embodiment, by providing the chip cooling structure being made of coating 1, chip cooling structure is for being arranged in chip
On, coating 1 is covered on the wafer 9 of chip, and radiator 2 is welded on coating 1 by solder layer 10；Wherein, coating 1 include according to
The first metal layer 3, second metal layer 4 and the third metal layer 5 of secondary setting；The first metal layer 3 is covered on wafer 9, the second gold medal
Belong to layer 4 to be covered on the first metal layer 3, third metal layer 5 is covered in second metal layer 4；Furthermore, it is possible to on coating 1
Connect radiator 2.Increase by three metal layers, by way of physical sputtering at the top of chip so as to dissipate by solder layer
Hot device 2 welds on the metal layer, and then radiator 2 is fixed to the top of chip；The main component of solder layer is metallic tin, gold
Belong to the epoxy glue material that layer is mounted relative to traditional heat sinks, there is higher thermal coefficient, to solve glue material in chip
The problem of heat dissipation bottleneck；Metal layer and solder layer 10 further accelerate the heat dissipation of chip；The heat dissipation effect of chip can be promoted
Fruit prevents a large amount of heat loss chip.
Figure 20 is the structural schematic diagram one of chip structure provided by the embodiments of the present application, and Figure 21 provides for the embodiment of the present application
Chip structure structural schematic diagram two, as shown in Figure 20 and Figure 21, chip structure include chip body and be arranged in chip
Chip cooling structure on ontology, wherein chip cooling structure uses chip cooling structure provided by the above embodiment.
Illustratively, chip body includes wafer 9, plastic package structure 11 and substrate 12；It is opened up on plastic package structure 11 recessed
Slot wafer 9 can be arranged in groove, and then wafer 9 is packaged by plastic package structure 11, and the upper surface with wafer 9
It is exposed；Plastic package structure 11 is fixed on a side of substrate 12；Furthermore it is also possible to substrate 12 another
At least one tin ball 13 is set on side, and tin ball 13 is fixed on circuit boards for connecting with circuit board, and then by chip.
Then chip cooling structure provided by the above embodiment is set on the wafer of chip body 9.Chip cooling structure
Structure and principle may refer to above-described embodiment, repeat no more.
In the present embodiment, at least one hole can be offered on plastic package structure 11；One or more at least one hole
Conductive structure is provided in a hole.Optionally, conductive structure is metal heat-conducting structure or nonmetallic heat conductive structure.To by
Aperture on plastic package structure 11, and conductive structure is set in hole, further radiate to chip structure.
For example, the material of metal heat-conducting structure includes at least one of copper, aluminium, silver, tin, gold, iron, aluminium alloy or more
Kind.The material of nonmetallic heat conductive structure includes at least one of resin, ceramics, graphite, graphene, water or a variety of.
The present embodiment, by the way that chip cooling structure provided by the above embodiment is arranged on the wafer 9 of chip body.Pass through
The chip cooling structure being made of coating is provided, for chip cooling structure for being arranged in chip, coating is covered on the crystalline substance of chip
On circle, radiator is connect with coating；Wherein, coating includes the first metal layer set gradually, second metal layer and third metal
Layer；Furthermore, it is possible to connect radiator on coating.Increase by three metal layers by way of physical sputtering at the top of chip,
So as to which radiator is welded on the metal layer by solder layer, and then the top by radiator fixed to chip；Solder layer
Main component be metallic tin, the epoxy glue material that metal layer mount relative to traditional heat sinks, with higher thermal coefficient,
To solve the problems, such as the heat dissipation bottleneck of glue material in chip；The heat dissipation effect that chip can be promoted prevents a large amount of heat from damaging
Hurt chip.
Figure 22 is the structural schematic diagram of circuit board provided by the embodiments of the present application, as shown in figure 22, the embodiment of the present application
The chip structure of at least one above-described embodiment is provided on circuit board 14.
Illustratively, the chip structure of at least one above-described embodiment is provided on circuit board 14, chip structure is the same as tin ball
It is fixedly connected with circuit board 14.
Position and number for the chip structure on circuit board 14 are with no restrictions.For example, can be in the upper of circuit board 14
At least one chip structure is arranged in surface；Alternatively, at least one chip structure can be set in the upper surface of circuit board 14, and
And at least one chip structure is set in the lower surface of circuit board 14.
The specific structure of chip structure on circuit board 14, can be identical or different.For example, a core on circuit board 14
The upper surface of coating is flushed with the upper surface of plastic package structure in chip architecture, coating in another chip structure on circuit board 14
Lower surface is flushed with the upper surface of plastic package structure.
Wherein, the structure and principle of chip structure may refer to above-described embodiment, repeat no more.
The present embodiment, by being provided with the chip structure of at least one above-described embodiment on circuit board 14, in chip knot
Chip cooling structure provided by the above embodiment is set on the wafer of structure.By providing the chip cooling structure being made of coating,
Chip cooling structure is for being arranged in chip, and coating is covered on the wafer of chip, and radiator is connect with coating；Wherein, it plates
Layer includes the first metal layer, second metal layer and the third metal layer set gradually；Furthermore, it is possible to radiate with connection on coating
Device.Increase by three metal layers, by way of physical sputtering at the top of chip so as to weld radiator by solder layer
On the metal layer, and then by radiator it is fixed to the top of chip；The main component of solder layer be metallic tin, metal layer relative to
The epoxy glue material of traditional heat sinks attachment, has higher thermal coefficient, thus solve the heat dissipation bottleneck of glue material in chip
Problem；The heat dissipation effect that chip can be promoted prevents a large amount of heat loss chip.Further, circuit board 14 is carried out scattered
Heat prevents the component on heat loss circuit board 14 and circuit board 14.
Figure 23 is the structural schematic diagram of supercomputer equipment provided by the embodiments of the present application, as shown in figure 23, the embodiment of the present application
At least one circuit board 14 provided by the above embodiment is provided in the supercomputer equipment of offer.
Optionally, parallel with one another between each circuit board 14 in supercomputer equipment.
Optionally, it may be provided with sliding slot on the cabinet of supercomputer equipment, sliding slot is used for and each circuit board 14 in supercomputer equipment
It is slidably connected.
Optionally, the cabinet two sides of supercomputer equipment are also provided with fan, the heat dissipation wind channel of fan can on circuit board 14
The heat dissipation cavity of radiator be consistent, so that quickly the heat that cabinet interior circuit board 14 generates is dispersed into outside cabinet, into
And provide the performance of supercomputer equipment.
Illustratively, one or more circuit boards 14 are set in supercomputer equipment, which uses above-described embodiment
The circuit board 14 of offer.The structure and function of circuit board 14 may refer to the introduction of above-described embodiment, repeat no more.
In the present embodiment, multiple circuit boards 14 can be subjected to parallel connection, then circuit board 14 in parallel is arranged in supercomputer
In equipment.In one embodiment, supercomputer equipment can be supercomputer server.
Circuit board 14 can choose the mode for being fixedly connected or being slidably connected with the connection type of supercomputer equipment.It is exemplary
Ground can be provided with one or more sliding slots on the cabinet of supercomputer equipment, and then circuit board 14 is arranged in sliding slot, so that
Circuit board 14 can slide on the chute.
Wherein, when multiple circuit board 14 are set in supercomputer equipment, each of multiple circuit boards 14 circuit board
14 structure can be identical or different.
The chip structure of at least one above-described embodiment is provided on each circuit board 14, chip structure is the same as tin ball and electricity
Road plate 14 is fixedly connected.
Wherein, the structure and principle of chip structure may refer to above-described embodiment, repeat no more.
The present embodiment provides one or more circuit boards 14 by the way that above-described embodiment is arranged in supercomputer equipment, every
It is provided with the chip structure of at least one above-described embodiment on one circuit board 14, above-mentioned reality is set on the wafer of chip structure
The chip cooling structure of example offer is provided.By providing the chip cooling structure being made of coating, chip cooling structure is for being arranged
On chip, coating is covered on the wafer of chip, and radiator is connect with coating；Wherein, coating includes first set gradually
Metal layer, second metal layer and third metal layer；Furthermore, it is possible to connect radiator on coating.Pass through object at the top of chip
The mode of reason sputtering increases by three metal layers, so as to be welded radiator on the metal layer by solder layer, and then will dissipate
Hot device is fixed to the top of chip；The main component of solder layer is metallic tin, and metal layer is mounted relative to traditional heat sinks
Epoxy glue material has higher thermal coefficient, to solve the problems, such as the heat dissipation bottleneck of glue material in chip；Core can be promoted
The heat dissipation effect of piece prevents a large amount of heat loss chip.Further, it radiates to circuit board 14, prevents heat loss
Component on circuit board 14 and circuit board 14.
When in the application, although term " first ", " second " etc. may be used in this application to describe respectively
Element, but these elements should not be limited by these terms.These terms are only used to by an element and another element region
It does not open.For example, in the case where not changing the meaning of description, first element can be called second element, and same, second
Element can be called first element, as long as " second yuan that " first element " occurred is unanimously renamed and occurred
Part " unanimously renames.First element and second element are all elements, but can not be identical element.
Word used herein is only used for description embodiment and is not used in limitation claim.Such as embodiment with
And used in the description of claim, unless context clearly illustrates, otherwise "one" (a) of singular, "one"
(an) and " described " (the) is intended to include equally plural form.Similarly, term "and/or" as used in this specification
Refer to comprising one or more associated any and all possible combinations listed.In addition, when being used for the application
When middle, term " includes " (comprise) and its modification " comprising " (comprises) and/or refer to including (comprising) etc. old
The presence of feature, entirety, step, operation, element and/or the component stated, but be not excluded for one or more other features,
Entirety, step, operation, element, component and/or these grouping presence or addition.
Various aspects, embodiment, realization or feature in described embodiment can be used alone or in any combination
Mode use.
Above-mentioned technical description can refer to attached drawing, these attached drawings form a part of the application, and by description attached
The embodiment according to described embodiment is shown in figure.Although the description of these embodiments is enough in detail so that this field
Technical staff can be realized these embodiments, but these embodiments are non-limiting；Other implementations thus can be used
Example, and variation can also be made in the case where not departing from the range of described embodiment.For example, described in flow chart
Operation order be non-limiting, therefore in flow charts illustrate and according to flow chart description two or more behaviour
The sequence of work can be changed according to several embodiments.As another example, in several embodiments, it explains in flow charts
It releases and is optional or deletable according to one or more operations that flow chart describes.In addition, certain steps or
Function can be added in the disclosed embodiments or more than two sequence of steps are replaced.All these variations are considered
Included in the disclosed embodiments and claim.
In addition, using term to provide the thorough understanding of described embodiment in above-mentioned technical description.However, and being not required to
Will excessively detailed details to realize described embodiment.Therefore, the foregoing description of embodiment be in order to illustrate and describe and
It presents.The embodiment and example disclosed according to these embodiments presented in foregoing description is provided separately, with
Addition context simultaneously helps to understand described embodiment.Description above, which is not used in, accomplishes exhaustive or by described reality
Apply the precise forms that example is restricted to the application.According to the above instruction, it is several modification, selection be applicable in and variation be feasible.?
In some cases, processing step well known is not described in avoid described embodiment is unnecessarily influenced.
Claims (20)
1. a kind of chip cooling structure is arranged on chip, which is characterized in that the chip cooling structure includes: to be covered on institute
State the coating on the wafer of chip；
Wherein, the coating includes the first metal layer set gradually, second metal layer and third metal layer.
2. chip cooling structure according to claim 1, which is characterized in that the chip cooling structure further include: with institute
State the radiator of coating connection.
3. chip cooling structure according to claim 1, which is characterized in that the first metal layer is covered on the wafer
On, the second metal layer is covered on the first metal layer, and the third metal layer is covered in the second metal layer.
4. chip cooling structure according to claim 1, which is characterized in that the chip includes the wafer and plastic packaging knot
The upper surface of structure, the wafer is exposed.
5. chip cooling structure according to claim 1, which is characterized in that the area of the coating is upper with the wafer
The area on surface is identical.
6. chip cooling structure according to claim 1-5, which is characterized in that the first metal layer is titanium
Belong to layer.
7. chip cooling structure according to claim 6, which is characterized in that the first metal layer with a thickness of 1000
Angstrom.
8. chip cooling structure according to claim 1-5, which is characterized in that the second metal layer is nickel vanadium
Alloying metal layer.
9. chip cooling structure according to claim 8, which is characterized in that the second metal layer with a thickness of 3500
Angstrom.
10. chip cooling structure according to claim 1-5, which is characterized in that the third metal layer is by gold
It is manufactured.
11. chip cooling structure according to claim 10, which is characterized in that the third metal layer with a thickness of 1000
Angstrom.
12. chip cooling structure according to claim 1-5, which is characterized in that the face of the first metal layer
The area of long-pending, the described second metal layer is identical with the area three of the third metal layer.
13. chip cooling structure according to claim 2, which is characterized in that the radiator is welded on by solder layer
On the coating.
14. chip cooling structure according to claim 13, which is characterized in that the solder in the solder layer is tin.
15. chip cooling structure according to claim 14, which is characterized in that the solder layer with a thickness of 0.1-0.15
Millimeter.
16. chip cooling structure according to claim 13, which is characterized in that the area of the solder layer and the coating
Area it is identical, alternatively, the area of the solder layer is identical as the area of the lower surface of the radiator.
17. chip cooling structure according to claim 4, which is characterized in that the upper surface of the coating and the plastic packaging
The upper surface of structure flushes, alternatively, the lower surface of the coating is flushed with the upper surface of the plastic package structure.
18. a kind of chip structure, which is characterized in that including chip body and be arranged on the chip body as right is wanted
Seek the described in any item chip cooling structures of 1-17.
19. a kind of circuit board, which is characterized in that be provided at least one chip as claimed in claim 18 on the circuit board
Structure.
20. a kind of supercomputer equipment, which is characterized in that it is as claimed in claim 19 to be provided at least one in the supercomputer equipment
Circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821942991.5U CN209029362U (en) | 2018-11-23 | 2018-11-23 | Chip cooling structure, chip structure, circuit board and supercomputer equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821942991.5U CN209029362U (en) | 2018-11-23 | 2018-11-23 | Chip cooling structure, chip structure, circuit board and supercomputer equipment |
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| CN209029362U true CN209029362U (en) | 2019-06-25 |
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ID=66910730
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| CN201821942991.5U Active CN209029362U (en) | 2018-11-23 | 2018-11-23 | Chip cooling structure, chip structure, circuit board and supercomputer equipment |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111148342A (en) * | 2020-01-14 | 2020-05-12 | 北京比特大陆科技有限公司 | Circuit board heat abstractor and server that has it |
| CN111508947A (en) * | 2019-01-30 | 2020-08-07 | 联发科技股份有限公司 | Semiconductor package and printed circuit board |
| CN113113369A (en) * | 2020-01-13 | 2021-07-13 | 华为技术有限公司 | Heat dissipation structure, manufacturing method thereof, chip structure and electronic equipment |
-
2018
- 2018-11-23 CN CN201821942991.5U patent/CN209029362U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508947A (en) * | 2019-01-30 | 2020-08-07 | 联发科技股份有限公司 | Semiconductor package and printed circuit board |
| US11227846B2 (en) | 2019-01-30 | 2022-01-18 | Mediatek Inc. | Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure |
| US11302657B2 (en) | 2019-01-30 | 2022-04-12 | Mediatek Inc. | Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure |
| US11705413B2 (en) | 2019-01-30 | 2023-07-18 | Mediatek Inc. | Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure |
| US11967570B2 (en) | 2019-01-30 | 2024-04-23 | Mediatek Inc. | Semiconductor package having improved thermal interface between semiconductor die and heat spreading structure |
| CN113113369A (en) * | 2020-01-13 | 2021-07-13 | 华为技术有限公司 | Heat dissipation structure, manufacturing method thereof, chip structure and electronic equipment |
| CN111148342A (en) * | 2020-01-14 | 2020-05-12 | 北京比特大陆科技有限公司 | Circuit board heat abstractor and server that has it |
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