CN209017168U - A kind of mixed structure capacitor, pixel circuit and imaging device - Google Patents
A kind of mixed structure capacitor, pixel circuit and imaging device Download PDFInfo
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- CN209017168U CN209017168U CN201822049548.1U CN201822049548U CN209017168U CN 209017168 U CN209017168 U CN 209017168U CN 201822049548 U CN201822049548 U CN 201822049548U CN 209017168 U CN209017168 U CN 209017168U
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Abstract
The utility model relates to a kind of mixed structure capacitor, pixel circuit and imaging devices.Wherein, mixed structure capacitor includes mos capacitance and metal-metal capacitor.The mos capacitance is set in semiconductor substrate, and the metal-metal capacitor is set in the dielectric layer in the semiconductor substrate, and the metal-metal capacitor is located at the top of the mos capacitance.And the source electrode and drain electrode of the mos capacitance is connect with the first electrode plate of the metal-metal capacitor, the grid of the mos capacitance is connect with the second electrode plate of the metal-metal capacitor.Since mos capacitance and metal-metal capacitor are vertically arranged on the direction perpendicular to semiconductor substrate surface, and it is mos capacitance is in parallel with metal-metal capacitor progress, so as under conditions of not increasing capacity area, increase the capacitance of capacitor, the capacitance density in unit area is improved.
Description
Technical field
The utility model relates to field of semiconductor devices more particularly to a kind of mixed structure capacitor, pixel circuit and at
As device.
Background technique
Cmos image sensor (CMOS Image Sensor, abbreviation CIS) is that optical imagery is changed into digital picture is defeated
Semiconductor device out.In order to realize the noise objective that can be compared favourably with CCD converter and level of sensitivity, cmos image sensing
Device applies active pixel.Meanwhile cmos image sensor uses CMOS integrated circuit technology, by pixel array photosensitive structure and
Other CMOS simulation, digital circuit are integrated on same chip, highly integrated not only to reduce complete machine number of chips, reduce complete machine
Power consumption and packaging cost, and the connection of chip interior direct signal also helps the quality and speed of signal transmission, to improve
The quality of image conversion.In recent years, cmos image sensor is on the one hand further towards " faster, smaller, lighter, cheaper "
Developing direction continues to develop, and on the other hand, requirement of the consumer to picture quality is also higher and higher.
Two key factors for determining the picture quality of cmos image sensor are dark current and dynamic range.Cmos image
The dynamic range of sensor is determined by the amount of charge that photodiode PD can accumulate.But since charge is converted into voltage
When signal, the amount of charge that can detecte depends on the voltage amplitude and capacitance of floating diffusion region FD again, therefore floats and expand
The voltage amplitude and capacitance that dissipate area FD determine the actual dynamic range of imaging sensor, and the quality of the bigger image of capacitance is more
It is high.
To the capacitor for storing photogenerated charge, the size of capacitance is usually directly proportional to the area of capacitor, if passing through
The mode for increasing capacity area improves capacitance, will certainly reduce the photosensitive area of photodiode, lead to pixel unit
Sensitivity decrease.
Therefore, how photodiode photosensitive area is not being influenced, under conditions of not increasing capacity area, is increasing capacitor
Capacitance is current industry technical problem urgently to be solved.
Utility model content
Aiming at the problems existing in the prior art, the purpose of this utility model is to provide a kind of mixed structure capacitor, as
Plain circuit and imaging device.The mixed structure capacitor and pixel circuit and imaging device with the mixed structure capacitor,
The capacitance of capacitor can be increased under conditions of not increasing capacity area, improve the capacitance density in unit area.
In order to reach foregoing purpose, the utility model provides a kind of mixed structure capacitor, comprising:
Mos capacitance is set in semiconductor substrate；
Metal-metal capacitor is set in the dielectric layer in the semiconductor substrate；
Wherein, the metal-metal capacitor is located at the top of the mos capacitance；The source electrode and drain electrode of the mos capacitance with
The first electrode plate of the metal-metal capacitor connects, and the second of the grid of the mos capacitance and the metal-metal capacitor
Electrode plate connection.
Further, the metal-metal capacitor includes MIM capacitor and/or MOM capacitor.
The utility model also provides a kind of pixel circuit, and the pixel circuit includes mixed structure capacitor；The mixing knot
Structure capacitor includes:
Mos capacitance is set in semiconductor substrate；
Metal-metal capacitor is set in the dielectric layer in the semiconductor substrate；
Wherein, the metal-metal capacitor is located at the top of the mos capacitance；The source electrode and drain electrode of the mos capacitance with
The first electrode plate of the metal-metal capacitor connects, and the second of the grid of the mos capacitance and the metal-metal capacitor
Electrode plate connection.
Further, the metal-metal capacitor includes MIM capacitor and/or MOM capacitor.
Further, the pixel circuit includes dual conversion gain control unit, the dual conversion gain control unit packet
A storage capacitance is included, the storage capacitance is mixed structure capacitor.
Further, the pixel circuit includes global exposure output unit, and the global exposure output unit includes picture
Plain signal storage capacitance and reset signal storage capacitance, the picture element signal storage capacitance and/or reset signal storage capacitance are
Mixed structure capacitor.
The utility model also provides a kind of imaging device, comprising:
Pixel array, the pixel array include the multiple pixel circuits for being arranged to row and column；
Peripheral circuit, controls the pixel array, and to the picture element signal of pixel array output carry out quantization and
Processing；
The pixel circuit includes mixed structure capacitor；The mixed structure capacitor includes:
Mos capacitance is set in semiconductor substrate；
Metal-metal capacitor is set in the dielectric layer in the semiconductor substrate；
Wherein, the metal-metal capacitor is located at the top of the mos capacitance；The source electrode and drain electrode of the mos capacitance with
The first electrode plate of the metal-metal capacitor connects, and the second of the grid of the mos capacitance and the metal-metal capacitor
Electrode plate connection.
Further, the metal-metal capacitor includes MIM capacitor and/or MOM capacitor.
Further, the pixel circuit includes dual conversion gain control unit, the dual conversion gain control unit packet
A storage capacitance is included, the storage capacitance is mixed structure capacitor.
Further, the pixel circuit includes global exposure output unit, and the global exposure output unit includes picture
Plain signal storage capacitance and reset signal storage capacitance, the picture element signal storage capacitance and/or reset signal storage capacitance are
Mixed structure capacitor.
Compared with prior art, mixed structure capacitor provided by the utility model comprising mos capacitance and metal-metal
Capacitor.The mos capacitance is set in semiconductor substrate, and the metal-metal capacitor is set in the semiconductor substrate
In dielectric layer, the metal-metal capacitor is located at the top of the mos capacitance.And source electrode and drain electrode and the institute of the mos capacitance
State the first electrode plate connection of metal-metal capacitor, the second electricity of the grid of the mos capacitance and the metal-metal capacitor
Pole plate connection.Since mos capacitance and metal-metal capacitor are vertically arranged on the direction perpendicular to semiconductor substrate surface, with
And mos capacitance is in parallel with metal-metal capacitor progress, so as to increase capacitor under conditions of not increasing capacity area
Capacitance, improve unit area in capacitance density.
For pixel circuit or imaging device including above-mentioned mixed structure capacitor, capacity area can not increased
While, the sensitivity of pixel circuit is improved, and then improve the dynamic range and imaging of the imaging device including the pixel circuit
Quality.
Detailed description of the invention
In the following, preferred embodiments of the present invention will be described in more detail in conjunction with attached drawing, in which:
Fig. 1 is the structural schematic diagram of mixed structure capacitor in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of mixed structure capacitor in another embodiment of the utility model；
Fig. 3 is the circuit diagram of pixel circuit in an embodiment of the present invention；
Fig. 4 is the circuit diagram of pixel circuit in another embodiment of the utility model；
Fig. 5 is the structural schematic diagram of imaging device in an embodiment of the present invention.
Specific embodiment
To keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, below in conjunction with specification reality
The attached drawing in example is applied, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that described
Embodiment is the utility model a part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, originally
Field those of ordinary skill every other embodiment obtained without making creative work belongs to practical
Novel protected range.
In the following detailed description, the specific reality for being used to illustrate this specification as this specification a part may refer to
Apply each Figure of description of example.It can be with repeat reference numerals and/or letter in each example in the accompanying drawings.This repetition is only
It is in order to concise and clear, its own is not offered as the relationship between discussed each embodiment and/or configuration.In addition, being
Convenient for description, can be used in this specification such as " in ... lower section ", " ... below ", " lower part ", " ... above ", " on
The spatial relation term in portion " etc., to describe the relationship of an element as illustrated in the drawing or component and another element or component.It removes
Outside orientation shown in figure, spatial relation term is intended to include different direction of the device in use or operating process.Device
The spatial relation description symbol that can be positioned in other ways and (be rotated by 90 ° or in other orientation), and use in the present specification
It can similarly be interpreted accordingly.Each specific embodiment of this specification has carried out description detailed enough following, makes
The those of ordinary skill that must have ability domain-dependent knowledge and technology can implement the technical solution of the application.It should be appreciated that also
It can use other embodiments or carry out the change of structure, logic or electrical property to the embodiment of this specification.
It is the structural schematic diagram of mixed structure capacitor in an embodiment of the present invention with reference to Fig. 1.Mixed structure in Fig. 1
Capacitor 100 includes mos capacitance and MIM capacitor, and the mos capacitance is set in semiconductor substrate (not shown)；The MIM capacitor
It is set in the dielectric layer (not shown) in the semiconductor substrate.
Wherein, the mos capacitance includes source electrode 101, drain electrode 103 and is located at half between the source electrode 101 and drain electrode 103
Grid 105 above conductor substrate, the source electrode 101 of the mos capacitance connect (not shown) with the source electrode 103 of the mos capacitance.
The MIM capacitor includes first electrode plate 107 and second electrode plate 109, the first electrode plate 107 and second electrode plate 109
Between be formed with dielectric layer.Metal interconnecting wires 111 and metal throuth hole 113 are also formed in the dielectric layer, being used for will be described
The grid 105 of mos capacitance is connect with the second electrode plate 109 of the MIM capacitor, and for by the drain electrode of the mos capacitance
103 connect with the first electrode plate 107 of the MIM capacitor.The MIM capacitor is located at the top of the mos capacitance.
In the present embodiment, the first electrode plate 107 and second electrode plate 109 can be formed by titanium nitride and/or tantalum nitride
Double layer of metal nitride layer and double layer of metal nitride layer between one layer of metal Al layer constitute, the thickness control of metal Al layer
System is at 2 μm or more, and the thickness control of metal nitride layer is between 150nm-200nm, for increased viscosity, metal nitride layer
The upper surface Titanium that can also plate one layer of 8nm-10nm or so or metal tantalum as superimposed layer.The metal Al layer can be with
It is replaced by Ni metal layer or u layers of metal W.The material of dielectric layer between the first electrode plate 107 and second electrode plate 109
Material can be SiO2, SiN or high dielectric (high k, k are dielectric constant) material.
In the present embodiment, since the MIM capacitor is located at the top of the mos capacitance, and the MIM capacitor and described
Mos capacitance is in parallel by metal interconnecting wires 111 and metal throuth hole 113, to increase in the case where not increasing capacity area
The capacitance of capacitor improves the capacitance density in unit area.
It is the structural schematic diagram of mixed structure capacitor in another embodiment of the utility model with reference to Fig. 2.Knot is mixed in Fig. 2
Structure capacitor 200 includes mos capacitance, MIM capacitor and MOM capacitor；The mos capacitance is set in semiconductor substrate (not shown)；
The MIM capacitor is set in the dielectric layer (not shown) in the semiconductor substrate；The MOM capacitor, which is set to, described partly to be led
In dielectric layer in body substrate.
Wherein, the mos capacitance includes source electrode 201, drain electrode 203 and is located at half between the source electrode 201 and drain electrode 203
Grid 205 above conductor substrate, the source electrode 201 of the mos capacitance connect (not shown) with the drain electrode 203 of the mos capacitance.
The MIM capacitor includes first electrode plate 207 and second electrode plate 209, the first electrode plate 207 and second electrode plate 209
Between be formed with dielectric layer.Metal interconnecting wires 211 and metal throuth hole 213 are also formed in the dielectric layer, being used for will be described
The grid 205 of mos capacitance is connect with the second electrode plate 209 of the MIM capacitor, and for by the drain electrode of the mos capacitance
203 connect with the first electrode plate 207 of the MIM capacitor.The metal throuth hole 213 is also used to as the MOM capacitor
One electrode plate or second electrode plate are connected by metal interconnecting wires 211 between each first electrode plate of the MOM capacitor,
It is connected between each second electrode plate of the MOM capacitor by metal interconnecting wires 211.The grid 205 of the mos capacitance and institute
State the second electrode plate 209 of MIM capacitor and the second electrode plate connection of the MOM capacitor, the drain electrode 203 of the mos capacitance
It is connect with the first electrode plate of the first electrode plate 207 of the MIM capacitor and the MOM capacitor.And the MIM capacitor and institute
State the top that MOM capacitor is located at the mos capacitance.
In the present embodiment, since the MIM capacitor and the MOM capacitor are located at the top of the mos capacitance, and it is described
MIM capacitor, MOM capacitor and the mos capacitance are in parallel by metal interconnecting wires 111 and metal throuth hole 113, thus not increasing electricity
In the case where holding area, the capacitance of capacitor is increased, improves the capacitance density in unit area.
In a further embodiment, MOM capacitor can also be only formed in the dielectric layer above mos capacitance, also can
In the case where not increasing capacity area, increase unit-area capacitance value, reaches the effect for improving the capacitance density in unit area
Fruit.
Fig. 3 is the circuit diagram of pixel circuit in an embodiment of the present invention.Pixel circuit 300 includes photoelectricity two in Fig. 3
Pole pipe PD, transfering transistor TX, reset transistor RST, source following transistor SF and row selecting transistor RS.Further,
Pixel circuit 300 further includes dual conversion gain (Double Conversion Gain, DCG) control unit in Fig. 3, and described double turns
It is mixed structure capacitor that gain control unit, which is changed, including storage capacitance a Cdcg, the storage capacitance Cdcg.Due to unit area
The capacitance of interior storage capacitance Cdcg is improved, therefore improves the gain effect of dual conversion gain, and then improves half-light
Under picture quality.
Fig. 4 is the circuit diagram of pixel circuit in another embodiment of the utility model.Pixel circuit 400 includes a light in Fig. 4
An electric diode PD and transfering transistor TX.Transfering transistor TX is connected to floating diffusion region FD.The floating diffusion region
FD connection one reset transistor RST and the first source following transistor SF.Pixel circuit 400 further includes that the second source electrode follows crystal
A pipe GSF and row selecting transistor GSW, is capable of forming output circuit, provides output signal.Pixel circuit 400 further wraps
Global exposure output unit is included, the global exposure output unit includes picture element signal storage capacitance CsigIt is stored with reset signal
Capacitor Crst.Picture element signal storage capacitance CsigWith reset signal storage capacitance CrstAnd corresponding switch GS_SIG and GS_RST
It is connected between the first source following transistor SF and the second source following transistor GSF.Wherein, the picture element signal storage electricity
Hold CsigFor mixed structure capacitor；Alternatively, the reset signal storage capacitance CrstFor mixed structure capacitor；Again alternatively, the picture
Plain signal storage capacitance CsigWith reset signal storage capacitance CrstIt is mixed structure capacitor.
In the case where the overall situation exposes (global shutter) state, due to picture element signal storage capacitance C in unit areasigWith/
Or reset signal storage capacitance CrstCapacitance significantly improve, the pixel circuit 400 read when noise very little, greatly improve
Signal-to-noise ratio；Further, it is also possible to the number of photodiode in pixel circuit 400 be continued growing, to improve image resolution ratio.
Fig. 3 and pixel circuit shown in Fig. 4 are only a kind of enforceable modes, and the pixel circuit of the utility model can be with
Including other structures.Since mixed structure capacitor does not increase its area while improving capacitance, it will not influence
The photosensitive area of photodiode in pixel circuit will not sacrifice pixel circuit while improving dynamic range and picture quality
Sensitivity.
Fig. 5 provides a kind of imaging device 500 using the utility model mixed structure capacitor, and especially a kind of image passes
Sensor, as shown in figure 5, imaging sensor includes pixel array 510.Pixel array 510 includes the multiple pictures being arranged in rows and columns
Plain unit.Each column pixel is connected by column selection line options in pixel array 510, and is driven by column driving unit 530；Often
One-row pixels are selectively exported by row select line respectively, and are driven by row driving unit 520.Specifically, each pixel list
Member includes a pixel circuit, and wherein at least one pixel circuit includes the mixed structure capacitor of the utility model.The figure of reading
The progress signal processing of image processing unit 560, composite high dynamic image are transferred to as signal is arranged A/D converting unit 550.Logic
Control unit 540 includes row driving unit 520, column driving unit 530, column A/D converting unit 550 and image to each functional unit
Processing unit 560 is controlled.
Specifically, the pixel circuit of pixel unit includes dual conversion gain control unit in pixel array 510, described double turns
Changing gain control unit includes a storage capacitance, and the storage capacitance is mixed structure capacitor.Alternatively, picture in pixel array 510
The pixel circuit of plain unit includes global exposure output unit, and the global exposure output unit includes picture element signal storage capacitance
With reset signal storage capacitance, the picture element signal storage capacitance and/or reset signal storage capacitance are mixed structure capacitor.
The imaging device 500 can be used in the various processing systems comprising the imaging device, in the case where without restriction,
This processing system may include computer system, camera system, scanner, machine vision, automobile navigation, visual telephone, monitoring system
System, autofocus system, star tracker system, movement detection systems, image stabilisation system and data compression system.
Include the imaging device with the pixel circuit of mixed structure capacitor in the present embodiment, capacitive surface can not increased
While product, improve the sensitivity of pixel circuit, so improve include the pixel circuit imaging device dynamic range and at
Image quality amount.
Above embodiments are only for illustration of the utility model, and are not limitations of the present invention, related technology
The those of ordinary skill in field can also make a variety of changes and modification in the case where not departing from the scope of the utility model, because
This, all equivalent technical solutions also should belong to scope disclosed by the utility model.
Claims (10)
1. a kind of mixed structure capacitor characterized by comprising
Mos capacitance is set in semiconductor substrate；
Metal-metal capacitor is set in the dielectric layer in the semiconductor substrate；
Wherein, the metal-metal capacitor is located at the top of the mos capacitance；The source electrode and drain electrode of the mos capacitance with it is described
The first electrode plate of metal-metal capacitor connects, the second electrode of the grid of the mos capacitance and the metal-metal capacitor
Plate connection.
2. mixed structure capacitor according to claim 1, which is characterized in that the metal-metal capacitor includes MIM capacitor
And/or MOM capacitor.
3. a kind of pixel circuit, which is characterized in that the pixel circuit includes mixed structure capacitor；The mixed structure capacitor packet
It includes:
Mos capacitance is set in semiconductor substrate；
Metal-metal capacitor is set in the dielectric layer in the semiconductor substrate；
Wherein, the metal-metal capacitor is located at the top of the mos capacitance；The source electrode and drain electrode of the mos capacitance with it is described
The first electrode plate of metal-metal capacitor connects, the second electrode of the grid of the mos capacitance and the metal-metal capacitor
Plate connection.
4. pixel circuit according to claim 3, which is characterized in that the metal-metal capacitor include MIM capacitor and/
Or MOM capacitor.
5. pixel circuit according to claim 3, which is characterized in that the pixel circuit includes that dual conversion gain control is single
Member, the dual conversion gain control unit include a storage capacitance, and the storage capacitance is mixed structure capacitor.
6. pixel circuit according to claim 3, which is characterized in that the pixel circuit includes that global exposure output is single
Member, the global exposure output unit includes picture element signal storage capacitance and reset signal storage capacitance, and the picture element signal is deposited
Storage is held and/or reset signal storage capacitance is mixed structure capacitor.
7. a kind of imaging device characterized by comprising
Pixel array, the pixel array include the multiple pixel circuits for being arranged to row and column；
Peripheral circuit controls the pixel array, and the picture element signal of pixel array output is quantified and handled；
The pixel circuit includes mixed structure capacitor；The mixed structure capacitor includes:
Mos capacitance is set in semiconductor substrate；
Metal-metal capacitor is set in the dielectric layer in the semiconductor substrate；
Wherein, the metal-metal capacitor is located at the top of the mos capacitance；The source electrode and drain electrode of the mos capacitance with it is described
The first electrode plate of metal-metal capacitor connects, the second electrode of the grid of the mos capacitance and the metal-metal capacitor
Plate connection.
8. imaging device according to claim 7, which is characterized in that the metal-metal capacitor include MIM capacitor and/
Or MOM capacitor.
9. imaging device according to claim 7, which is characterized in that the pixel circuit includes that dual conversion gain control is single
Member, the dual conversion gain control unit include a storage capacitance, and the storage capacitance is mixed structure capacitor.
10. imaging device according to claim 7, which is characterized in that the pixel circuit includes that global exposure output is single
Member, the global exposure output unit includes picture element signal storage capacitance and reset signal storage capacitance, and the picture element signal is deposited
Storage is held and/or reset signal storage capacitance is mixed structure capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822049548.1U CN209017168U (en) | 2018-12-07 | 2018-12-07 | A kind of mixed structure capacitor, pixel circuit and imaging device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201822049548.1U CN209017168U (en) | 2018-12-07 | 2018-12-07 | A kind of mixed structure capacitor, pixel circuit and imaging device |
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ID=66843594
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110661990A (en) * | 2018-06-29 | 2020-01-07 | 格科微电子（上海）有限公司 | Design method of pixel output signal blocking capacitor |
| CN110707113A (en) * | 2019-09-05 | 2020-01-17 | 成都微光集电科技有限公司 | Global exposure pixel unit and preparation method thereof |
| CN111952266A (en) * | 2020-07-09 | 2020-11-17 | 北京信息科技大学 | Capacitor and circuit element |
-
2018
- 2018-12-07 CN CN201822049548.1U patent/CN209017168U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110661990A (en) * | 2018-06-29 | 2020-01-07 | 格科微电子（上海）有限公司 | Design method of pixel output signal blocking capacitor |
| CN110661990B (en) * | 2018-06-29 | 2022-07-15 | 格科微电子（上海）有限公司 | Design method of pixel output signal blocking capacitor |
| CN110707113A (en) * | 2019-09-05 | 2020-01-17 | 成都微光集电科技有限公司 | Global exposure pixel unit and preparation method thereof |
| CN110707113B (en) * | 2019-09-05 | 2021-06-15 | 成都微光集电科技有限公司 | Global exposure pixel unit and preparation method thereof |
| CN111952266A (en) * | 2020-07-09 | 2020-11-17 | 北京信息科技大学 | Capacitor and circuit element |
| CN111952266B (en) * | 2020-07-09 | 2024-01-12 | 北京信息科技大学 | Capacitor and circuit element |
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Address after: Room 612, 6th floor, No. 111 Building, Xiangke Road, Shanghai Pudong New Area Free Trade Pilot Area, 201203 Patentee after: Starway (Shanghai) Electronic Technology Co.,Ltd. Address before: Room 612, 6th floor, No. 111 Building, Xiangke Road, Shanghai Pudong New Area Free Trade Pilot Area, 201203 Patentee before: Siteway (Shanghai) Electronic Technology Co.,Ltd. |
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