KR20200144405A - Pixel array and image sensor - Google Patents

Abstract

According to exemplary embodiments of the present invention, provided is a pixel array with enhanced reliability. The pixel array comprises a plurality of pixels. Each of the plurality of pixels can include: a photoelectric element formed on a substrate and generating an electric charge from light; and a pixel circuit formed between the photoelectric element and the substrate and configured to output a digital signal value based on an amount of the generated electric charge, wherein the pixel circuit can include: floating diffusion formed in the substrate and storing the electric charge; a vertical pixel electrode connecting the floating diffusion and the photoelectric element and extending in a direction perpendicular to the substrate; an analog-to-digital converter configured to convert potential of the floating diffusion into the digital signal value; and a memory element configured to store the digital signal value.

Description

Pixel array and image sensor {PIXEL ARRAY AND IMAGE SENSOR}

The technical idea of the present invention relates to a charge pump device and an image sensor including the charge pump device.

The image sensor is a semiconductor-based sensor that receives light and generates an electrical signal, and may include a pixel array having a plurality of pixels and a circuit for driving the pixel array. The image sensor can be widely applied to smart phones, tablet PCs, laptop computers, and televisions, as well as cameras for taking photos or videos. Recently, as the demand for devices and applications utilizing wavelength bands other than the visible light region is increasing, research on image sensors using photoelectric devices other than semiconductor photoelectric devices continues.

A problem to be solved by the technical idea of the present disclosure is to provide a pixel array and an image processing apparatus with improved reliability.

The problem to be solved by the technical idea of the present invention is not limited to the problems mentioned above, and other problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problem, according to exemplary embodiments, a pixel array including a plurality of pixels is provided. Each of the plurality of pixels may include a photoelectric device formed on a substrate and generating electric charge from light; And a pixel circuit formed between the photoelectric device and the substrate and configured to output a digital signal value based on the amount of the generated charge, wherein the pixel circuit is formed in the substrate and the floating charge is stored Diffusion; A vertical pixel electrode connecting the floating diffusion and the photoelectric device and extending in a direction perpendicular to the substrate; An analog-to-digital converter configured to convert the potential of the floating diffusion into the digital signal value; And a memory device configured to store the digital signal value.

An image sensor according to exemplary embodiments includes a pixel array including pixels arranged in a matrix along a plurality of row lines and column lines, each of the pixels generating a charge proportional to the intensity of incident light. And a configured photoelectric device and a pixel circuit, wherein the pixel circuit comprises: a floating diffusion formed in a substrate and shorted to the photoelectric device to store the charge; A reset transistor configured to provide a reset potential to the floating diffusion during a reset period; An analog-to-digital converter configured to generate a digital reset value based on the reset potential in the reset period; And a memory device configured to store the digital reset value during the reset period.

An image sensor according to example embodiments includes: a pixel array including pixels arranged in a matrix along a plurality of row lines and column lines; A sensor circuit configured to drive the pixel array; And an image processor configured to control the sensor circuit and generate an image, wherein each of the pixels comprises: a photoelectric element configured to generate a charge proportional to the intensity of incident light; And a pixel circuit, wherein the pixel circuit comprises: a floating diffusion formed in a substrate and storing the charge generated by the photoelectric device; A vertical pixel electrode configured to connect the photoelectric device and the floating diffusion; A reset transistor configured to provide a reset potential to the floating diffusion during a reset period; A driving transistor configured to generate a signal potential according to the potential of the floating diffusion; An analog-to-digital converter configured to convert the signal potential into the digital signal value in a sampling period, and to generate a digital reset value based on the reset potential in the reset period; And a memory device configured to store the digital signal value in the sampling period and to store the digital reset value in the reset period.

According to the technical idea of the present invention, a digital signal representing a signal potential stored in a memory device included in a pixel is provided. It can be compared with a digital signal representing a reset voltage stored in the memory device in the previous frame period. Accordingly, since the digital signal representing the reset potential and the digital signal representing the signal potential contain the same reset noise component, the reset noise can be removed through the CDS in the digital region.

Fig. 1 is a block diagram illustrating an image sensor according to an exemplary embodiment.
2A and 2B are schematic circuit diagrams for describing a pixel included in an image sensor according to exemplary embodiments.
3 and 4 are schematic cross-sectional views for describing a pixel included in an image sensor according to exemplary embodiments.
5 to 8 are graphs for explaining an operation of an image sensor according to an exemplary embodiment.
9 is a block diagram illustrating a system including an image sensor according to some embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted. In the following drawings, the thickness or size of each layer is exaggerated and expressed for convenience and clarity of description, and accordingly, may be slightly different from the actual shape and ratio.

1 is a block diagram illustrating an image sensor 1 according to exemplary embodiments.

Referring to FIG. 1, an image sensor 1 according to exemplary embodiments may include a pixel array 10, a sensor circuit 20, and an image processor 30.

The pixel array 10 may include a plurality of row lines ROW1 to ROWM and a plurality of pixels PX11 to PXMN arranged along the plurality of column lines COL1 to COLN. The plurality of pixels PX11 to PXMN may be arranged to form a matrix. Each of the pixels PX11 to PXMN includes a photoelectric element PE that receives light to generate charge, and a pixel circuit PXC configured to generate digital signals DSO1 to DSON based on the generated charge amount. I can.

The sensor circuit 20 may include a row driver 21, a readout circuit 23, and a timing controller 25. The sensor circuit 20 may control the pixel array 10 according to a command transmitted from the image processor 30.

The row driver 21 may generate first to Mth control signals CTRL1 to CTRLM for driving the plurality of pixels PX11 to PXMN according to a command input by the timing controller 25. The first to Mth control signals CTRL may be transmitted to the pixels PX11 to PXMN through the plurality of row lines ROW1 to ROWM. For example, the first control signal CTRL1 may be transmitted to the pixels PX11 to PX1N connected to the first row line ROW1 through the first row line ROW1, and the second control signal CTRL2 May be transferred to the pixels PX21 to PX2N connected to the second row line ROW2 through the second row line ROW2. The pixels PX11 to PXMN may be driven in units of row lines according to the first to Mth control signals CTRL1 to CTRLM. The first to Mth control signals CTRL1 to CTRLM may include the selection signal SEL of FIGS. 2A and 2B, the reset signal RS, and the read signal RD of FIG. 7.

The read-out circuit 23 may read the first to Nth digital signals DSO1 to DSON from the pixels PX11 to PXMN selected by the row driver 21 among the pixels PX11 to PXMN. . The first to Nth digital signals DSO1 to DSON may be transmitted to the readout circuit 23 through the first to Nth column lines COL1 to COLN, respectively, in order. As described later, the first to Nth digital signals DSO1 to DSON may include a digital signal indicating a signal potential and a digital signal indicating a reset potential. The readout circuit 23 may perform correlated double sampling (CDS).

In the field of CMOS image sensor technology, CDS outputs an image signal from which noise is removed by calculating a difference between a reference potential (eg, a reset voltage of a pixel) and a signal potential (eg, a signal potential of a pixel sampled in a sampling period). It's technology. By performing CDS, the read-out circuit 23 can generate image data from which noise, such as common noise, has been removed.

The timing controller 25 may operate by a command input from the image processor 30. The image processor 30 may control the row driver 21 and the readout circuit 23 through the timing controller 25. The image processor 30 may construct an image based on image data output from the read-out circuit 23. The image configured by the image processor 30 may be output to a display device or the like or stored in a storage device such as a memory.

2A is a schematic circuit diagram of a pixel PX according to exemplary embodiments.

1 and 2A, the pixel PXa may include a photoelectric device PEa and a pixel circuit PXC.

According to example embodiments, the pixel PXa illustrated in FIG. 2A may have a circuit structure of each of the pixels PX11 to PXMN.

As light is incident from the outside, the photoelectric device PEa may generate charge proportional to the intensity of the external light. Charges generated by the incidence of light are referred to as photo charges. According to example embodiments, the photoelectric device PEa may use electrons as main charge carriers. In the embodiment of FIG. 2A, since electrons are used as main charge carriers, a ground voltage GND may be applied to one electrode (eg, an anode) of the photoelectric device PEa. The other electrode (eg, a cathode) of the photoelectric device PEa may be connected to the floating diffusion FD. Accordingly, photocharges generated by the photoelectric device PEa may be collected in the floating diffusion FD or may be output from the floating diffusion FD.

The pixel circuit PXC may include a reset transistor RX, a driving transistor DX, an analog-to-digital converter ADC, a memory element ME, a current source'I', and a switch element SW. A plurality of switch elements may be provided in proportion to the number of memory elements ME, or may be serial type switch elements. The pixel circuit may be driven by a reset signal RS and a selection signal SEL, which are control signals CTRL1 to CTRLN generated from the row driver 21.

Here, the ground voltage GND is a voltage of a node that is a reference for circuit analysis, and may be set to have a potential of 0V. By setting the ground voltage GND to 0V, the power voltage VDD, the reset signal RS, the selection signal SEL, the reset voltage, and the signal voltage may be defined.

The gate of the driving transistor DX may be connected to the floating diffusion FD. As photo charges accumulate in the floating diffusion FD, the potential of the floating diffusion FD may change. The driving transistor DX may be a source follower buffer amplifier operated by charges accumulated in the floating diffusion FD. The current source'I' may operate as a bias current sink.

The power voltage VDD may be applied to the first electrode (eg, the drain terminal) of the driving transistor DX. The second electrode (eg, source) of the driving transistor DX may be connected to the analog-to-digital converter ADC. Accordingly, the driving transistor DX may transfer the photo charge to the analog-to-digital converter ADC. Unlike FIG. 2A, in some embodiments, the driving transistor DX may be omitted. In this case, the floating diffusion (FD) can be directly connected to the analog-to-digital converter (ADC).

The driving transistor DX may output the pixel voltage VPIX to the second electrode (eg, a source). Here, the pixel voltage VPIX may be one of a signal potential or a reset potential indicating a potential of the floating diffusion FD determined according to an amount of photocharge generated by the photoelectric device PEa. The pixel voltage VPIX may be an analog signal.

Since electrons are generated as main charge carriers in the photoelectric device PEa, the power voltage VDD may be applied to the first electrode (eg, the drain terminal) of the reset transistor RX. The second electrode (eg, the source terminal) of the reset transistor RX may be connected to the floating diffusion FD. In the reset period, the reset transistor RX may provide a reset potential to the floating diffusion FD according to the reset signal RS output from the row driver 21. In the embodiment of FIG. 2A, the reset potential may be the power voltage VDD. Accordingly, immediately after the reset operation is performed, the potential of the floating diffusion FD may be substantially the same as the power voltage VDD (ie, the reset voltage).

Here, substantially the same as the power voltage VDD means that it is the same as the power voltage VDD within an error range in circuit operation. The potential of the reset floating diffusion FD may be different from the power voltage VDD by at least a reset noise. The reset noise may include, for example, flicker noise and thermal noise (ktc noise).

In the reset period, the reset voltage, which is the reset potential of the floating diffusion FD, may be transmitted to the analog-to-digital converter ADC via the driver transistor DX and the transistor SX. That is, in the reset period, the pixel voltage VPIX may be the reset voltage.

The analog-to-digital converter ADC may generate a digital signal DSO based on the pixel voltage VPIX. The digital signal may include a digital signal value obtained by digitizing the signal potential, and a digital reset value of the reset potential. Here, the signal potential may be a potential value of the floating diffusion FD according to the amount of charge generated by the photoelectric device PEa as described above.

Generating a digital signal is by comparing the ramp voltage and the pixel voltage (VPIX) changing with a predetermined slope, and counting the number of clocks during a period greater than (or during a smaller period) than the ramp voltage (VPIX). In the embodiment of Fig. 2A, the ramp voltage may be a voltage that decreases with time.

At least one of the digital signal value and the digital reset value may be stored in the memory device ME. The memory device ME may store a digital signal value and a digital reset value, respectively, or may store only a digital reset value.

The switch element SW may be connected between the memory element ME and the column line COL. At least one of the stored digital signal value and digital reset value may be read out by a readout signal of the readout circuit 23. Here, the read-out signal may be a selection signal SEL or a signal generated from the selection signal (eg, read signal RD of FIGS. 7 and 8 ). More specifically, the read-out signal may turn on the switch element SW, and accordingly, the digital signal stored in the memory element ME passes through the switch element SW and the column line COL, and the read-out circuit 23 ) Can be delivered. Here, the column line COL may be any one of the first to Nth column lines COL1 to COLN of FIG. 1.

According to example embodiments, each of a digital signal value and a digital reset value may be read from the memory device ME by a readout signal. According to other exemplary embodiments, each of the digital reset values may be read out from the memory device ME by a readout signal, and the digital signal values may be read out from the analog-to-digital converter ADC by a readout signal.

2B is a schematic circuit diagram of a pixel PX according to exemplary embodiments.

1 and 2B, the pixel PXb may include a photoelectric device PEb and a pixel circuit PXC.

For convenience of explanation, overlapping with those described with reference to FIG. 2A will be omitted, and differences will be mainly described.

According to example embodiments, the pixel PXb illustrated in FIG. 2B may have a circuit structure of each of the pixels PX11 to PXMN.

Unlike the photoelectric device Pea of FIG. 2A, the photoelectric device PEb of FIG. 2B may generate holes as main charge carriers. According to example embodiments, one electrode (eg, an anode) of the photoelectric device PEb may be connected to the floating diffusion FD. According to example embodiments, the first voltage may be applied to the other electrode (eg, a cathode) of the photoelectric device PEb. According to exemplary embodiments, the first voltage V1 may have a value of several volts, for example, about 3.0 V.

A reset voltage VRST having a value different from that of the power voltage VDD may be applied to the first electrode (eg, a drain terminal) of the reset transistor RX. In the reset period, the reset transistor RX may provide the reset voltage VRST to the floating diffusion FD according to the reset signal RS output from the row driver 21. Accordingly, the potential of the floating diffusion FD may be substantially the same as the power voltage VRST.

The analog-to-digital converter ADC may generate a digital signal value based on the pixel voltage VPIX. In the embodiment of FIG. 2B, the ramp voltage may be a voltage that increases with time.

According to example embodiments, the dark current characteristic of the pixel PXb may be improved by including the photoelectric device PEb using holes as main charge carriers.

3 is a schematic cross-sectional view illustrating a pixel PX according to exemplary embodiments. The pixel PX of FIG. 3 may correspond to any one of the pixels PXa and PXb of FIGS. 2A and 2B.

Referring to FIG. 3, a pixel PX may include a circuit unit 100 and a photoelectric device PE disposed on the circuit unit 100.

The circuit unit 100 may constitute the pixel circuit PXC of FIGS. 2A and 2B. The pixel PX may operate according to any one of the methods described with reference to FIGS. 2A and 2B. In addition, the photoelectric device PE may be any one of the photoelectric devices PEa and PEb of FIGS. 2A and 2B.

Here, a direction perpendicular to the upper surface of the substrate 101 (i.e., a normal direction) is defined as a first direction (Z direction), and two directions parallel to the upper surface and perpendicular to each other are in order, respectively, in the second and third directions ( X, Y direction). The first direction (Z direction) is alternatively also referred to as a vertical direction, and the second and third directions (X, Y direction) are also referred to as a horizontal direction.

The substrate 101 may be a semiconductor substrate. The substrate 101 may be, for example, an SOI substrate. The substrate 101 is a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or selective epitaxial growth. It may be a substrate of an epitaxial thin film obtained by performing (selective epitaxial growth: SEG). The substrate 101 includes at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof can do. The substrate 101 may be doped with a P conductivity type dopant.

Source/drain regions SD may be formed in the substrate 101. The source/drain regions SD may be doped by, for example, an N conductivity type dopant. Any one of the source/drain regions SD may correspond to the floating diffusion FD of FIG. 2. One of the source/drain regions SD corresponding to the floating diffusion FD of FIG. 2 may contact the vertical pixel electrode 125.

A plurality of gate electrodes GE may be formed on the substrate 101. The gate electrodes GE may include a gate conductive layer and a gate insulating layer disposed under the electrode conductive layer. According to example embodiments, the gate conductive layer may include a conductive material such as a metal, and the gate insulating layer may include an insulating material such as silicon oxide. The gate electrodes GE and the source/drain regions SD may constitute the first and second transistors T1 and T2.

The first transistor T1 may correspond to the reset transistor RX of FIG. 2. The second transistor T2 may be at least one of a transistor constituting the analog-to-digital converter ADC of FIG. 2, a driving transistor DX, and.

The insulating layer 110 may be disposed on the substrate 101. The insulating layer 110 may cover the gate electrodes GE. The insulating layer 110 may include an insulating material such as SiO ₂ , SiN, Al ₂ O ₃ , HfO _x (x is a rational number). The insulating layer 110 may be formed by integrating a plurality of insulating material layers formed at different levels.

A conductive wiring 120 may be formed in the insulating layer 110. The conductive wiring 120 may include conductive vias 121, conductive patterns 123, and vertical pixel electrodes 125. The structure in which the conductive wiring 120 including a plurality of conductive layers disposed at different levels is covered by the insulating layer 110 is also referred to as a metal-insulator-metal (MIM) structure, and is referred to as a BEOL (Back End of Line) process.

The conductive patterns 123 may be disposed in plural at different levels, and may extend in a horizontal direction. The conductive vias 121 may extend in a vertical direction (eg, a first direction (Z direction)). The conductive vias 121 may connect conductive patterns 123 formed at different levels to each other. The conductive vias 121 may connect the conductive patterns 123 to some of the substrate 101, such as the source and drain region S/D.

The photoelectric device PE may be disposed on the insulating layer 110. The photoelectric device PE may make contact with the lower electrode 211 and the upper electrode 215. The lower and upper electrodes 211 and 215 may have a wide horizontal cross-sectional area, and accordingly, the photoelectric device PE may be The vertical pixel electrode 125 may extend in a vertical direction (eg, a first direction (Z direction)) The vertical pixel electrode 125 may have a lower electrode 211 and a lower electrode of FIG. It may be connected to the source/drain regions SD corresponding to the floating diffusion FD, thereby forming an electrical path for the photoelectric charge generated in the photoelectric device PE to move to the floating diffusion FD. have.

The memory device ME may be disposed on the substrate 101. The memory device ME may be provided in a BEOL process. According to example embodiments, the memory device ME may be disposed at the same level as at least some of the conductive patterns 123. According to example embodiments, the memory device ME may overlap at least a portion of the vertical pixel electrode 125.

According to example embodiments, the memory device ME may be a dynamic random access memory (DRAM) device. According to other exemplary embodiments, the memory device ME may be any one of a phase change memory (PRAM), a spin transfer torque-magnetic RAM (STT-MRAM), and a resistive RAM (ReRAM). have.

The photoelectric device PE may be disposed on the insulating layer 110. The photoelectric elements PE are disposed at different vertical levels from the circuit unit 100 and may vertically overlap each other. The photoelectric device PE may be a photoelectric conversion device other than a semiconductor-based photoelectric device. According to exemplary embodiments, the photoelectric device PE may be any one of a quantum dot photodiode, an organic photoconductive film, and a perovskite photodiode. The photoelectric device PE may generate photoelectrons by using light in the visible and infrared bands.

The upper electrode 215 may provide a voltage for operating the photoelectric device PE, such as a ground voltage GND of FIG. 2A or a first voltage V1 of FIG. 2B. The lower and upper electrodes 211 and 215 may include a transparent conductive material such as ITO, IZO, ZnO, or SnO ₂ .

The protective layer 220 on the upper electrode 215 may protect the upper electrode 215 and the photoelectric device PE.

The color filter 230 may be a band pass filter that passes only light of a partial band among the light incident on each pixel PX. Accordingly, the photoelectric device PE may receive light having a wavelength of the pass band of the color filter 230. The adjacent pixels PX may include color filters 230 having different passbands or color filters 230 having substantially the same passband.

The microlens 240 is disposed on the color filter, and condenses external light to widen the light-receiving angle of each pixel PX.

4 is a schematic cross-sectional view illustrating a pixel PX' according to exemplary embodiments. The pixel PX' of FIG. 4 may correspond to any one of the pixels PXa and PXb of FIGS. 2A and 2B.

For convenience of description, overlapping with those described with reference to FIG. 3 will be omitted, and differences will be mainly described.

Referring to FIG. 4, a pixel PX' may include a circuit unit 100 and a photoelectric device PE disposed on the circuit unit 100 ′.

The circuit unit 100 ′ may constitute the pixel circuit PXC of FIGS. 2A and 2B. The pixel PX' may operate according to any one of the methods described with reference to FIGS. 2A and 2B.

Referring to FIG. 4, the memory device may be formed at a lower vertical level than the conductive patterns 123. According to example embodiments, the memory device may be a static RAM (SRAM) device. According to example embodiments, the memory device may be configured by a plurality of second transistors T2. Accordingly, the memory device may be disposed at the same level as the first transistor T1.

5 are graphs for explaining the operation of the image sensor 1 (refer to FIG. 1) including the pixel PXa of FIG. 2A.

More specifically, FIG. 5 illustrates first to M-th selection signals SEL1 to SLM, which are control signals CTRL (see FIG. 1) input to first to M-th row lines (ROW1 to ROWM, see FIG. 1). , First to M-th reset signals RS1 to RSM and first to M-th pixel voltages VPX1 to VPXM (refer to FIG. 2A) according thereto.

The first to Mth row periods R1 to RM may be time intervals that sequentially arrive. Here, the first to Mth row periods R1 to RM may be a time period in which the pixels PX11 to PXMN connected to the first to Mth row lines ROW1 to ROM are driven in order, respectively.

More specifically, in the first to Mth row periods R1 to RM, i) the photoelectric device PE included in the pixels PX11 to PXMN connected to the first to Mth row lines ROW1 to ROM Generates photocharges, ii) corresponding driving transistors DX output first to Mth pixel voltages VPIX1 to VPIXM using the generated photocharges, and iii) corresponding analog- After the digital converter (ADC) generates a digital signal based on the first to M-th pixel voltages (VPIX1 to VPIXM) iv) each corresponding memory device (ME) stores the digital signal v) the memory The digital signal stored in the device ME may be read through first to Nth row lines ROW1 to ROWN.

For example, in the first row period R1, i) the driving transistor may generate the first row by using charges generated from the photoelectric elements PE included in the pixels PX11 to PX1N connected to the first row line ROW1. A pixel voltage VPIX1 is generated, ii) an analog-to-digital converter generates a digital signal based on the first pixel voltage VPIX1, iii) stores the digital signal in the memory device ME, and iv ) It may be a time period in which the digital signal stored in the memory device ME is read through first to Nth row lines ROW1 to ROWN. In the second row period R2 that follows the first row period R1, similar operations may be performed on the pixels PX21 to PX2N connected to the second row line ROW2.

The first and second frame periods FR1 and FR2 may include the same number of row periods as the number of row lines, respectively, included in the image sensor 1 of FIG. 1. The first and second frame periods FR1 and FR2 may each include first to Mth row periods R1 to RM. Each of the first and second frame periods FR1 and FR2 is a time period taken to sequentially drive all of the first to Mth row lines ROW1 to ROWM.

1, 2A, and 5, pixels PX11-PXMN connected to first to Mth row lines ROW1 to ROWM in order, respectively, in first to Mth row periods R1 to RM Can be chosen.

Each of the first to Mth row periods R1 to RM may include a sampling period SAM for detecting a signal voltage and a reset period RST for detecting a reset voltage. In FIG. 5, the sampling interval SAM is shown to be longer than the reset interval RST, but is not limited thereto.

After the first row period R1 of the first frame period FR1 starts, the first pixel voltage VPIX1 of the pixels PX11 to PX1N connected to the first row line ROW1 at a time point t1_1 is applied to the driving transistor ( DX) can be output to an analog-to-digital converter (ADC). The first pixel voltage VPIX1 output at time t1_1 may be a signal potential of the floating diffusion FD that is proportional to the amount of photocharge generated by the photoelectric device PE. The analog-to-digital converter (ADC) can generate a digital signal value based on the signal potential. The generated digital signal value may be stored in the memory device ME.

At time t1_2 that arrives after time t1_1, the floating diffusion FD of the pixels PX11 to PX1N connected to the first row line ROW1 may be reset. At time t1_2, the first pixel voltage VPIX1 may be output to the analog-to-digital converter ADC through the driving transistor DX. The first pixel voltage VPIX1 output at time t1_2 may be a reset potential. The analog-to-digital converter (ADC) may generate a digital reset value based on the reset voltage. The generated digital reset value may be stored in the memory device ME.

In the pixel PXa of the exemplary embodiments, the floating diffusion FD and the photoelectric element PE are directly connected so that a separate transfer transistor is not disposed therebetween. Accordingly, a digital signal value may be first generated in each of the first and second frame periods FR1 and FR2, and then a digital reset value may be generated.

At time t2_1 of the first row period R1 of the second frame period FR2, the digital signal values of the pixels PX11 to PX1N connected to the first row line ROW1 in the same manner as in t1_1 are stored in the memory device. (ME) can be stored.

At time t2_2 of the first row period R1 of the second frame period FR2, the digital reset values of the pixels PX11 to PX1N connected to the first row line ROW1 in the same manner as in t1_2 are set to the memory device. (ME) can be stored.

Digital signal values of the pixels PX21 to PX2N connected to the second row line ROW2 may be stored in the memory device ME at a time point t1_3 and a time point t2_3. Digital signal values of the pixels PX21 to PX2N connected to the second row line ROW2 may be stored in the memory device ME at a time point t1_4 and a time point t2_4.

When performing CDS using digital signal values and digital reset values included in the same frame period, for example, when performing CDS using digital signal values stored at time t1_1 and digital reset values stored at time t1_2, digital Different reset noise components may be included in the signal value and the digital reset value. During the reset operation, KTC noise may occur due to the movement of unwanted charges. Due to this KTC noise, reset potential values may be different for each frame period. Accordingly, there is a problem in that noise (eg, reset noise) cannot be removed despite CDS being performed.

According to some embodiments, the read-out circuit 23 may calculate a difference between a digital signal value generated in different frame periods and a digital reset value. More specifically, the read-out circuit 23 detects a digital signal value stored in the memory element ME at a time t2_1 and a digital reset stored in the memory element ME detected from the first pixels PX11-PX1N at a time t1_2. You can calculate the difference in values.

At this time, the digital reset value stored at time t1_2 is the potential of the floating diffusion before charge accumulation of the digital signal value stored at t2_1.By comparing the digital reset value stored at time t1_2 with the digital signal value stored at t2_1, the reset noise is removed. Ture) CDS can be performed. The TCDS can be performed in a digital domain.

6 are graphs for explaining the operation of the image sensor 1 (refer to FIG. 1) including the pixel PXb of FIG. 2B.

For convenience of description, overlapping with those described with reference to FIG. 5 will be omitted, and differences will be mainly described.

The operation of the image sensor according to the embodiment shown in FIG. 6 may be similar to the operation of the image sensor according to the embodiment shown in FIG. 5. However, the embodiment of FIG. 6 relates to the pixel PXb of FIG. 2B, and more specifically, relates to a case in which holes are used as main charge carriers. Accordingly, the increase or decrease of the signal voltage VPIX may be in the opposite direction to the embodiment shown in FIG. 5.

1, 2B, and 6, the read-out circuit 23 includes a digital signal value stored in the memory element ME at a time 2_1 of a second frame period FR2 and a memory at a time 1_2 of the first frame period. The difference between the digital reset values stored in the device ME can be calculated. Accordingly, TCDS in the digital domain can be performed.

7 is a schematic graph for describing an operation of an image sensor according to some embodiments.

For convenience of description, descriptions with reference to FIG. 5 will be omitted, and differences will be mainly described.

1, 2A, and 7, the first and second frame periods FR1 and FR2 may include a sensing period SEN and a read period RO unlike FIG. 5. The sensing period SEN may be a period in which data (eg, digital signal values and digital reset values) for an image is generated using light incident on the pixels PX11 to PXMN. The read period RO may be a period in which data (eg, digital signal values and digital reset values) of images stored in the pixels PX11 to PXMN are read.

The pixels PX11 to PXMN connected to the first to Mth row lines ROW1 to ROWM may simultaneously sense external light.

According to some embodiments, all of the pixels PX11 to PXMN substantially simultaneously sense external light, so that distortion due to movement of an external light source or subject may be reduced. Each of the pixels PX11 to PXMN at a time point t1_1 and a time point t2_1 may output a pixel voltage VPIX1 according to a photo charge generated by the photoelectric device PEa, and generate and store a digital signal value based on this. Each of the pixels PX11 to PXMN at time t1_2 and time t2_2 may output a pixel voltage VPIX1 according to the execution of the reset operation, and may generate and store a digital reset value based on this.

Data (eg, digital signal values and digital reset values) stored in each of the pixels PX11 to PXMN connected to the first to Mth row lines ROW1 to ROWM are sequentially based on the read signal RD. Can be read as. For example, after data (eg, digital signal values and digital reset values) of images stored in the pixels PX11 to PX1N connected to the first row lines ROW1 are read, for example, the second row lines ROW2 Data (eg, digital signal values and digital reset values) stored in the pixels PX21 to PX2N connected to) may be read.

8 is a schematic graph for describing an operation of an image sensor according to some embodiments.

For convenience of explanation, descriptions with reference to FIGS. 6 to 8 are omitted, and differences will be mainly described.

The operation of the image sensor according to the embodiments shown in FIG. 8 may be similar to the operation of the image sensor according to the embodiment shown in FIG. 7. However, the embodiment of FIG. 8 relates to the pixel PXb of FIG. 2B, and more specifically, relates to a case in which holes are used as main charge carriers. Accordingly, the increase or decrease of the signal voltage VPIX may be in the opposite direction to the embodiment shown in FIG. 5.

Fig. 9 is a block diagram showing a system 1000 including an image sensor 1300 according to an exemplary embodiment.

Referring to FIG. 9, the system 1000 may be any one of a computing system requiring image data, a camera system, a scanner, a vehicle navigation system, a video phone, a security system, or a motion detection system.

As shown in FIG. 9, the system 1000 includes a central processing unit (or processor) 1100, a nonvolatile memory 1200, an image sensor 1300, an input/output device 1400, and a RAM 1500. I can. The central processing unit 1100 may communicate with the nonvolatile memory 1200, the image sensor 1300, the input/output device 1400, and the RAM 1500 through the bus 1600. The image sensor 1300 may be implemented as an independent semiconductor chip, or combined with the central processing unit 1100 to be implemented as a single semiconductor chip. The image sensor 1300 may be implemented according to the embodiments described above with reference to FIGS. 1 to 6.

The central processing unit 1100 may control the system 1000 and may exchange data with other components through the bus 1600. For example, the central processing unit 1100 may receive data generated by the image sensor 1300 according to an exemplary embodiment of the present invention. The nonvolatile memory 1200 is a memory that retains data stored even when power is turned off, and may store, for example, data generated by the image sensor 1300 or data processed by the generated data. The RAM 1500 may function as a data memory of the central processing unit 1100 and may be a volatile memory device. The input/output device 1400 may receive a command from a user of the system 1000 or may output an image and/or audio to the user.

In the above, embodiments of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features. You can understand that there is. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting.

Claims (10)

As a pixel array including a plurality of pixels,
Each of the plurality of pixels,
A photoelectric element formed over the substrate and generating electric charge from light; And
A pixel circuit formed between the photoelectric element and the substrate and configured to output a digital signal value based on the amount of the generated charge,
The pixel circuit,
A floating diffusion formed in the substrate and storing the electric charge;
A vertical pixel electrode connecting the floating diffusion and the photoelectric device and extending in a direction perpendicular to the substrate;
An analog-to-digital converter configured to convert the potential of the floating diffusion into the digital signal value; And
And a memory element configured to store the digital signal value. The method of claim 1,
Wherein the vertical pixel electrode comprises a metal material. The method of claim 1,
And the memory device is disposed at the same level as at least a portion of the vertical pixel electrode. The method of claim 1,
The pixel circuit,
Further comprising a reset transistor configured to use the floating diffusion as one electrode and to provide a reset potential to the floating diffusion in a reset period,
Wherein the memory device is formed at the same level as the reset transistor. The method of claim 1,
The pixel circuit,
Further comprising a reset transistor configured to use the floating diffusion as one electrode and to provide a reset potential to the floating diffusion in a reset period,
And in the reset period, the analog-to-digital converter is configured to convert the reset potential into a digital reset value. The method of claim 5,
Wherein the memory device is configured to store a value corresponding to the digital reset value in the reset period. Including a pixel array including pixels arranged in a matrix along a plurality of row lines and column lines,
Each of the pixels,
A photoelectric device and a pixel circuit configured to generate a charge proportional to the intensity of the incident light,
The pixel circuit,
A floating diffusion formed in a substrate and shorted to the photoelectric device to store the charge;
A reset transistor configured to provide a reset potential to the floating diffusion during a reset period;
An analog-to-digital converter configured to generate a digital reset value based on the reset potential in the reset period; And
And a memory device configured to store the digital reset value during the reset period. The method of claim 7,
The pixel circuit,
Further comprising a driving transistor configured to generate a signal potential according to the potential of the floating diffusion,
The analog-to-digital converter is an image sensor, characterized in that configured to convert the signal potential into a digital signal value in a sampling period. The method of claim 8,
And the memory element is configured to store a value of the digital signal value in the sampling period. The method of claim 9,
A row driver configured to drive all of the row lines during each of a first frame period and a second frame period following the first frame period; And
And a readout circuit configured to read the digital reset value and the digital signal value from the memory device.

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