CN208848330U - A kind of double-core POS machine safety chip - Google Patents
A kind of double-core POS machine safety chip Download PDFInfo
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- CN208848330U CN208848330U CN201821676585.9U CN201821676585U CN208848330U CN 208848330 U CN208848330 U CN 208848330U CN 201821676585 U CN201821676585 U CN 201821676585U CN 208848330 U CN208848330 U CN 208848330U
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Abstract
The utility model discloses a kind of double-core POS machine safety chips, and comprising SP system, AP system, bus matrix and double-core communication, the SP system, AP system and double-core communication are connect with bus matrix by interface respectively；Wherein, the AP system includes AP processor module, first memory module, second memory module, the first access controller, USB interface, multimedia card interface, universal communication interface, external memory controller interface, four line peripheral hardware serial line interfaces；Under the premise of almost without chip area is increased, the R&D cycle is shortened, it is at low cost and flexible and changeable；In the operation of no security application, common double-core chip can be treated as；In security application operation, can realize in the physical environment of an autonomous closure to the completely isolated of confidential data；Chip processing capabilities and security protection are largely improved, can be adapted for the application scenarios of a variety of different secure contexts.
Description
Technical field
The utility model belongs to POS machine safety chip field more particularly to a kind of double-core POS machine safety chip.
Background technique
With the explosive growth of smart phone and Internet of Things, more and more safety chips are set in the terminal of various fields
It is standby to be above widely used, as mobile payment field, intelligent transportation system, public affair government affairs field, fail-safe computer field, safety are logical
Letter field, internet of things field etc..Safety chip has the advantages that incomparable and irreplaceable at the aspect that ensures information safety
Effect.Just because of safety chip is so important, also emerge one after another for the attack technology of safety chip；The peace of safety chip itself
Full property design also becomes more and more important, and the research and application to this part have important practical significance.
In current information security application, the chip with security coprocessor scheme is had been widely adopted.However safety
Coprocessor is substantially for certain concrete application the hardware module of design one realization specific function, function is simple,
There is no flexibility.And the design of the hardware module of specific function is entirely by hardware realization, it is desirable that higher, design itself is got up more multiple
It is miscellaneous, the design cycle is longer, area is also larger.
In more complicated financial occasion, such as POS machine payment technical field, Yao Shixian be not merely data encryption and decryption.
From the card data protection swiped the card at the beginning, to the protection of code keyboard, then the display of liquid crystal interface is arrived, each link will consider
To the protection of data.And chip itself is also required to attack protection module and confidential data protection module (encounters attack and wants removing machine
Ciphertext data).It is unpractical that all above security functions will be fully achieved by hardware entirely by the method for coprocessor.Mesh
Preceding POS machine chip on the market is all that monokaryon is realized, mainly removes confidential data by monitoring whether to encounter attack.This
Text on this basis, is designed, so that confidential data operates in the environment completely isolated with practical application and works as by special double-core
In.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of double-core POS machine safety for the deficiency of background technique
Chip largely improves chip processing capabilities and security protection, can be adapted for a variety of different secure contexts
Application scenarios.
The utility model uses following technical scheme to solve above-mentioned technical problem:
A kind of double-core POS machine safety chip includes SP system, AP system, bus matrix and double-core communication, the SP system
System, AP system and double-core communication are connect with bus matrix by interface respectively；
Wherein, the AP system is deposited comprising AP processor module, first memory module, second memory module, first
Take controller, USB interface, multimedia card interface, universal communication interface, external memory controller interface, four line peripheral hardwares serial
Interface；It is the AP processor module, first memory module, second memory module, the first access controller, USB interface, more
Media card interface, universal communication interface, external memory controller interface, four line peripheral hardware serial line interfaces connect with bus matrix respectively
It connects；
SP system includes SP safe processor, third memory, the second access controller, the 4th memory and safeguard protection
Module；SP safe processor, third memory, the second access controller, the 4th memory and security protection module are respectively and always
Wire matrix connection；
Double-core communication module includes double-core communication protocol module and double-core communication buffer module；The double-core communication protocol mould
Block and double-core communication buffer module are connect with bus matrix respectively.
As a kind of further preferred scheme of double-core POS machine safety chip of the utility model, the AP system and SP system
System follows double-core communication protocol, passes through the transmission of data between the timesharing implementing reading and writing double-core to double-core communication buffer module.
As a kind of further preferred scheme of double-core POS machine safety chip of the utility model, bus matrix is to pass through piece
Upper bus follows equipment and is connected, and the AMBA agreement or opencores of ARM company can be used in on-chip bus agreement
The avalon agreement of altera can also be used in wishbone bus protocol.
As a kind of further preferred scheme of double-core POS machine safety chip of the utility model, the double-core communication protocol
One group of SP interrupt register, including interrupt identification bit register are equipped in module, interruption sets 1 register and interrupts clear 0 register.
As a kind of further preferred scheme of double-core POS machine safety chip of the utility model, the double-core communication protocol
Module includes a mutual exclusion register
As a kind of further preferred scheme of double-core POS machine safety chip of the utility model, the multimedia card interface
Using eMMC interface.
As a kind of further preferred scheme of double-core POS machine safety chip of the utility model, the four lines peripheral hardware is serial
The chip model of interface is QSPI.
The utility model compared with the prior art by using the above technical solution, has following technical effect that
The utility model shortens the R&D cycle under the premise of almost without chip area is increased, at low cost and flexible
It is changeable；In the operation of no security application, common double-core chip can be treated as；It, can be at one solely in security application operation
Closed physical environment is found to realize to the completely isolated of confidential data；Largely improve chip processing capabilities and safety
Protection, can be adapted for the application scenarios of a variety of different secure contexts.
Detailed description of the invention
Fig. 1 is the structure principle chart of the utility model double-core POS machine safety chip；
Fig. 2 is the structure principle chart of the utility model AP system；
Fig. 3 is the structure principle chart of the utility model SP system；
Fig. 4 is the structure principle chart of the utility model double-core communication module.
Specific embodiment
The technical solution of the utility model is described in further detail with reference to the accompanying drawing:
A kind of double-core POS machine safety chip, as shown in Figure 1, communicated comprising SP system, AP system, bus matrix and double-core,
The SP system, AP system and double-core communication are connect with bus matrix by interface respectively；
Wherein, as shown in Fig. 2, the AP system includes AP processor module, first memory module, second memory mould
Block, the first access controller, USB interface, multimedia card interface, universal communication interface, external memory controller interface, four lines
Peripheral hardware serial line interface；The AP processor module, first memory module, second memory module, the first access controller,
USB interface, multimedia card interface, universal communication interface, external memory controller interface, four line peripheral hardware serial line interfaces respectively with
Bus matrix connection；
As shown in figure 3, SP system includes SP safe processor, third memory, the second access controller, the 4th memory
And security protection module；SP safe processor, third memory, the second access controller, the 4th memory and safeguard protection mould
Block is connect with bus matrix respectively；
As shown in figure 4, double-core communication module includes double-core communication protocol module and double-core communication buffer module；The double-core
Communication protocol module and double-core communication buffer module are connect with bus matrix respectively
Wherein, AP system mainly include application processor (AP), using Static RAM (SRAM-AP), using depositing
Reservoir, using direct memory access controller (DMA-AP), USB interface, embedded multi-media card interface (eMMC interface), general
The modules such as communication interface, external memory controller interface (EMI), four line peripheral hardware serial line interfaces (QSPI).SP system is mainly wrapped
Include safe processor (SP), Secure static random access memory (SRAM-SP), safe direct memory access controller (DMA-SP),
The modules such as safe storage and security protection module.Double-core communication module includes double-core communication protocol module and double-core communication buffer
Module.
Safe storage and application memory can be ROM, OTP, Flash or EEPROM, be also possible to above-mentioned 4 kinds with
Meaning mixing.
AP system and SP system follow double-core communication protocol, double by the timesharing implementing reading and writing to double-core communication buffer module
The high efficiency of transmission of data between core.
Derived from the special designing of bus matrix, SP can possess the power of access any module of AP system according to actual needs
Limit, and AP can not access any module of SP system.In this way, realizing the closed SP system completely isolated with AP system.
All safety operations are completed by SP system, AP system only needs to send corresponding data and operation by double-core communication protocol
Instruction, SP system receive the data and operational order, result are returned to AP system by double-core communication protocol after execution.
Bus matrix: each unit in chip can be referred to as equipment (IP), and equipment can be divided into main equipment or from setting
It is standby.Main equipment is connected by on-chip bus with bus matrix, and bus matrix is also to follow equipment by on-chip bus to be connected.
On-chip bus agreement can be the AMBA agreement of ARM company or the wishbone bus protocol of opencores, be also possible to
The avalon agreement of altera, is also possible to other similar bus protocol.
Main equipment on bus matrix can be SP, AP, overall situation DMA, be also possible to the interface module containing built-in DMA function
(such as USB, EMMC, WiFi, bluetooth)；It can be memory from equipment, SRAM, external storage interface, security protection module, be total to
With access modules etc., can be split more to refine according to application demand from equipment.Main equipment and number from equipment can roots
It is increased or decreased according to practical application scene, corresponding bus matrix also will and then change.Each host device interface and each from setting
There is access between standby interface, can be designed to bridge joint (connection) or disconnects.Bridge joint represents the main equipment at bridge joint both ends and from setting
Standby access is connection, and main equipment is accessible from equipment；Disconnection then represents main equipment can not access slave.
SP passes through bus matrix and SRAM-SP, safe storage, SRAM-AP, application memory, safety as main equipment
Protection module etc. is connected from equipment；AP is also used as main equipment to connect by bus matrix and SRAM-AP, application memory etc. from equipment
It connects.In this way, SP is able to access that application system module, and AP can not access safety system module.In this way, disconnecting AP and secure storage
The connection relationship of device, SRAM-SP, safety protection module stops access of the AP to security system, forms a completely enclosed peace
The confidential data of security protection module and its inside can not be accessed in total system, i.e. application developer completely.
The interface module of remaining built-in DMA function can carry out differentiation configuration according to application demand and (all stay in Fig. 2
It is empty), it is not unfolded specifically herein.
Double-core communication: SP system and AP system are realized by double-core communication protocol module to double-core communication buffer module
Time-sharing control, ensure double-core between data secure interactive.
Double-core communication protocol module: there are one group of SP interrupt register, including interrupt flag bit in double-core communication protocol module
Register, interruption set 1 register and interrupt clear 0 register.It is similar with interrupting system, as long as having in SP interrupt identification bit register
One position 1, then can generate interrupt requests, and SP completes the interrupt requests by identification interrupt flag bit；Therefore, as long as the past SP of AP
Corresponding value (this value represents a certain specific tasks that AP and SP has been appointed) is written in interrupt flag bit register, and SP is just
It can complete the specific tasks of value meaning.Conversely, similarly there are one group of AP interrupt registers, as long as the past AP interrupt flag bit of SP
Corresponding value (this value represents a certain specific tasks that AP and SP has been appointed) is written in register, and AP can complete the value
Signified specific tasks.
Double-core communication buffer timesharing read-write:
Double-core communication protocol module includes a mutual exclusion register.Before operating double-core communication buffer such as AP, should first it read
Mutual exclusion register-bit is taken, such as reads 1, then it represents that has permission and double-core communication buffer is written and read；0 is such as read, indicates SP
Operating double-core communication buffer, (SP can carry out write operation, mutual exclusion to mutual exclusion register-bit after operation double-core communication buffer is complete
1) value of register-bit is that AP should then be waited and be inquired, and can be operated to double-core communication buffer until reading 1 side.Instead
It,.Before operating double-core communication buffer such as SP, mutual exclusion register-bit should be first read, such as reads 1, then it represents that have the right
Limit is written and read double-core communication buffer；0 is such as read, expression AP is operating double-core communication buffer, and (AP is logical in operation double-core
After letter has cached, write operation can be carried out to mutual exclusion register-bit, 1) value of mutual exclusion register-bit is that SP should then be waited and be looked into
It askes, double-core communication buffer can be operated until reading 1 side.
The realization of double-core communication buffer:
SP system and AP system follow the agreement of the above double-core communication protocol jointly, realize the timesharing to double-core communication buffer
Read-write；SP and AP can access SRAM-AP, therefore, can directly specify certain section of section to lead to for double-core in SRAM-AP by SP
Letter caching, peopleware need to do this section of section additional definition and constraint, avoid that maloperation occurs.Double-core communication buffer
It can be one piece of SRAM being implemented separately with hardware capability, this block SRAM is communicated only for double-core and used, and can completely avoid maloperation.
Double-core communication functions: SP system provide all power functions so as to AP system communication.AP developer passes through
Double-core communication buffer is written in the data for needing to input by double-core communication function, then corresponding toward the write-in of SP interrupt flag bit register
Value (representing corresponding mission function), such SP i.e. receive corresponding interruption, be carried out the task and finally data knot
Fruit writes back to double-core communication buffer, and then analog value (representing task execution to finish) is written toward AP interrupt flag bit register in SP,
Inform AP system.Likewise, SP can also actively initiate double-core communication, as SP system detection to safety protection module has data defeated
Enter, then corresponding demand data can be written to double-core communication buffer, then corresponding value is written toward AP interrupt flag bit register
(representing corresponding mission function)；AP in this way is received by corresponding interruption, gets the data that SP system transmits.It is all double
Communication between core all has to comply with power function set provided by SP system, exceeds the set, and SP system will not be taken the post as
What response.
Function call interface is defined by SP and is provided, many program codes can be completed with ROM by doing so, and be saved
FLASH cost, finally saves chip cost.
The application solutions of POS machine: safety protection module includes following module: encryption/decryption module, data protection module, physics
Security module, code keyboard module, bank's card module, LCD MODULE.These modules can be according to practical security application need
It asks to add or reduce.Security module can be hung on bus matrix by bus as shown in Figure 2, can also be direct by bus
It hangs on safe CPU；All safety for information about or the module of financial payment can all be blended in safety protection module.
Encryption/decryption module, including but not limited to DES/3DES, AES, HASH, ECC, RSA, the close scheduling algorithm of state, for completing
The encryption and decryption of confidential information is handled.Data protection unit is made of nonvolatile memory, supports quickly to remove function, for protecting
Important safety data are deposited, and quickly remove sensitive data when data are under attack.Physical security unit is visited by various physical quantitys
Unit composition is surveyed, for defending various voltages, electric current, capacitor, temperature, the physical attacks of frequency type, bank's card interface is used for
Support the reading data of bank card, code keyboard module is for the protection to Password Input data.
AP can choose the low-power consumption series RISC CPU of common in the market ARM or MIPS, in order to client development and
Marketing.SP by company's independent research, artificially forms a more closed exploitation environment completely.In this way, confidential data exists
When product export, burning is carried out by the hardware corridor and burning agreement of autonomous Design, and after reading confirmation burning success,
The burning channel is fallen by fuse opening closing, has prevented the possibility that burning channel discloses secrets to data.AP system and SP system
Data interaction there was only double-core communication buffer, the offer of SP system carries out corresponding operating with confidential data and exports the function of result,
The function directly read to confidential data is not provided.In this way, AP developer does not have any physical channel to read machine
Ciphertext data, how outside world personnel pass through the loophole or software bug of AP system again, and can not obtain confidential data, from
And realize real physical isolation.
POS machine secure payment
The safe POS machine chip of double-core of the present invention, secure payment process are as follows:
(1) user carries out movement of swiping the card, bank's card interface that equipment passes through security system in double-core chip by POS terminal
The bank card information of module reading user.
(2) user is directly connected to the cryptographic key of security system by information, keys such as key-press input passwords in POS machine
Disk module.Relevant information is shown on liquid crystal by the LCD Controlling interface in security system, carries out certain information with user
Interaction, such as deletion, backspace, confirmation.
(3) security system encrypts above- mentioned information by encryption/decryption module, then passes through the data encrypted double
Core communication function is transferred to application system, and application system is again sent out the information encrypted by communication interface (such as serial ports, USB)
Give payment backstage.
(4) after payment is background processed, then the check results of encryption information is passed through into communications interface transmission and return POS terminal,
Check results are sent to security system, and the letter of the double-core communication protocol by appointing by double-core communication function by application system
Number, final transaction results are shown by the liquid crystal interface in security system.
Application system is docked by communication interface with bank, only carries out handling work, safety to encrypted good information
The all working of aspect is completed by safe kernel entirely, can not be formed attack using personnel and can not be obtained confidential data.
The data protection of POS machine
Various attack resistance designs are carried out using the correlation function of physical security unit in security system.Physical security unit is suitable
When detect environmental change, it is ensured that the important sensitive information in the protection location that clears data after machine is under attack, in order to avoid
It is stolen by attacker.The work of data protection remains security system completion, touchless using personnel.
Claims (7)
1. a kind of double-core POS machine safety chip, it is characterised in that: it is communicated comprising SP system, AP system, bus matrix and double-core,
The SP system, AP system and double-core communication are connect with bus matrix by interface respectively；
Wherein, the AP system includes AP processor module, first memory module, second memory module, the first access control
Device processed, USB interface, multimedia card interface, universal communication interface, external memory controller interface, four line peripheral hardware serial line interfaces；
The AP processor module, first memory module, second memory module, the first access controller, USB interface, multimedia
Card interface, universal communication interface, external memory controller interface, four line peripheral hardware serial line interfaces are connect with bus matrix respectively；
SP system includes SP safe processor, third memory, the second access controller, the 4th memory and safeguard protection mould
Block；SP safe processor, third memory, the second access controller, the 4th memory and security protection module respectively with bus
Matrix connection；
Double-core communication module includes double-core communication protocol module and double-core communication buffer module；The double-core communication protocol module and
Double-core communication buffer module is connect with bus matrix respectively.
2. a kind of double-core POS machine safety chip according to claim 1, it is characterised in that: the AP system and SP system
Double-core communication protocol is followed, the transmission of data between the timesharing implementing reading and writing double-core to double-core communication buffer module is passed through.
3. a kind of double-core POS machine safety chip according to claim 1, it is characterised in that: bus matrix is to pass through on piece
Bus follows equipment and is connected, and the AMBA agreement of ARM company or the wishbone of opencores can be used in on-chip bus agreement
The avalon agreement of altera can also be used in bus protocol.
4. a kind of double-core POS machine safety chip according to claim 1, it is characterised in that: the double-core communication protocol mould
One group of SP interrupt register, including interrupt identification bit register are equipped in block, interruption sets 1 register and interrupts clear 0 register.
5. a kind of double-core POS machine safety chip according to claim 1, it is characterised in that: the double-core communication protocol mould
Block includes a mutual exclusion register.
6. a kind of double-core POS machine safety chip according to claim 1, it is characterised in that: the multimedia card interface is adopted
With eMMC interface.
7. a kind of double-core POS machine safety chip according to claim 1, it is characterised in that: the four lines peripheral hardware serial interface
The chip model of mouth is QSPI.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821676585.9U CN208848330U (en) | 2018-10-16 | 2018-10-16 | A kind of double-core POS machine safety chip |
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| CN201821676585.9U CN208848330U (en) | 2018-10-16 | 2018-10-16 | A kind of double-core POS machine safety chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112804054A (en) * | 2021-01-27 | 2021-05-14 | 上海商米科技集团股份有限公司 | Financial POS (point of sale) key capacity expansion system and key interaction method between AP (access point) chip and SP (service provider) chip |
| CN113626839A (en) * | 2021-03-31 | 2021-11-09 | 中汽创智科技有限公司 | Encryption and decryption engine system and method based on multithreading concurrent processing and automobile |
| WO2022252715A1 (en) * | 2021-12-29 | 2022-12-08 | 杭州万高科技股份有限公司 | Dual-core heterogeneous soc chip |
-
2018
- 2018-10-16 CN CN201821676585.9U patent/CN208848330U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112804054A (en) * | 2021-01-27 | 2021-05-14 | 上海商米科技集团股份有限公司 | Financial POS (point of sale) key capacity expansion system and key interaction method between AP (access point) chip and SP (service provider) chip |
| CN113626839A (en) * | 2021-03-31 | 2021-11-09 | 中汽创智科技有限公司 | Encryption and decryption engine system and method based on multithreading concurrent processing and automobile |
| WO2022252715A1 (en) * | 2021-12-29 | 2022-12-08 | 杭州万高科技股份有限公司 | Dual-core heterogeneous soc chip |
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