CN208782981U - A kind of band dual-polarized single channel frequency demultiplier of Ku - Google Patents

Abstract

The utility model discloses a kind of band dual-polarized single channel frequency demultipliers of Ku, and including frequency demultiplier cavity and the wiring board being arranged on frequency demultiplier cavity, frequency demultiplier circuit is arranged on the wiring board；The frequency demultiplier circuit, including sequentially connected rf signal reception module, amplification module, filter module, PLL handle chip, intermediate-freuqncy signal output module；The frequency demultiplier circuit further includes power supply circuit module；The rf signal reception module includes horizontally-polarized antenna and vertical polarized antenna；The intermediate-freuqncy signal output module is single channel output；The PLL processing chip is RT310S.The utility model handles chip module using integrated PLL, and properties of product are stablized, affected by environment smaller big.And chip is handled by using the PLL of RT310S, it not only can solve the spuious problem of the 22K of client's proposition, select the flatness of gain after such chip to can achieve the requirement of 6dB of client's proposition, in addition also meet the restriction required value of noise.

Description

A kind of band dual-polarized single channel frequency demultiplier of Ku

Technical field

The utility model relates to communicate to use frequency demultiplier field, more particularly to a kind of band dual-polarized single channel frequency demultiplier electricity of Ku Road and frequency demultiplier.

Background technique

Satellite television low noise block downconverter is also known as frequency demultiplier, and the effect of frequency demultiplier is to receive satellite TV signal, goes forward side by side Row channel selection, signal amplification and down conversion process, the stable intermediate-freuqncy signal of final output.It is known that on every satellite usually Possess multiple a television channels.

Because of the competitiveness demand of market user, the product of low noise frequency demultiplier is designed with resolution element (DRO scheme) in the past It has been unable to meet production cost-competitive；And frequency mixing module is affected by environment larger using the product stability of resolution element. Because design scheme adopts resolution element DRO(DRO scheme) design match pattern, product on design cost completely hair Shoot corresponding advantage.

Some frequency demultipliers, specific Ku wave band (10.7GHz~12.75GHz) faint radio frequency that satellite transmission is got off are believed Number amplify, filter, be mixed with local oscillator after export, obtain required intermediate-freuqncy signal (950MHz~2150MHz) this Section IF frequency.In the environment of market competition, need to meet the individual demand of client from different places.Because of individual area fortune Quotient client is sought to the spuious problem of the position 22KHZ (hereinafter referred to as 22K) before and after the intermediate-freuqncy signal 10.6GHZ centre frequency of output It requires, in addition, the flatness of gain changes, needs to reach the requirement of 6dB, limiting for noise wants maximizing as 1.0dB.And The frequency demultiplier of existing design can not meet the above demand.

Utility model content

In order to solve above-mentioned the deficiencies in the prior art, the utility model provides a kind of band dual-polarized single channel frequency demultiplier of Ku, Including frequency demultiplier cavity and the wiring board being arranged on frequency demultiplier cavity, frequency demultiplier circuit is set on the wiring board；The drop Frequency device circuit, including sequentially connected rf signal reception module, amplification module, filter module, PLL processing chip, intermediate frequency letter Number output module；The frequency demultiplier circuit further includes power supply circuit module；The rf signal reception module includes horizontal polarization Antenna and vertical polarized antenna；The intermediate-freuqncy signal output module is single channel output；The PLL processing chip is RT310S.

The utility model handles chip module using integrated PLL, and properties of product are stablized, affected by environment smaller big.And Chip is handled by using the PLL of RT310S, not only can solve the spuious problem of the 22K of client's proposition, after selecting such chip The flatness of gain can achieve the requirement of the 6dB of client's proposition, in addition also meet the restriction required value of noise.RT310S is The product of Rafael Microelectronics, Inc. company.

Preferably, the amplification module includes the first amplification connecting respectively with horizontally-polarized antenna and vertical polarized antenna Device and the second amplifier, the amplification module further include third amplifier, first amplifier and the second amplifier respectively with The input terminal of third amplifier connects.

By the two-stage amplifying circuit external using radio frequency in rf inputs, wanted from performance using the external amplification of two-stage Better than integrated rear built-in level-one amplification, this is based on the consideration in performance perspective.Under the premise of performance is unaffected, have compressed The materials cost of wiring board；And the first order of amplifying circuit uses the first amplifier and the second amplifier, second level amplifying circuit Third amplifier has been shared, not only there is advantage in cost price, but also the size of wiring board can be reduced.

Preferably, the amplification factor of the third amplifier is greater than the amplification factor of the first amplifier, the third amplification The amplification factor of device is greater than the amplification factor of the second amplifier.Pass through this of first order amplifying circuit and second level amplifying circuit Matching combination can make the product that performance is dominant.

Preferably, the model CDK7513 of the third amplifier.The CDK7513 is Chuo Denshi Kogyo Co., the product of L company.

Preferably, first amplifier, the second amplifier, third amplifier are respectively FET field-effect tube.

Preferably, the filter module is filter capacitor.The utility model directly carries the mode of connection with filter capacitor Substitute two-way parallel coupling microstrip bandpass filter in traditional design, it is therefore an objective to since the factor of PLL processing chip 4 itself is easily made It is vibrated at OSC, OSC oscillation is reduced by way of using filter capacitor instead and directly carrying, can stablized very much.

Preferably, the wiring board is ISOLA plate.The reflectance (VSWR) of the plate difference output used is not not With, the FR4 fibrous plate in traditional design is very big to high frequency signal attenuation, and this high frequency plate of ISOLA plate is selected to avoid Decaying to high-frequency signal.

Preferably, the power supply circuit module is connect with PLL processing chip；The power supply circuit module includes voltage-stabiliser tube, The voltage-stabiliser tube is connect with intermediate-freuqncy signal output module.

Preferably, the input terminal of the PLL processing chip is also connected with clock crystal oscillator module.

The utility model has the following beneficial effects:

The utility model handles chip module using integrated PLL, and properties of product are stablized, affected by environment smaller big.And Chip is handled by using the PLL of RT310S, not only can solve the spuious problem of the 22K of client's proposition, after selecting such chip The flatness of gain can achieve the requirement of (6dB) of client's proposition, in addition also meet the restriction required value of noise.

Detailed description of the invention

Fig. 1 is the block diagram of the band dual-polarized single channel frequency demultiplier circuit of Ku provided by the utility model；

Fig. 2 is the circuit diagram of the band dual-polarized single channel frequency demultiplier circuit of Ku provided by the utility model；

Fig. 3 is the rf signal reception module of circuit diagram shown in Fig. 2 and the partial enlarged view of amplification module；

Fig. 4 is the filter module of circuit diagram shown in Fig. 2 and the partial enlarged view of PLL processing chip；

Fig. 5 is the intermediate-freuqncy signal output module of circuit diagram shown in Fig. 2 and the partial enlarged view of power supply circuit module.

Appended drawing reference:

1- rf signal reception module, 11- horizontally-polarized antenna, 12- vertical polarized antenna, 2- amplification module, 21- first Amplifier, the second amplifier of 22-, 23- third amplifier, 3- filter module, 4- PLL processing chip, 5- intermediate-freuqncy signal export mould Block, 6- power supply circuit module, 7- clock crystal oscillator module.

Specific embodiment

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work Every other embodiment obtained, fall within the protection scope of the utility model.

Embodiment one

The band dual-polarized single channel frequency demultiplier of Ku provided by the embodiment of the utility model, including frequency reducing is discussed in detail in the present embodiment Device cavity and the wiring board being arranged on frequency demultiplier cavity are provided with the band dual-polarized single channel frequency demultiplier electricity of Ku on the wiring board Road.As shown in Fig. 1 ~ Fig. 5, the band dual-polarized single channel frequency demultiplier circuit of Ku, including sequentially connected rf signal reception module 1, Amplification module 2, filter module 3, PLL handle chip 4, intermediate-freuqncy signal output module 5.Rf signal reception module 1 includes level Poliarizing antenna 11 and vertical polarized antenna 12, horizontally-polarized antenna 11 and vertical polarized antenna 12 are respectively used to reception space level With the ku waveband radio frequency signal in vertical direction, Ku audio range frequency is the .75GHz of 10 .7 ~ 12.Frequency demultiplier circuit its can be by Ku The weak radio-frequency signal that wave band (10.7GHz~12.75GHz) satellite transmission gets off is amplified, is filtered, being mixed with local oscillator It is exported after frequency, finally obtains required intermediate-freuqncy signal (950MHz~2150MHz) this section of IF frequency, in the utility model Frequency signal output module 5 is single channel output.The PLL processing chip is RT310S.The utility model is using integrated PLL processing Chip module, properties of product are stablized, affected by environment smaller big.And chip is handled by using the PLL of RT310S, it not only can be with It solves the problems, such as that the 22K's that client proposes is spuious, the flatness of gain after such chip is selected to can achieve (6dB) of client's proposition It is required that in addition also meeting the restriction required value of noise.

Amplification module 2 uses two-stage amplification module, first order amplification module include respectively with horizontally-polarized antenna and vertical The first amplifier 21 and the second amplifier 22 of poliarizing antenna connection.Second level amplification module includes third amplifier 23, described First amplifier 21 and the second amplifier 22 are connect with the input terminal of third amplifier 23 respectively, the output end of third amplifier 23 Connect filter module 3.

The frequency demultiplier circuit of the utility model uses PLL conceptual design, uses external two of radio frequency in rf inputs Grade amplifying circuit is better than integrated rear built-in level-one using the external amplification of two-stage from performance and amplifies, this is based on performance perspective On consideration.And the first order amplifying circuit of amplifying circuit uses the first amplifier 21 and the second amplifier 22, second level amplification Circuit has shared third amplifier 23, not only has advantage in cost price, but also can reduce the size of wiring board.

As a preferred option, the amplification factor of the third amplifier 23 is greater than the amplification factor of the first amplifier 21, The amplification factor of the third amplifier 23 is greater than the amplification factor of the second amplifier 22.Pass through first order amplifying circuit and second This matching combination of grade amplifying circuit can make the product that performance is dominant.As a preferred option, first amplifier 21, Second amplifier 22, third amplifier 23 are respectively FET field-effect tube.As shown in figure 3, the first amplifier 21, the second amplifier 22, third amplifier 23 is FET field-effect tube Q1, Q2, Q3 respectively.The third amplifier 23 of second level amplifying circuit is general optional With the one of which in CDK7513, CDK7514, CDK8513, CDK7543.More preferred, the third amplifier Model CDK7513.

Preferably, filter module 3 selects filter capacitor.The utility model is directly replaced with the mode that filter capacitor carries connection For parallel coupling microstrip bandpass filter two-way in traditional design, it is therefore an objective to since the factor of PLL processing chip 4 itself easily causes OSC oscillation reduces OSC oscillation by way of using filter capacitor instead and directly carrying, and can stablize very much.

Amplification module further includes multiple capacitors and resistance.There is coupling between the first amplifier 21 and third amplifier 23 Capacitor has coupled capacitor between the second amplifier 22 and third amplifier 23.First amplifier 21, the second amplifier 22, The front of third amplifier 23 also has the resistance of respectively their offer bias voltages.

The frequency demultiplier circuit further includes power supply circuit module 6.Power supply circuit module 6 is connect with PLL processing chip 4, institute Stating power supply circuit module 6 includes voltage-stabiliser tube, as shown in figure 5, the input terminal connection PLL processing chip of power supply circuit module 6 POL22K foot, by PLL processing chip 4 provide 13V 18V voltage, then core handled by voltage-stabiliser tube U2 decompression access PLL The VCC foot of piece 4 handles chip for PLL and provides a low-voltage, and PLL processing chip 4 is allowed to have horizontal polarization signals and vertical polarization The function of signal switching.One end of the voltage-stabiliser tube is also connect with the output end of intermediate-freuqncy signal output module 5.

The input terminal of PLL processing chip 4 is also connected with clock crystal oscillator module 7, and clock crystal oscillator module 7 is for exciting and starting PLL handles the internal logic circuit of chip 4, and controls two-way radiofrequency signal and carry out Frequency mixing processing.When PLL processing chip 4 by when After the excitation starting of clock crystal oscillator module 7, amplified radiofrequency signal is subjected to function point, be then mixed and forms single channel intermediate frequency letter Number this section of IF frequency of 950MHz~2150MHz.

Preferably, the wiring board is ISOLA plate.The reflectance (VSWR) of the plate difference output used is not not With, the FR4 fibrous plate in traditional design is very big to high frequency signal attenuation, and this high frequency plate of ISOLA plate is selected to avoid Decaying to high-frequency signal.

The utility model has the following beneficial effects:

A kind of band dual-polarized single channel frequency demultiplier circuit of Ku provided by the utility model and frequency demultiplier, frequency demultiplier circuit are adopted Amplified from performance in the rf inputs two-stage amplifying circuit external using radio frequency using two-stage is external with PLL conceptual design It is better than integrated rear built-in level-one amplification, this is based on the consideration in performance perspective.And the first order of amplifying circuit uses first Amplifier and the second amplifier, second level amplifying circuit have shared third amplifier, not only have advantage in cost price, and And the size of wiring board can also be reduced.

It should be understood that for those of ordinary skills, it can be modified or changed according to the above description, All these improvement or transformation all should belong within the protection scope of the appended claims for the utility model.

Claims (9)

1. a kind of band dual-polarized single channel frequency demultiplier of Ku, including frequency demultiplier cavity and the wiring board being arranged on frequency demultiplier cavity, Frequency demultiplier circuit is set on the wiring board；The frequency demultiplier circuit, including sequentially connected rf signal reception module, amplification Module, filter module, PLL handle chip, intermediate-freuqncy signal output module；The frequency demultiplier circuit further includes power supply circuit module； It is characterized in that, the rf signal reception module includes horizontally-polarized antenna and vertical polarized antenna；The intermediate-freuqncy signal is defeated Module is single channel output out；The PLL processing chip is RT310S.

2. frequency demultiplier according to claim 1, which is characterized in that the amplification module include respectively with horizontally-polarized antenna The first amplifier and the second amplifier connected with vertical polarized antenna, the amplification module further includes third amplifier, described First amplifier and the second amplifier are connect with the input terminal of third amplifier respectively.

3. frequency demultiplier according to claim 2, which is characterized in that the amplification factor of the third amplifier is greater than first and puts The amplification factor of big device, the amplification factor of the third amplifier are greater than the amplification factor of the second amplifier.

4. frequency demultiplier according to claim 3, which is characterized in that the model CDK7513 of the third amplifier.

5. frequency demultiplier according to claim 2, which is characterized in that first amplifier, the second amplifier, third amplification Device is respectively FET field-effect tube.

6. frequency demultiplier according to claim 1, which is characterized in that the filter module is filter capacitor.

7. frequency demultiplier according to claim 1, which is characterized in that the wiring board is ISOLA plate.

8. frequency demultiplier according to claim 1, which is characterized in that the power supply circuit module is connect with PLL processing chip； The power supply circuit module includes voltage-stabiliser tube, and the voltage-stabiliser tube is connect with intermediate-freuqncy signal output module.

9. frequency demultiplier according to claim 1, which is characterized in that when the input terminal of the PLL processing chip is also connected with Clock crystal oscillator module.