CN208781808U - Semiconductor devices - Google Patents
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- CN208781808U CN208781808U CN201821515238.8U CN201821515238U CN208781808U CN 208781808 U CN208781808 U CN 208781808U CN 201821515238 U CN201821515238 U CN 201821515238U CN 208781808 U CN208781808 U CN 208781808U
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Abstract
The utility model provides a kind of semiconductor devices, and the hard mask layer being arranged including substrate, in substrate and the first sacrificial layer being arranged on hard mask layer are formed with micro- pattern in the first sacrificial layer.The utility model improves the alignment precision of semiconductor devices, avoids the generation of contact resistance and parasitic capacitance problems, substantially increases finished product rate, while the utility model product structure is simple, at low cost.
Description
Technical field
The utility model relates to field of semiconductor manufacture, in particular to semiconductor integrated circuit manufacturing field, and in particular to
A kind of semiconductor devices.
Background technique
Photoetching is basic technology used in manufacture integrated circuit.Generally speaking, photoetching is included in material layer or substrate
(substrate) top forms light or radiation sensitive material layer, such as photoresist.By the radiation-sensitive materials be exposed selectively to by
The light that light source (such as deep ultraviolet or extreme ultraviolet source) generates, is transferred to the radiation-sensitive materials for the pattern defined by exposure mask.
The exposed surface of the radiation-sensitive materials is developed to define patterned mask layer.Then, through the patterned mask layer under this
Various technological operations, such as etching or ion implantation technology can be performed on the square bar bed of material or substrate.
The purpose of IC manufacturing is the verily circuit design of replicating original on IC products.The prior art
Disclosing photoetching process is one of the critical process in ic manufacturing process.As integrated circuit feature size constantly contracts
Small, territory pattern density is continuously increased, but the wavelength of light source used in photoetching is not substantially reduced, and exposure resolution does not mention significantly
It rises, thus causes on same mask plate, pattern number of collisions is continuously increased.The pattern conflict is defined as two territory patterns
Standoff distance is less than a certain particular value, this particular value is known as the distance that conflicts.Studies have shown that multiple-exposure photoetching technique is to solve
One of the effective way of pattern conflict.
Multiple-exposure photoetching process is decomposed territory pattern on multiple different mask plates, and multiple exposure and quarter are passed through
The iterative process of erosion ultimately forms complete silicon wafer pattern.How GDSII design layout pattern multiple are assigned to different to cover
In film version, so that the pattern conflict on same mask plate is minimum, it is the key that multiple-exposure domain distribution method；Meanwhile
In order to reduce number of collisions, same territory pattern may be divided and be assigned on different mask plates.
In 20/22 nano-technology techniques node, double exposure photolithographic process is widely used.In double exposure light
In carving technology, the pattern being assigned on two mask plates is made usually using exposure-etching-exposure-etching technics (LELE)
It makes, double patterning is a kind of exposure method comprising intensive overall goal circuit pattern is divided into and (namely divides or divides
From) two independent less dense patterns.Then, by using two independent exposure mask (wherein, one of use of the exposure mask
With one of imaging to the less dense pattern, and another exposure mask is to be imaged another less dense pattern), it will
The simple less dense pattern is independently printed on wafer.The complexity of photoetching process is effectively reduced in this technology, improves reachable
To resolution ratio and smaller feature can be printed, otherwise, the use of existing lithography tool is impossible.Photoetching-erosion
Quarter-photoetching-etching (LELE) is multiple patterning techniques as one kind.
But in 14/16 nano-technology techniques node, with further reducing for integrated circuit feature size, territory pattern is more
Crypto set is difficult to decompose original layout pattern on two mask plates and does not generate pattern conflict, introduces three re-exposure thus
Photoetching process.In triple exposure technologies, usually using exposure-etching-exposure-etching-exposure-etching (LELELE) technique into
Row production, triple patternings are a kind of increasingly complex exposure methods comprising are divided into intensive overall goal circuit pattern
(namely divide or separate) three independent less dense patterns.It then, will be simple by using three independent exposure masks
Less dense pattern is independently printed on wafer.The complexity of photoetching process is effectively reduced in this technology, improves accessible resolution
Rate simultaneously can print smaller feature, otherwise, it the use of existing lithography tool is impossible.Photoetching-etching-photoetching-
Etching-photoetching-etching (litho-etch-litho-etch-litho-etch；It LELELE) is multiple patterning as one kind
Technology.Pattern can not be formed by single exposure mask, and be divided into three patterns.Different colors is distributed to each pattern,
In, all meet design rule in various colors.But, LELELE needs are carefully aligned between exposure mask, this technology is deposited
The problems such as process is cumbersome, and interlayer alignment precision long with the period at high cost is low.
Patent publication No. is the Chinese patent of CN103578952A, discloses and a kind of forms grid using gap wall technique
The manufacturing method of transistor.In the method for the utility model, in the side of dummy gate electrode storehouse, the first gap is sequentially formed
Wall, the second clearance wall and third space wall form the grid that width is controlled by the second clearance wall by removing the second clearance wall
Groove, grid required for then being formed in gate recess and gate insulating layer.
Patent publication No. is the Chinese patent of CN105470117A, disclose a kind of semiconductor devices based on double patterning and
Its manufacturing method, electronic device, the described method comprises the following steps: provide semiconductor substrate, on the semiconductor substrate shape
At there is several spaced virtual core laminations；The first rectangular clearance wall is sequentially formed on the side wall of the virtual core lamination
With the second clearance wall；The virtual core lamination is removed, with obtain being made of first clearance wall and second clearance wall
Clearance wall array；First clearance wall described in etch-back or second clearance wall, so that the distance between described clearance wall array
It is equal.
Above method complex operation is unable to large-scale promotion use.
Utility model content
That the technical problem to be solved by the present invention is to provide a kind of alignment precisions is high, structure is simple, at low cost and have
The semiconductor devices of fine micro-pattern, to realize the above-mentioned technical purpose, the specific technical solution that the utility model is taken are as follows:
A kind of semiconductor devices, the hard mask layer being arranged including substrate, on the substrate and on the hard mask layer
The first sacrificial layer being arranged, is formed with micro- pattern on first sacrificial layer, micro- pattern by following steps to reach
At the second sacrificial layer is arranged on first sacrificial layer, 3rd sacrifice layer is arranged on second sacrificial layer；Described in etching
3rd sacrifice layer forms the first dot pattern using exposure development and figure transposition, and first dot pattern is by first row figure
Case column combines formation on second sacrificial layer；Second sacrificial layer is etched, is formed using exposure development and figure transposition
Second dot pattern, second dot pattern group on first sacrificial layer by first row pattern column and secondary series pattern column
It closes and constitutes, the interval between the first row pattern column and the secondary series pattern column includes closely-spaced and large-spacing；Described
On second dot pattern deposit autoregistration coating, the autoregistration coating be completely covered it is described closely-spaced, described from right
The 4th sacrificial layer is deposited on quasi- coating, recycles autoregistration to form third dot pattern, the third dot pattern is by first
Column pattern column, secondary series pattern column and third column pattern column combine formation, the third column pattern on first sacrificial layer
Column is located in the large-spacing；First sacrificial layer is performed etching described first using the third dot pattern as exposure mask
Sacrificial layer forms micro- pattern.
As an improved technical scheme, the deposition thickness of the autoregistration coating is greater than two points of the closely-spaced width
One of.
As an improved technical scheme, the deposition thickness of the autoregistration coating is less than two points of the large-spacing width
One of.
As an improved technical scheme, the coating photoresist in the 3rd sacrifice layer carries out first time photoetching process, shape
The 3rd sacrifice layer is etched using first photoetching offset plate figure as exposure mask at the first photoetching offset plate figure, by first photoetching
Glue pattern, which is transferred in the 3rd sacrifice layer, forms first dot pattern.
As an improved technical scheme, the coating photoresist on first dot pattern carries out second of photoetching process,
The second photoetching offset plate figure is formed, it is sacrificial to described second using first dot pattern and second photoetching offset plate figure as exposure mask
Domestic animal layer performs etching, and first dot pattern and second photoetching offset plate figure are transferred on second sacrificial layer and formed
Second dot pattern.
As an improved technical scheme, autoregistration coating is deposited on second dot pattern, the autoregistration is covered
Cap rock is completely covered described closely-spaced, deposits the 4th sacrificial layer on the autoregistration coating, it is sacrificial to etch the described 4th
Domestic animal layer remains on the 4th sacrificial layer only in the large-spacing, further etches the autoregistration coating, forms the
Three dot patterns.
As an improved technical scheme, the 3rd sacrifice layer and first sacrificial layer use identical material, described
3rd sacrifice layer includes borophosphosilicate glass layer.
As an improved technical scheme, second sacrificial layer and the 4th sacrificial layer use identical material, described
Second sacrificial layer includes silicon oxide layer.
Beneficial effect
The utility model provides a kind of semiconductor devices with micro- pattern, and what is be arranged including substrate, in substrate covers firmly
Film layer and the first sacrificial layer being arranged on hard mask layer, are formed with micro- pattern on the first sacrificial layer, using exposure development and
Figure transposition forms the first dot pattern and the second dot pattern, and the second dot pattern is by first row pattern column and secondary series pattern
Column is formed, and the interval between first row pattern column and the secondary series pattern column includes closely-spaced and large-spacing；It is dotted second
Autoregistration coating is deposited on pattern, autoregistration coating is completely covered described closely-spaced, and autoregistration coating adequately protects
Second dot pattern is not influenced by subsequent deposition and etching step.Self-aligned technology is recycled to form third dot pattern, this
Utility model improves the alignment precision of semiconductor devices, avoids the generation of contact resistance and parasitic capacitance problems, mentions significantly
High finished product rate, while the utility model product structure is simple, it is at low cost.
Detailed description of the invention
Fig. 1 is painted the structure section figure obtained after step S1 in the utility model embodiment.
Fig. 2 is painted the cross-section diagram of the structure after forming the first photoetching offset plate figure in the utility model embodiment.
Fig. 3 is painted the top view of the structure after forming the first photoetching offset plate figure in the utility model embodiment.
Fig. 4 is painted the cross-section diagram that the structure after 3rd sacrifice layer is etched in the utility model embodiment.
Fig. 5 is painted the top view of the structure after forming the first dot pattern in the utility model embodiment.
Fig. 6 is painted the structure in the utility model embodiment in step S3 on the first dot pattern after coating photoresist
Cross-section diagram.
Fig. 7 is painted the structure in the utility model embodiment in step S3 on the first dot pattern after coating photoresist
Top view.
Fig. 8 is painted the cross-section diagram of the structure after forming the second photoetching offset plate figure in the utility model embodiment.
Fig. 9 is painted the top view of the structure after forming the second photoetching offset plate figure in the utility model embodiment.
Figure 10 is painted the cross-section diagram of the structure after etching the second sacrificial layer in the utility model embodiment.
Figure 11 is painted the top view of the structure after forming the second dot pattern in the utility model embodiment.
Figure 12 is painted the cross-section diagram that the structure after autoregistration coating is deposited in the utility model embodiment.
Figure 13 is painted the top view that the structure after autoregistration coating is deposited in the utility model embodiment.
Figure 14 is painted the cross-section diagram that the structure after the 4th sacrificial layer is deposited in the utility model embodiment.
Figure 15 is painted the top view that the structure after the 4th sacrificial layer is deposited in the utility model embodiment.
Figure 16 is painted the cross-section diagram that the structure after the 4th sacrificial layer is etched in the utility model embodiment.
Figure 17 is painted the top view that the structure after the 4th sacrificial layer is etched in the utility model embodiment.
Figure 18 is painted the cross-section diagram that the structure after autoregistration coating is etched in the utility model embodiment.
Figure 19 is painted the top view that the structure after third dot pattern is formed in the utility model embodiment.
Figure 20 is painted the cross-section diagram of the structure after etching the first sacrificial layer in the utility model embodiment.
Figure 21 is painted the top view of the structure after forming micro- pattern in the utility model embodiment.
In figure, 101, substrate；102, photoresist；11, closely-spaced；110, hard mask layer；12, large-spacing；120, first is sacrificial
Domestic animal layer；130, the second sacrificial layer；140,3rd sacrifice layer；150, autoregistration coating；160, the 4th sacrificial layer.
Specific embodiment
To keep the purpose and technical solution of the utility model embodiment clearer, implement below in conjunction with the utility model
The technical solution of the utility model is clearly and completely described in example.Obviously, described embodiment is the utility model
A part of the embodiment, instead of all the embodiments.Based on described the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained under the premise of being not necessarily to creative work, belongs to the model of the utility model protection
It encloses.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, all terms used herein (including technology art
Language and scientific term) there is meaning identical with the general understanding of those of ordinary skill in the utility model fields.Also
It should be understood that those terms such as defined in the general dictionary should be understood that have in the context of the prior art
The consistent meaning of meaning will not be explained in an idealized or overly formal meaning and unless defined as here.
In order to solve alignment precision existing for photoetching-etching-photoetching-etching-photoetching-etching (LELELE) in the prior art
The problem of contact resistance caused by low and parasitic capacitance, the utility model provides a kind of semiconductor devices with micro- pattern.
The utility model embodiment is related to a kind of semiconductor devices with micro- pattern, which is schemed more using autoregistration
Case technology is formed with less than the miniature sectional hole patterns of the spacing of the resolution ratio of permission.
In addition, including implementing Twi-lithography technology in the product preparation process.Therefore, it is possible to reduce using typical case Duo Tu
The undesirable critical dimension (CD) often generated when case technology by the misalignment of exposed mask (misalignment).Also,
Because reducing the implementation number of exposure technology, it is possible to reduce cost.
Fig. 2 to 21, which is shown in this semiconductor devices, forms semiconductor device structure cross-section diagram and vertical view in micro- patterning process
Figure.Fig. 2,4,6,8,10,12,14,16,18 and 20 indicate semiconductor devices structure section figure, Fig. 3,5,7,9,11,13,15,
17,19 and 21 top view for respectively indicating semiconductor devices shown in Fig. 2,4,6,8,10,12,14,16,18 and 20.This is practical
Novel product specific the preparation method is as follows:
Step S1: as shown in Figure 1, providing a substrate 101, hard mask layer 110 is formed in substrate 101, in hard mask layer
The first sacrificial layer 120 is formed on 110, and the second sacrificial layer 130 is formed on the first sacrificial layer 120, the shape on the second sacrificial layer 130
At 3rd sacrifice layer 140；
Step S2: as shown in Figure 2,3, the coating photoresist 102 in 3rd sacrifice layer 140 carries out first time photoetching process,
Form the first photoetching offset plate figure.As shown in Figure 4,5, using the first photoetching offset plate figure as exposure mask, the first photoetching offset plate figure is passed through into quarter
Erosion, which is transferred in 3rd sacrifice layer 140, forms the first dot pattern.First dot pattern is sacrificed by first row pattern column second
It combines and is formed on layer 130；Wherein lithographic method can be dry etching；
Step S3: as shown in Fig. 6,7,8,9,10,11, the coating photoresist 102 on the first dot pattern is carried out second
Photoetching process forms the second photoetching offset plate figure, using the first dot pattern and the second photoetching offset plate figure as exposure mask, by the first scattergram
Case and the second photoetching offset plate figure are transferred on second sacrificial layer 130 by etching forms the second dot pattern.Second is dotted
Pattern is combined on first sacrificial layer 120 by first row pattern column and secondary series pattern column and is constituted, first row pattern column and
Interval between secondary series pattern column includes closely-spaced 11 and large-spacing 12；
Step S4: as shown in Figure 12,13,14,15,16,17,18,19, autoregistration covering is deposited on the second dot pattern
Layer 150, it is preferred that the deposition thickness of autoregistration coating 150 is greater than the half or autoregistration covering of closely-spaced 11 width
The deposition thickness of layer 150 is less than the half of 12 width of large-spacing, it is furthermore preferred that the deposition thickness of autoregistration coating 150
Half greater than closely-spaced 11 width and the half less than 12 width of large-spacing are sunk on autoregistration coating 150
The 4th sacrificial layer 160 of product etches the 4th sacrificial layer 160 and the 4th sacrificial layer 160 is only remained in the large-spacing 12,
Autoregistration coating 150 of the etching without the covering of the 4th sacrificial layer 160 simultaneously retains the second sacrificial layer 130 in the second dot pattern,
Form third dot pattern.Third dot pattern is by first row pattern column, secondary series pattern column and third column pattern column first
It combines and is formed on sacrificial layer 120, wherein third column pattern column is located in large-spacing 12.
Step S5: as shown in Figure 20,21, the first sacrificial layer 120 is performed etching as exposure mask using third dot pattern to be formed
Micro- pattern.
In the present embodiment the area of the first dot pattern can less than the area of the second dot pattern, the second dot pattern
Area can be less than the area of third dot pattern.
The etching selectivity of 3rd sacrifice layer 140 and the second sacrificial layer 130, the second sacrificial layer 130 and the first sacrificial layer 120
Etching selectivity and autoregistration coating 150 can be different from 130 etching selectivity of the second sacrificial layer, 3rd sacrifice layer 140
Etching selectivity with the second sacrificial layer 130 is 1:2 or more, the etching selectivity of the second sacrificial layer 130 and the first sacrificial layer 120
For 1:3 or more.The etching selectivity of autoregistration coating 150 and the second sacrificial layer 130 is between 1:5~1:10, autoregistration covering
The etching selectivity of layer 150 and the 4th sacrificial layer 160 is between 3:1~10:1, autoregistration coating 150 and the first sacrificial layer 120
Etching selectivity between 1:5~1:10.3rd sacrifice layer 140 and the first sacrificial layer 120 can use identical material, and second
Sacrificial layer 130 and the 4th sacrificial layer 160 can use identical material.3rd sacrifice layer 140 may include borophosphosilicate glass layer；
Second sacrificial layer 130 may include silicon oxide layer；4th sacrificial layer 160 may include silicon oxide layer；First sacrificial layer 120 can be with
Include borophosphosilicate glass layer.The 4th sacrificial layer can be etched using one of etch back process and immersion technique in step s 4
160。
The utility model implements the 3rd sacrifice layer by using the etching rate difference between different etching targets
140, the etching of the second sacrificial layer 130, the 4th sacrificial layer 160 and the first sacrificial layer 120.
Point of permission is formed with less than by the more patterning techniques of autoregistration according to the embodiments of the present invention
The miniature sectional hole patterns of the spacing of resolution.Furthermore due to photoetching process of few implementation, can effectively reduce using typical more patterns
The undesirable critical dimension (CD) between pattern often generated when change technology by the misalignment of exposed mask.Also, because subtract
The implementation number of few exposure technology, it is possible to reduce cost.
Hard mask layer 110 is formed in the present invention to reduce the influence to etching layer, and the wherein influence may be by
In hard mask layer 110 produced by the inclination of subsequent sectional hole patterns to be formed.Hard mask layer 110 may include carbon-coating, polycrystalline
One of silicon layer and the layer based on oxide.Hard mask layer 110 includes that opposite first sacrificial layer 120 has etching selectivity
Material.For example, the first sacrificial layer 120 is formed as including polysilicon if hard mask layer 110 may include the layer based on oxide
One of layer and the layer based on nitride, if hard mask layer 110 includes polysilicon layer, the first sacrificial layer 120 forms packet
Include the layer based on oxide.
3rd sacrifice layer 140 can also include carbon-coating, and 102 layers of photoresist are formed in 3rd sacrifice layer 140, implement exposure
102 layers of photoresist are patterned, with developing process to form 102 pattern of photoresist with groove-shaped opening.Forming photoetching
Before 102 pattern of glue, bottom antireflective coating can be additionally formed.102 pattern P R of photoresist can be used as mask, erosion
Carve bottom antireflective coating and 3rd sacrifice layer 140.At this point, because being made using 102 pattern of photoresist with groove-shaped opening
3rd sacrifice layer 140 is etched for mask, so the opening of 102 pattern of photoresist is reflected into 3rd sacrifice layer 140, thus
Groove-shaped opening can be formed in 3rd sacrifice layer 140.
In one embodiment of the utility model, it can be used and implement the removal technique of photoresist 102, to remove photoresist
The remaining portion of 102 patterns and bottom antireflective coating.Cleaning process after implementation.At this point, if the first sacrificial pattern includes can
The material that technique easy removal is removed by photoresist 102 then can be omitted photoresist 102 and remove technique.
In one embodiment of the utility model, autoregistration coating 150 may include covering with 0.9 or bigger ladder
Cover degree (step coverage) and the material relative to the second sacrificial layer 130 and the 4th sacrificial layer 160 with etching selectivity.
For example, autoregistration coating 150 may include one of layer and polysilicon layer based on oxide.
In one embodiment of the utility model, formed using certain deposition gases at a certain temperature from right
Quasi- coating 150, wherein can choose temperature not have negative effect to sacrificial layer.For example, if sacrificial layer includes carbon-coating,
Then when forming autoregistration coating 150 under high-temperature, sacrificial layer may shrink and deform.It therefore, can be at about 25 DEG C extremely
Autoregistration coating 150 is formed under about 300 DEG C of low temperature range.Furthermore, it is possible to use the gas for not having negative effect to sacrificial layer
Body forms autoregistration coating 150, so as to used during the formation of autoregistration coating 150 gas will not remove it is sacrificial
Domestic animal layer.
In one embodiment of the utility model, etch back process can be implemented to autoregistration coating 150, second
Autoregistration coating 150 is deposited on dot pattern, the deposition thickness of autoregistration coating 150 is greater than two points of closely-spaced 11 width
One of and be less than 12 width of large-spacing half, on autoregistration coating 150 deposit the 4th sacrificial layer 160, etch institute
Stating the 4th sacrificial layer 160 remains on the 4th sacrificial layer 160 only in the large-spacing 12, and etching is covered without the 4th sacrificial layer 160
The autoregistration coating 150 of lid simultaneously retains the second sacrificial layer 130 in the second dot pattern, forms third dot pattern.Third
Dot pattern is combined on the first sacrificial layer 120 by first row pattern column, secondary series pattern column and third column pattern column and is formed,
Middle third column pattern column is located in large-spacing 12.The utility model improves alignment precision in capacitance pattern manufacturing process, avoids
The generation of contact resistance and parasitic capacitance problems, substantially increases finished product rate.The utility model method operated simultaneously
Journey is simple, and the at low cost and period is short.
The above is only the embodiments of the present invention, and the description thereof is more specific and detailed, but cannot therefore be interpreted as
A limitation on the scope of the patent of the present invention.It should be pointed out that those skilled in the art, not departing from this
Under the premise of utility model is conceived, various modifications and improvements can be made, these belong to the protection scope of the utility model.
Claims (8)
1. a kind of semiconductor devices, the hard mask layer being arranged including substrate, on the substrate and set on the hard mask layer
The first sacrificial layer set is formed with micro- pattern on first sacrificial layer, which is characterized in that passing through for micro- pattern is following
The second sacrificial layer is arranged on first sacrificial layer to reach in step, and 3rd sacrifice layer is arranged on second sacrificial layer；
Etch the 3rd sacrifice layer, form the first dot pattern using exposure development and figure transposition, first dot pattern by
First row pattern column combines formation on second sacrificial layer；Second sacrificial layer is etched, exposure development and figure are utilized
Transposition forms the second dot pattern, and second dot pattern is sacrificial described first by first row pattern column and secondary series pattern column
It combines and constitutes on domestic animal layer, between the interval between the first row pattern column and the secondary series pattern column includes closely-spaced and big
Every；On second dot pattern deposit autoregistration coating, the autoregistration coating be completely covered it is described closely-spaced,
The 4th sacrificial layer is deposited on the autoregistration coating, and autoregistration is recycled to form third dot pattern, the third scattergram
Case is combined on first sacrificial layer by first row pattern column, secondary series pattern column and third column pattern column and is formed, and described
Three column pattern columns are located in the large-spacing；First sacrificial layer is performed etching using the third dot pattern as exposure mask
First sacrificial layer forms micro- pattern.
2. semiconductor devices according to claim 1, which is characterized in that the deposition thickness of the autoregistration coating is greater than
The half of the closely-spaced width.
3. semiconductor devices according to claim 2, which is characterized in that the deposition thickness of the autoregistration coating is less than
The half of the large-spacing width.
4. semiconductor devices according to claim 1, which is characterized in that the coating photoresist in the 3rd sacrifice layer,
First time photoetching process is carried out, the first photoetching offset plate figure is formed using first photoetching offset plate figure as exposure mask and etches the third
First photoetching offset plate figure is transferred in the 3rd sacrifice layer and forms first dot pattern by sacrificial layer.
5. semiconductor devices according to claim 1, which is characterized in that be coated with photoetching on first dot pattern
Glue carries out second of photoetching process, the second photoetching offset plate figure is formed, with first dot pattern and the second photoresist figure
Shape is exposure mask, is performed etching to second sacrificial layer, and first dot pattern and second photoetching offset plate figure are shifted
Second dot pattern is formed on to second sacrificial layer.
6. semiconductor devices according to claim 1, which is characterized in that deposit autoregistration on second dot pattern
Coating, the autoregistration coating are completely covered described closely-spaced, and it is sacrificial on the autoregistration coating to deposit the described 4th
Domestic animal layer etches the 4th sacrificial layer and the 4th sacrificial layer is only remained in the large-spacing, further described in etching
Autoregistration coating forms third dot pattern.
7. semiconductor devices according to claim 1, which is characterized in that the 3rd sacrifice layer and first sacrificial layer
Using identical material, the 3rd sacrifice layer includes borophosphosilicate glass layer.
8. semiconductor devices according to claim 1, which is characterized in that second sacrificial layer and the 4th sacrificial layer
Using identical material, second sacrificial layer includes silicon oxide layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110911272A (en) * | 2018-09-17 | 2020-03-24 | 长鑫存储技术有限公司 | Method of forming micro pattern in semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110911272A (en) * | 2018-09-17 | 2020-03-24 | 长鑫存储技术有限公司 | Method of forming micro pattern in semiconductor device |
| CN110911272B (en) * | 2018-09-17 | 2024-05-03 | 长鑫存储技术有限公司 | Method for forming micro pattern in semiconductor device |
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| GR01 | Patent grant |