CN208739262U - It is used for transmission the transmitting line of SDI and ASI data - Google Patents

Abstract

The utility model relates to field of data transmission, disclose a kind of transmitting line for being used for transmission SDI and ASI data, it can be achieved that the transmission of sdi signal and the transmission of DVB-ASI signal after circuit loads corresponding software.The utility model includes a bnc interface, driving circuit, a fpga chip, a clock generator and a parallel-to-serial converter that can be driven respectively to SDI and DVB-ASI data；The fpga chip is electrically connected with the driving circuit, clock generator and parallel-to-serial converter respectively, and the driving circuit is electrically connected with the bnc interface.The utility model is suitable for a variety of occasions such as digital studio, radio and television production, digital film production.

Description

It is used for transmission the transmitting line of SDI and ASI data

Technical field

The utility model relates to field of data transmission, in particular to a kind of transmission electricity for being used for transmission SDI and ASI data Road.

Background technique

Currently, the specification of SDI has standard definition (Standard Definition, SD), fine definition (High Definition, HD) and tri- kinds of SDI of 3G (3Gbit/s).SD-SDI is defined by SMPTE 259M standard, it is considered to be tradition SDI in meaning, it passes through the digital video of video coaxial cable serial transmission standard definition.HD-SDI is by SMPTE 292M Standard is defined, similar with SD-SDI, but what is transmitted is digital video high-definition.3G-SDI is by SMPTE 424M standard institute Definition, makes improvements on the basis of HD-SDI, to support the transmission of more high-definition digital video.In digital studio's sum number Code production of film and TV center, SD-SDI have been widely used, and with the continuous development of HDTV industry, HD-SDI and 3G-SDI's Demand just increases sharply.

DVB-ASI (digital television broadcasting Asynchronous Serial Interface) is a kind of serial video communication mark defined by DVB tissue Standard, for transmitting the video flowing of mpeg encoded, transmission rate reaches 270Mb/s.ASI interface is in current radio data system Use a kind of very extensive interface form.

Utility model content

Technical problem to be solved by the utility model is: a kind of transmitting line for being used for transmission SDI and ASI data is provided, , it can be achieved that the transmission of sdi signal and the transmission of DVB-ASI signal after circuit loads corresponding software.

To solve the above problems, the technical solution adopted in the utility model is: being used for transmission the transmission of SDI and ASI data Circuit, including a bnc interface, driving circuit, a FPGA that can be driven respectively to SDI and DVB-ASI data Chip, a clock generator and a parallel-to-serial converter；The fpga chip is sent out with the driving circuit, clock respectively Raw device and parallel-to-serial converter electrical connection, the driving circuit are electrically connected with the bnc interface.

Preferably, the driving circuit includes LMH0040 chip, and the fpga chip is SPARTAN-3A Series FPGA core Piece, the clock generator include LMK03000C chip.

The beneficial effects of the utility model are: the utility model framework is simple, required chip is few, it is only necessary to which a BNC connects Mouth is able to realize the transmission of sdi signal and ASI signal.It can be flexibly applied to digital studio, radio and television production, number The a variety of occasions of code production of film and TV etc., particularly suitable interface resource is nervous and needs support the video of a variety of rate sdi signals and sets It is standby.

Detailed description of the invention

Fig. 1 is the structure chart of the utility model.

Fig. 2 is the video processing principles figure of SDI in utility model.

Fig. 3 is the handling principle figure of DVB-ASI signal in utility model.

Specific embodiment

The utility model is directed to a kind of transmitting line for being used for transmission SDI and ASI data, to realize multi-speed SDI The transmission of signal and the transmission of DVB-ASI signal.As shown in Figure 1, the utility model can be distinguished including a bnc interface, one The driving circuit that is driven to SDI and DVB-ASI data, a fpga chip, a clock generator and one simultaneously go here and there Conversion circuit；The fpga chip is electrically connected with the driving circuit, clock generator and parallel-to-serial converter respectively, described Driving circuit is electrically connected with the bnc interface.

Driving circuit described in the utility model can select LMH0040 chip architecture, the drive as SDI and DVB-ASI The dynamic basic electric interfaces of device are connected to the bnc interface of coaxial cable, they are always used separately to solid in previous solution Fixed output, and the function of the two can be neatly realized in the LMH0040 chip of single-chip.This chip can support speed to reach The DVB-ASI interface of 270Mbps, serial digital needed for can also supporting standard definition/high-resolution data transmission speed connect Mouth (SDI).The chip is encapsulated using 48 small and exquisite pin LLP, other fine definition chip products are small by 60% in the market for volume ratio.

Fpga chip described in the utility model can select SPARTAN-3A Series FPGA chip, have and be internally integrated RocketIO^TMThe Serial Transmission Module of several Gbit and advanced SelectIO^TMXILINX SPARTAN-3A Series FPGA energy Completely a low cost, low-power consumption and flexible development platform are provided for SDI physical layer, DVB-ASI physical layer. XILINXSPARTAN-3A has differential pair abundant and multiple digital dock managers (DCM), and each pair of difference IO support is up to The data of 640Mbit/s are transmitted.

Hardware configuration based on the utility model, the utility model can choose the following software of load:

The physical layer realization of SDI will meet the standard-definition digital video data of SMPTE259M standard, meet SMPTE292M's High-definition digital video data and SMPTE424 high-definition digital video data and the digital audio-frequency data for meeting AES3-2003 standard Being packaged framing respectively is SD-SDI data, HD-SDI data.In FPGA, the physical interface of high speed SDI IP kernel can detect automatically And lock received video data stream.The physical layer of SDI realizes that the main TRS/CRC/EDH for completing parallel video data flow is inserted Enter, embedding audio, scrambling, 20:5 multiplexing, rate selection, the functions such as parallel-serial conversion and driving.

In order to reduce shake when sdi signal is serially sent, it is necessary that TX PLL, which selects the reference clock of a low jitter, , clock generator described in the utility model can select LMK03000C chip solution.The effect of driver is driving SDI Output signal makes it abide by the electrical code that need to meet specified in SMPTE standard in Coaxial Cables.Although for can The electric requirement of the SD-SDI of transmission, HD-SDI signal is essentially identical, but the difference of their rise time and fall time is right Drive performance proposes different requirements.Therefore, the SDI driver an of multi tate has been used in present design, it The sdi signal that voltage conversioning rate is different under a variety of different transmission rates can adaptively be driven.

It, only need to be by the eight bit data of Mpeg2 transport stream and a TS code rate transmission clock input in the cataloged procedure of ASI To FPGA.FIFO is written with TS bit rate clock in the data received by FPGA.FPGA is searching the long packet header of 188 byte packets Start to write data into FIFO after 0x47, while monitoring the half-full signal HF of FIFO, by the reading enable signal of FIFO if half-full It raises, and reads data from FIFO at this time and complete to encode to 8B/10B coding module.

System receives MPEG transmission packet in a manner of byte of sync, and received reference clock is using fixed 27MHz Clock frequency.Then, 8B/10B coding is carried out to byte, the word of a 10bit is generated to each 8bit byte of appearance, is made These 10bit words pass through the parallel/serial conversion to fix output bit rate 270Mbps work.

Using the circuit of the utility model, need to note also following fabric swatch item:

When circuit fabric swatch in view of the signal between used high speed fpga chip and LMH0040 chip using LVDS signal, so needing to pay attention to the following when fabric swatch: selecting four laminate fabric swatch based on the considerations of cost；Differential pair line spacing Less than or equal to line width；Short-term, straight line are walked, the mistake hole count in wiring is reduced；It must be noted that there are good reference planes, to not Cannot be too small with the pitch requirements interval between differential lines, it at least should be greater than 3~5 times of differential lines spacing, when necessary in different differences Between separated time pair plus the isolation of ground hole is to prevent the crosstalk mutually asked；Because selected four laminates be routed, then very possible LVDS and TTL uses same layer cabling, then the distance of LVDS and TTL should be remote enough, at least should be greater than 3~5 times of differential lines spacing； LVDS differential signal cannot across plane segmentation because transmission line across partitioning portion can cause to hinder because reference planes are lacked Anti- is discontinuous；The build-out resistor of receiving end will be as close as possible to since LMH0040 has built-in to the distance for receiving pin With 100 Ω of resistance, so this can be saved on external circuit；Signal impedance is 100 Ω；The impedance of cabling is normally controlled in 100Ω。

Claims (2)

1. being used for transmission the transmitting line of SDI and ASI data, which is characterized in that including a bnc interface, one can be right respectively Driving circuit, a fpga chip, a clock generator and one and the string turn that SDI and DVB-ASI data are driven Change circuit；The fpga chip is electrically connected with the driving circuit, clock generator and parallel-to-serial converter respectively, the drive Dynamic circuit is electrically connected with the bnc interface.

2. being used for transmission the transmitting line of SDI and ASI data as described in claim 1, which is characterized in that the driving circuit Including LMH0040 chip, the fpga chip is SPARTAN-3A Series FPGA chip, and the clock generator includes LMK03000C chip.