CN208738234U - Array of capacitors structure and semiconductor devices - Google Patents
Array of capacitors structure and semiconductor devices Download PDFInfo
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- CN208738234U CN208738234U CN201821635933.8U CN201821635933U CN208738234U CN 208738234 U CN208738234 U CN 208738234U CN 201821635933 U CN201821635933 U CN 201821635933U CN 208738234 U CN208738234 U CN 208738234U
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Abstract
The utility model provides a kind of array of capacitors structure and semiconductor devices; increase by a boundary protection layer being formed by insulating materials on the basis of the boundary of original capacitor array structure; can by conductive contact plug manufacture craft due to the out-of-flatness of capacitor array structure boundary generate crack separated with capacitor array structure boundary; to avoid the problem for causing conductive contact plug Yu the short circuit of capacitor array structure boundary because of the crack, the reliability of capacitor element is improved.
Description
Technical field
The utility model relates to technical field of semiconductors, in particular to a kind of array of capacitors structure and semiconductor devices.
Background technique
Dynamic RAM (Dynamic Random Access Memory, referred to as: DRAM) is commonly used in computer
Semiconductor storage unit, be made of many duplicate storage units, each storage unit generally includes capacitor and transistor,
The grid of transistor is connected with wordline, drain be connected with bit line, source electrode is connected with capacitor；Voltage signal in wordline can be controlled
Transistor processed opens or closes, and then reads the data information of storage in the capacitor by bit line, or will by bit line
Data information is written in capacitor and is stored.With the lasting evolution of DRAM making technology, integrated level is continuously improved, device
Size is constantly miniature, and the horizontal area of the storage array that storage unit is formed on substrate is also smaller and smaller.In order to enable DRAM
In capacitor can be improved or maintain sufficiently high capacitance, it will usually increase the lower electrode (bottom in capacitor
Electrode height), to increase lower contact area between electrode and capacitor dielectric layer.However, with lower electrode height
Increase, it is right so that the depth-width ratio of lower electrode also increases accordingly, and then the problem of easily cause lower electrode bending to deform or collapse
Device area reliability impacts.
Referring to FIG. 1, at present in existing DRAM capacitor array structure forming process, it is general by adding electrode
Laterally consecutive supporting layer (including bottom support layer 111, middle support layer 112, top support layer 113) increases stability, still
This will cause the boundary out-of-flatness of the array of capacitors structure of device region 100A, so that subsequent technique is to array of capacitors knot
It is configured to adverse effect, and then influences the reliability of DRAM.Such as in subsequent formation conductive contact plug 102 (CT) technique
In, it can be in the top of array of capacitors structure and its peripheral interlayer dielectric layer to accommodate conductive contact plug for making
102 contact hole, and the top of etched capacitor array structure and its peripheral interlayer dielectric layer form contact hole, later
Fill conductive metal material in the contact hole to form conductive contact plug 102.However, with the diminution of device size, capacitor
The distance between the top of device array structure and its conductive contact plug 102 of periphery also become very little, this makes capacitor battle array
Layer between the part from the uneven integral boundary convexity of array structure to array of capacitors structure peripheral and contact hole side wall of contact hole of
Between the thickness of dielectric layer become very thin, during etching the interlayer dielectric layer and forming the contact hole of these peripheries, electricity
The interlayer dielectric layer unbalance stress of the uneven integral boundary periphery of vessel array structure is easy so that contact hole side wall generates crack
(crack), when filling 102 corresponding conductive metal material of conductive contact plug later, on the one hand can aggravate the increase in crack and
Directly on cracking to the uneven integral boundary of array of capacitors structure, on the other hand the conductive metal material of filling, which can be also filled into, splits
In seam, in turn result between the conductive contact plug 102 to be formed and array of capacitors boundary or conductive contact plug 102 directly
Short circuit occurs, the reliability of DRAM is impacted.Therefore, protection is carried out to capacitor array boundary to be necessary.
Utility model content
The purpose of this utility model is to provide a kind of array of capacitors structure and semiconductor devices, can be to capacitor array
The boundary of structure carries out insulation protection, and plug caused by the crack for stopping subsequent conductive contact plunger technique to be formed and capacitor battle array
Array structure boundary short circuit problem, and then improve device reliability.
In order to solve the above technical problems, the utility model provides a kind of array of capacitors structure, comprising:
Substrate has the device region for being used to form array of capacitors；
Lower electrode layer is arranged on the device region of the substrate, and the lower electrode layer is multiple with being arranged in array
Tubular structure；
Capacitor dielectric layer is covered on the surfaces externally and internally of the lower electrode layer；
Upper electrode layer is covered on the surface of the capacitor dielectric layer；
Top electrode filled layer；It is covered on the surface of the upper electrode layer and fills up the gap in the upper electrode layer, institute
State the lateral wall that top electrode filled layer has uneven pattern；And
Boundary protection layer, the boundary protection layer are at least covered on the lateral wall of the top electrode filled layer, and
The boundary protection layer is insulating materials.
Optionally, the array of capacitors structure further includes top electrode coating, and the top electrode coating is covered on
On the surface of the top electrode filled layer, and have on the outside of out-of-flatness corresponding with the lateral wall of the top electrode filled layer
Wall；And the capacitor dielectric layer, the upper electrode layer, the top electrode filled layer and the top electrode coating successively extend
It is covered on the surface of the entire device region；The boundary protection layer at least covers the injustice of the top electrode coating
On whole lateral wall.
Optionally, the boundary protection layer be covered on the top electrode coating upper surface and the out-of-flatness lateral wall
On.
Optionally, the substrate also has the external zones positioned at the device region periphery, is formed with and leads in the external zones
Electric structure；The array of capacitors structure further includes interlayer dielectric layer, and the interlayer dielectric layer is not placed only in the side
On the surface of the device region of boundary's protective layer, also extend on the external zones；It is formed with and is located in the interlayer dielectric layer
Conductive contact plug in the device region and the conductive contact plug in the external zones, leading in the device region
The top electrode filled layer being in electrical contact in plug and the device region is in electrical contact, the conductive contact plug in the external zones with
Conductive structure electrical contact in the external zones.
Optionally, the boundary protection layer extends on the surface of the external zones.
Optionally, the array of capacitors structure further includes cross-brace layer, and the cross-brace layer is located at the device
On the substrate in part area and lateral connection described in lower electrode layer multiple tubular structures, wherein the top electrode filled layer
The uneven pattern of the lateral wall corresponds to the cross-brace layer outside the tubular structure of the lower electrode.
Optionally, the cross-brace layer includes a top support layer, at least one layer of middle support layer and a base layer support
Layer, the top support layer are located at the top periphery of the tubular structure of the lower electrode layer, and the middle support layer is located at described
The intermediate position of the tubular structure of lower electrode layer, the base layer support layer are located at outside the bottom of the tubular structure of the lower electrode layer
It encloses.
Optionally, multiple capacitance contact nodes are also formed in the substrate, the lower electrode layer is in each tubular
The bottom of structure is connected with the corresponding contact node.
The utility model also provides a kind of semiconductor devices, including array of capacitors structure described in the utility model.
Compared with prior art, a kind of array of capacitors structure provided by the utility model and semiconductor devices, original
Increase by the boundary protection layer that is formed by insulating materials on the basis of the boundary of capacitor array structure, it can will be in conductive contact plug
Since the crack that the out-of-flatness of capacitor array structure boundary generates is separated with capacitor array structure boundary in manufacture craft, to keep away
The problem for exempting to cause conductive contact plug Yu the short circuit of capacitor array structure boundary because of the crack, improves the reliable of capacitor element
Property.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section of an array of capacitors structure in the prior art.
Fig. 2 is the flow diagram of the preparation method of the array of capacitors structure of an embodiment of the present invention.
Fig. 3 a is plan structure of an embodiment of the present invention after executing the step S1 in preparation method shown in Fig. 2
Schematic diagram.
Fig. 3 b is the schematic diagram of the section structure of the AA ' line in Fig. 3 a.
Fig. 4 a is the overlooking structure diagram after executing the step S2 in preparation method shown in Fig. 2.
Fig. 4 b is the schematic diagram of the section structure of the AA ' line in Fig. 4 a.
Fig. 5 is cross-section structure of an embodiment of the present invention after executing the step S3 in preparation method shown in Fig. 2
Schematic diagram.
Fig. 6 is cross-section structure of an embodiment of the present invention after executing the step S4 in preparation method shown in Fig. 2
Schematic diagram.
Fig. 7 is cross-section structure of an embodiment of the present invention after executing the step S5 in preparation method shown in Fig. 2
Schematic diagram.
Fig. 8 is cross-section structure of an embodiment of the present invention after executing the step S6 in preparation method shown in Fig. 2
Schematic diagram.
Fig. 9 is that an embodiment of the present invention sedimentary boundaries in executing the step S7 in preparation method shown in Fig. 2 are protected
The schematic diagram of the section structure after sheath.
Figure 10 a is that an embodiment of the present invention etches boundary in executing the step S7 in preparation method shown in Fig. 2
Protective layer forms the overlooking structure diagram after side wall.
Figure 10 b is that an embodiment of the present invention etches boundary in executing the step S7 in preparation method shown in Fig. 2
Protective layer forms the schematic diagram of the section structure after side wall.
Figure 11 a is etched in executing the step S7 in preparation method shown in Fig. 2 for an embodiment of the present invention and is powered on
Overlooking structure diagram after pole coating to capacitor dielectric layer.
Figure 11 b is etched in executing the step S7 in preparation method shown in Fig. 2 for an embodiment of the present invention and is powered on
The schematic diagram of the section structure after pole coating to capacitor dielectric layer.
Figure 12 is cross-section structure of an embodiment of the present invention after executing the step S8 in preparation method shown in Fig. 2
Schematic diagram.
Figure 13 a is that another embodiment of the utility model etches side in executing the step S7 in preparation method shown in Fig. 2
Overlooking structure diagram after boundary's protective layer.
Figure 13 b is section of another embodiment of the utility model after executing the step S7 in preparation method shown in Fig. 2
Structural schematic diagram.
Figure 14 is section knot of another embodiment of the utility model after executing the step S8 in preparation method shown in Fig. 2
Structure schematic diagram.
Figure 15 is section knot of the another embodiment of the utility model after executing the step S6 in preparation method shown in Fig. 2
Structure schematic diagram.
Figure 16 a is vertical view of the another embodiment of the utility model after executing the step S7 in preparation method shown in Fig. 2
Structural schematic diagram.
Figure 16 b is section of the another embodiment of the utility model after executing the step S7 in preparation method shown in Fig. 2
Structural schematic diagram.
Figure 17 is section knot of the another embodiment of the utility model after executing the step S8 in preparation method shown in Fig. 2
Structure schematic diagram.
Wherein, appended drawing reference is as follows:
100- substrate；
100A- device region；
100B- external zones；
The crack 103-；
102,170- conductive contact plug；
101- capacitance contact node；
111- base layer support layer；
112- middle support layer；
113- top support layer；
The first sacrificial layer of 121-；
The second sacrificial layer of 122-；
110- capacitor hole；
Electrode under 130-；
131- capacitor dielectric layer；
132- upper electrode layer；
133- top electrode filled layer；
140- top electrode coating；
150- boundary protection layer；
160- interlayer dielectric layer；
The boundary of E1- array of capacitors；
The boundary of E2- device region.
Specific embodiment
To be clearer and more comprehensible the purpose of this utility model, feature, with reference to the accompanying drawing to the technical side of the utility model
Case is described in detail, however, the utility model can be realized with different forms, it should not be to be confined to the implementation
Example.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to conveniently, lucidly
Aid in illustrating the purpose of the utility model embodiment.
Referring to FIG. 2, an embodiment of the present invention provides a kind of preparation method of array of capacitors structure, including following
Step:
S1 provides a substrate with device region, forms alternately stacked sacrificial layer and supporting layer on the substrate；
S2 etches the supporting layer and the sacrificial layer, to form multiple capacitor holes in the device region, and the electricity
Hold hole and sequentially passes through the supporting layer and the sacrificial layer to expose the surface of the substrate；
S3 forms lower electrode layer on the side wall and bottom wall in the capacitor hole, to form multiple tubular structures；
S4 removes the sacrificial layer and retains the supporting layer, and the supporting layer connects multiple institutes of the lower electrode layer
State tubular structure；
S5 sequentially forms capacitor dielectric layer and upper electrode layer on the surfaces externally and internally of the lower electrode layer；
S6 forms top electrode filled layer on the surface of the upper electrode layer, and the top electrode filled layer fills up on described
Gap in electrode layer, the top electrode filled layer have the lateral wall of uneven pattern；
S7 forms boundary protection layer on the top electrode filled layer, and the boundary protection layer is at least covered on described
On the lateral wall of electrode filled layer, and the boundary protection layer is insulating materials；
S8 forms interlayer dielectric layer on the substrate with the boundary protection layer, and forms conductive contact and plug in institute
It states in interlayer dielectric layer, the conductive contact plug in the device region connects with the top electrode filled layer electricity in the device region
Touching.
Below with reference to the corresponding structural schematic diagram of each step, array of capacitors in the present embodiment is further explained
The preparation method of structure.
Fig. 3 a and Fig. 3 b is please referred to, in step sl, provides a substrate 100, the substrate 100 includes to be used to form capacitor
The device region 100A of device array and positioned at the periphery device region 100A external zones 100B, the device region 100A with it is described
External zones 100B can be kept apart by fleet plough groove isolation structure (not shown).The material of the substrate 100 can for monocrystalline silicon,
Polysilicon, unformed silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc. or other materials well known by persons skilled in the art
Material.Multiple capacitance contact nodes 101, the capacitance contact node 101 are also formed in the substrate 100 of the device region 100A
It is electrically connected with the subsequent lower electrode layer for being formed by capacitor；Conductive knot is also formed in the substrate 100 of external zones 100B
Structure (can be transistor etc., not shown), for being in electrical contact with subsequent conductive contact plug.Certainly, in the substrate 100 also
Other device architectures such as fleet plough groove isolation structure, transistor can be formed, the utility model does not limit this.It can pass through
The techniques such as chemical vapor deposition, spin coating sequentially form base layer support layer 111, the first sacrificial layer on the surface of the substrate 100
121, middle support layer 112, the second sacrificial layer 122 and top support layer 113, i.e., the alternately laminated sacrificial layer on substrate 100
And supporting layer.Wherein 111 one side of base layer support layer is used to carry out bottom support to the lower electrode layer being subsequently formed, on the other hand
It is also used to the elements such as the internal element at isolation liner bottom 100 and the capacitor of top.The formation process of base layer support layer 111 can be with
It is thermal oxidation technology.The material of the base layer support layer 111, middle support layer 112 and top support layer 113 including but not limited to
Silicon nitride, the first sacrificial layer 121, the second sacrificial layer 122 material including but not limited to silica.First sacrificial layer 121
Thickness definition go out the subsequent height for being formed by middle support layer 112, therefore, the thickness of first sacrificial layer 121 can root
It is adjusted according to the height and position of the middle support layer 112 of required formation.In first sacrificial layer 121 and middle support layer
In the case that 112 thickness determines, the thickness definition of second sacrificial layer 122, which goes out, subsequent is formed by top support layer 113
Height, therefore, the thickness of second sacrificial layer 122 can according to the height and position of the top support layer 113 of required formation into
Row adjustment.In the other embodiments of the utility model, in order to preferably be supported to lower electrode layer, base layer support layer 111
Two layers or more of middle support layer 112 can also be laminated between top support layer 113, have sacrifice between adjacent middle support layer
Layer is isolated.
It please refers to shown in Fig. 4 a and Fig. 4 b, in step s 2, forms multiple capacitor holes 110 on the device region 100A
In sacrificial layer and the supporting layer, the capacitor hole 110 exposes the surface of the substrate 100 of the 1 device region 100A, is used for shape
At capacitor.Multiple capacitor holes 110 are arranged in array.Specifically, forming a mask layer (not on the top support layer 113
Diagram), the mask layer is patterned, the predetermined region for forming capacitor hole 110 is exposed, then with patterned exposure mask
Layer be exposure mask, successively to the top support layer 113, the second sacrificial layer 122, middle support layer 112, the first sacrificial layer 121 with
And base layer support layer 111 performs etching, to remove the support on the external zones 100B and device region 100A fringe region
Layer and sacrificial layer, and multiple capacitor holes 110 are formed in device region 100A, then remove the patterned mask layer.It is described
Capacitor hole 110 sequentially passes through the top support layer 113, the second sacrificial layer 122, middle support layer 112, the first sacrificial layer 121
And base layer support layer 111, the surface of the capacitance contact node 101 in substrate 100 to expose the device region 100A can
Choosing, all capacitor holes 110 are arranged in hexagonal closs packing.In addition, capacitor hole 110 can be inverted trapezoidal hole, rectangular opening etc.,
Side wall can be irregular pattern, such as have curvilinear sidewall, be not particularly limited herein.In addition, in the present embodiment, external zones
The base layer support layer 111 is also remained on 100B, for protecting external zones 100B's in subsequent capacitance device formation process
100 surface of substrate.
It is understood that due to needing to form the capacitor hole in the alternately stacked supporting layer and sacrificial layer
110, and then the lower electrode with a tubular structure can be formed on the bottom wall and side wall in the capacitor hole 110 (under i.e. subsequent
Electrode layer 130), it is seen then that the total height for being used to form the lamination in the capacitor hole 110 can define the lower electrode layer being subsequently formed
Therefore the height of each tubular structure in 130 can pass through the thickness of increase by first sacrificial layer 121 and the second sacrificial layer 122
Degree, to increase the subsequent lower electrode height for being formed by capacitor, so as to increase the lower electrode surface product of capacitor, Jin Erke
Improve the capacitance of the capacitor formed.
Please refer to shown in Fig. 5, in step s3, formed a lower electrode layer 130 be covered in the capacitor hole 110 side wall and
On the wall of bottom.The lower electrode layer 130 is located at the part in the capacitor hole 110, the pattern one of pattern and the capacitor hole 110
It causes, so that the lower electrode layer 130 being located in the capacitor hole 110 constitutes a tubular structure.Specifically, the lower electricity
Pole layer 130 can be formed on the basis of depositing operation in conjunction with flatening process, for example, it is possible, firstly, to using figures such as photoresists
Change protective layer (not shown) to protect external zones 100B, and exposes the top of the top support layer 113 in device region 100A
The surface in surface and capacitor hole 110；Then, an electrode material is formed using techniques such as physical vapour deposition (PVD) or chemical vapor depositions
For the bed of material on the exposed surface of the patterned protective layer and device region 100A, the electrode material layer covers the capacitor hole
110 bottom and side wall, and cover the graphical protection of the top support layer 113 and external zones 100B of the device region 100A
Layer top surface；Then, flatening process (for example, chemical mechanical milling tech CMP) is executed, removes and is located at institute in electrode material layer
The part for stating 113 top of top support layer, to make remaining electrode material layer be made only in the capacitor hole 110, with structure
At the lower electrode layer 130 with multiple tubular structure 110a, the patterned protective layer is removed later.In addition, in the present embodiment
In, the capacitance contact node 101 is exposed by the capacitor hole 110, so that being formed by lower electrode layer 130
The bottom of tubular structure 110a can be electrically connected with the capacitance contact node 101.Further, the lower electrode layer 130
It can be polysilicon electrode or metal electrode.When lower electrode layer 130 is metal electrode, can also using titanium nitride (TiN) and
Ti stepped construction.It, can be using the polycrystalline silicon material shape of zero doping and/or doping when lower electrode layer 130 is polysilicon electrode
At.
It please refers to shown in Figures 5 and 6, in step s 4, removes the sacrificial layer described unless each and retain each support
Layer, all supporting layers form cross-brace layer, with the outer of multiple tubular structures of lower electrode layer 130 described in lateral connection
Wall, to be supported on the side wall of each tubular structure to lower electrode layer 130.Specifically, the top support layer 113
Positioned at the top periphery of multiple tubular structures of the lower electrode layer 130, the middle support layer 112 is located at the lower electrode layer
The intermediate position of 130 multiple tubular structures, base layer support layer 111 are located at multiple tubular structures of the lower electrode layer 130
Bottom periphery.Wherein, the detailed process of step S4 includes: to form the first opening (not shown) Yu Suoshu top support layer 113 simultaneously
Expose second sacrificial layer 122；Second sacrificial layer 122 can be removed using wet-etching technology etching；Form the
Two are opened in the middle support layer 112 to expose first sacrificial layer 121；It is etched and is removed using wet-etching technology
First sacrificial layer 121；Wherein, first opening is only overlapped with a capacitor hole 110 or described in one
First opening is overlapping with multiple capacitor holes 110 simultaneously；One second opening is only handed over a capacitor hole 110
Folded or second opening is overlapping with multiple capacitor holes 110 simultaneously.In addition, second opening can be with institute
It is perfectly aligned to state the first opening.
It please refers to shown in Fig. 7, in step s 5, firstly, using chemical vapor deposition process or atom layer deposition process etc.
A capacitor dielectric layer 131 is formed in the surface that the surfaces externally and internally of the lower electrode layer 130 and each supporting layer expose；
Then, a upper electrode layer 132 is formed in the inner surface and the outer surface of the capacitor dielectric layer 131.Wherein, the capacitor dielectric layer
The inner surface and the outer surface of the tubular structure 110a of the 131 covering lower electrode layers 130, to make full use of lower electrode layer 130
Two apparent surfaces constitute the capacitor with larger electrode surface area.Preferably, the capacitor dielectric layer 131 can be gold
Belong to the high-K dielectric layers such as oxide.Further, the capacitor dielectric layer 131 is multilayered structure, for example, oxidation Kazakhstan-zirconium oxide
Double-layer structure.The upper electrode layer 132 can may be multilayered structure for single layer structure, when the upper electrode layer 132 is
When single layer structure, for example, polysilicon electrode, or metal electrode, when upper electrode layer 132 is metal electrode, such as can
To be formed using titanium nitride (TiN).Inside and the tubular structure of the upper electrode layer 132 in the correspondence tubular structure
It is external to constitute capacitor with the capacitor dielectric layer 131 and the lower electrode layer 130.In addition, in device region 100A
On fringe region (i.e. the borderline region of capacitor hole array), due to cross-brace layer (i.e. middle support layer 112, top support layer
113) presence, the capacitor dielectric layer 131 and the upper electrode layer 132 all have the side wall construction of uneven pattern, institute
The side wall construction of uneven pattern is stated corresponding to the intermediate supports outside the tubular structure cylinder of the lower electrode layer 130
Layer 112, top support layer 113, so that the upper electrode layer 132 is in the device region 100A fringe region (i.e. capacitor hole
The borderline region of array) on part, the corresponding middle support layer 112, top support layer 113 are far from the lower electrode layer
130 direction protrusion, makes the array of capacitors boundary out-of-flatness in device region 100A.In addition, the capacitor is situated between in the present embodiment
Matter layer 131 and the upper electrode layer 132 also successively extend over the base layer support layer 111 retained on the external zones 100B
On surface.
It please refers to shown in Fig. 8, it in step s 6, can be first using chemical vapor deposition process in the upper electrode layer 132
Surface forms a top electrode filled layer 133, and the top electrode filled layer 133 fills up the gap between the upper electrode layer 132,
That is the top electrode filled layer 133 fills the gap between the tubular structure of full phase neighbour and covers the structure of above-mentioned formation.
Preferably, the material of the top electrode filled layer 133 includes undoped or boron doped polysilicon.Later, using physics gas
Mutually the techniques such as deposition form top electrode coating 140 on the top electrode filled layer 133, and the top electrode coating 160 is excellent
It is selected as laminated construction, (its material includes but unlimited including the conductive metal layer for connecting 132 surface of top electrode filled layer
In tungsten) and for avoid conductive metal layer aoxidize oxide layer (its material is including but not limited to silica).Equally, on described
Electrode filled layer 133 and the top electrode coating 140 all have the side wall construction of uneven pattern, the uneven shape
The side wall construction of looks corresponds to the middle support layer 112 and top support layer 113.This completes the systems of array of capacitors
Make.
Because added with cross-brace layer (i.e. bottom support layer 111, middle support layer 112 and top between lower electrode layer
Layer supporting layer 113), therefore the stability of above-mentioned array of capacitors is improved, but the presence of cross-brace layer makes electricity
The boundary of vessel array is rough out-of-flatness pattern, for sinking into contact hole in subsequent conductive plugs technique
When product and filling conductive metallic material, (concave-convex side) forms crack at the out-of-flatness on array of capacitors boundary, causes to be formed
Conductive contact plug and the short circuit of capacitor array boundary, influence the reliability of memory finally manufactured.To avoid this problem,
Being formed in step S7, there is the boundary protection layer of insulating properties to be at least covered in the uneven integral boundary of the array of capacitors, will
Subsequent technique potential fracture and array of capacitors boundary keep apart, so that conductive contact caused by the crack be avoided to insert
Short circuit problem between plug and capacitor array boundary, provides the reliability of device.
In an embodiment of the utility model, side only is formed in the uneven integral boundary of array of capacitors in the step s 7
Boundary's protective layer 150, detailed process include:
Firstly, referring to FIG. 9, by process deposits insulating materials such as chemical vapor depositions in the top electrode coating
On 140 surface, have the boundary protection layer 150 of insulating properties in the side wall of the top electrode coating 140 and top table to be formed
On face, the material of the boundary protection layer 150 includes at least one of silicon nitride, fire sand, silicon oxynitride.The boundary
Part of the protective layer 150 on the fringe region of the device region 100A also has the uneven whole side of the corresponding cross-brace layer
Wall.At this point, the boundary protection layer 150, top electrode coating 140, top electrode filled layer 133, upper electrode layer 132 and capacitor
Dielectric layer 131 is from all surfaces that device region 100A continuously extends to external zones 100B.
Then, Figure 10 a, 10b are please referred to, the boundary protection layer 150 can be etched using side wall etching technics, thus
Remove external zones 100B, the outermost edge region of device region 100A and the top electrode of device region 100A (i.e. array of capacitors area)
Boundary protection layer 150 on 140 upper surface of coating, remaining boundary protection floor 150 are placed only in array of capacitors area not
On smooth boundary (the out-of-flatness lateral wall of the top electrode coating 140 in the i.e. described device region 100A), as side
Boundary's side wall.At this point it is possible to the boundary E1 of array of capacitors is obtained, the region between boundary E1 and the boundary E2 of device region 100A
It is exactly the most fringe region of device region 100A.
Then, Figure 11 a, 11b are please referred to, light can be passed through with the contact hole mask plate on the aid of capacitor array and further
Carve, etching technics come remove the top electrode coating 140 on external zones 100A, top electrode filled layer 133, upper electrode layer 132 with
And capacitor dielectric layer 131, the boundary E2 of device region 100A is thus obtained, the boundary E2 can be with the lower electrode layer 130
Tubular structure is arranged in parallel in vertical direction, can also be arranged with the gradient of substrate 100 at an angle.
The boundary protection layer 150 that this method is formed is only a kind of sidewall structure, in protective condenser array boundary
The influence to array of capacitors middle section can also be minimized simultaneously.
Step S8 can be executed later, with the array of capacitors side wall of boundary side wall and top surface, boundary protection layer
Interlayer dielectric layer 160 is formed on the fringe region and external zones 100B of the 150 device region 100A exposed and is located at interlayer
Conductive contact plug 170 in dielectric layer 160.Specifically, Figure 12 is please referred to, it is possible, firstly, to using coating or chemical vapor deposition
Product technique simultaneously combines further top flattening technique, to form interlayer dielectric layer 160 in the bottom of the external zones 100B
The top electrode coating 140 that the boundary protection layer 150 and boundary protection layer 150 of supporting layer 111 and device region 100A expose
Surface on, and interlayer dielectric layer 160 is sufficiently thick, can be buried in boundary protection layer 150 and top electrode coating 140
It is interior, and there are flat sidewall surfaces and top surface.Then, contact hole etching device region 100A and external zones 100B can be passed through
Interlayer dielectric layer 160, to form the contact hole (not shown) that is located in device region 100A and external zones 100B, and device
Contact holes exposing in area 100A goes out the top surface of top electrode filled layer 133, and the contact holes exposing in external zones 100B goes out periphery
The upper surface of conductive structure (e.g. transistor etc.) in the substrate 100 of area 100B.It is then possible to using plating, sputtering etc.
Technique fills conductive metal material (its material includes but is not limited to tungsten) into each contact hole, until contact hole is filled up,
And extra conductive metal material is further removed by CMP process, to form conductive contact plug 170
In the interlayer dielectric layer 160 on the device region 100A and the external zones 100B, leading in the device region 100A
The upper surface for being in electrical contact the top electrode filled layer 133 in plug 170 and the device region 100A is in electrical contact, the external zones
Conductive contact plug 170 in 100B and the conductive structure in the substrate 100 of the external zones 100B are in electrical contact.
In another embodiment of the utility model, Fig. 9, Figure 13 a and Figure 13 b are please referred to, in the step s 7 in capacitor
Boundary protection layer 150 is formed in the uneven integral boundary and top surface of array, detailed process includes:
Firstly, referring to FIG. 9, by process deposits insulating materials such as chemical vapor depositions in the top electrode coating
On 140 surface, have the boundary protection layer 150 of insulating properties in the side wall of the top electrode coating 140 and top table to be formed
On face, the material of the boundary protection layer 150 includes at least one of silicon nitride, fire sand, silicon oxynitride.The boundary
Part of the protective layer 150 on the fringe region of the device region 100A also has the uneven whole side of the corresponding cross-brace layer
Wall.At this point, the boundary protection layer 150, top electrode coating 140, top electrode filled layer 133, upper electrode layer 132 and capacitor
Dielectric layer 131 is from all surfaces that device region 100A continuously extends to external zones 100B.
Then, Figure 13 a and Figure 13 b is please referred to, can be led to the contact hole mask plate on the aid of capacitor array and further
Cross photoetching, etching technics removes the boundary protection layer 150 on external zones 100A, top electrode coating 140, top electrode filled layer
133, upper electrode layer 132 and capacitor dielectric layer 131, thus obtain the boundary E2 of device region 100A, and the boundary E2 can be with
The tubular structure of the lower electrode layer 130 is arranged in parallel in vertical direction, can also set with the gradient of substrate 100 at an angle
It sets.
This method can form the boundary of boundary protection layer 150 and device region 100A, work by one of etching technics
Skill is simplified, and remaining boundary protection layer 150 not only can protect the uneven integral boundary (i.e. side wall) of array of capacitors, moreover it is possible to
The entire top surface of protective condenser array increases the protection of array of capacitors, be conducive to device reliability into one
Step improves.
Step S8 can be continued to execute later, in array of capacitors and external zones with boundary protection layer 150
Interlayer dielectric layer 160 and the conductive contact plug 170 in interlayer dielectric layer 160 are formed on 100B.Specifically, it please refers to
Figure 14 carrys out forming layer it is possible, firstly, to using coating or chemical vapor deposition process and combine further top flattening technique
Between dielectric layer 160 in the bottom support layer 111 of the external zones 100B and the surface of the boundary protection layer 150 of device region 100A
On (i.e. out-of-flatness side wall and top surface), and interlayer dielectric layer 160 is sufficiently thick, can fill up the gap in boundary protection layer 150
And in being completely buried in boundary protection layer 150, and there are flat sidewall surfaces and top surface.Then, contact can be passed through
The interlayer dielectric layer 160 of hole etched features area 100A and external zones 100B are located at device region 100A and external zones to be formed
Contact hole (not shown) in 100B, and the contact holes exposing in device region 100A goes out the top surface of top electrode filled layer 133, outside
Enclose the upper table for the conductive structure (e.g. transistor etc.) that the contact holes exposing in area 100B goes out in the substrate 100 of external zones 100B
Face.It is then possible to fill conductive metal material into each contact hole using techniques such as plating, sputterings, (its material includes
But it is not limited to tungsten), until filling up contact hole, and extra metallic conduction material is further removed by CMP process
Material, to form conductive contact plug 170 in the interlayer dielectric layer on the device region 100A and the external zones 100B
The top electrode filled layer in conductive contact plug 170 and the device region 100A in 160, in the device region 100A
133 upper surface is in electrical contact, the substrate 100 of conductive contact plug 170 and the external zones 100B in the external zones 100B
In conductive structure electrical contact.
In the another embodiment of the utility model, Figure 15, Figure 16 a and Figure 16 b are please referred to, it in the step s 7, can be with
Using another method for being different from above-described embodiment, boundary is formed in the uneven integral boundary and top surface of array of capacitors
Protective layer 150, detailed process include:
Firstly, please referring to Figure 15, photoetching, quarter can be passed through with the contact hole mask plate on the aid of capacitor array and further
Etching technique removes the top electrode coating 140 on external zones 100A, top electrode filled layer 133, upper electrode layer 132 and capacitor
Dielectric layer 131, thus obtains the boundary E2 of device region 100A, and the boundary E2 can be with the tubular knot of the lower electrode layer 130
Structure is arranged in parallel in vertical direction, can also be arranged with the gradient of substrate 100 at an angle.
Then, Figure 16 a, 16b are please referred to, is covered by the process deposits such as chemical vapor deposition insulating materials in the top electrode
On 111 surface of bottom support layer of cap rock 140 and the external zones 100B, to form the boundary protection layer 150 with insulating properties
In on the side wall and top surface of the top electrode coating 140 and in the bottom support layer 111 of external zones 100B, the boundary
The material of protective layer 150 includes at least one of silicon nitride, fire sand, silicon oxynitride.The boundary protection layer 150 is in institute
State the out-of-flatness side wall that part on the fringe region of device region 100A also has the corresponding cross-brace layer.At this point, the side
Boundary's protective layer 150, top electrode coating 140, top electrode filled layer 133, upper electrode layer 132 and capacitor dielectric layer 131 from
Device region 100A is continuously extended on all surfaces of external zones 100B.
This method first etches the boundary of device region 100A, and the boundary protection layer 150 re-formed, technique is simplified,
And the boundary protection layer 150 formed not only can protect the array of capacitors in device region 100A, additionally it is possible to external zones 100B
In structure protected, prevent subsequent conductive contact plug process from causing adverse effect to it.
Step S8 can be continued to execute later, in array of capacitors and external zones with boundary protection layer 150
Interlayer dielectric layer 160 and the conductive contact plug 170 in interlayer dielectric layer 160 are formed on 100B.Specifically, it please refers to
Figure 17 carrys out forming layer it is possible, firstly, to using coating or chemical vapor deposition process and combine further top flattening technique
Between dielectric layer 160 on the surface (i.e. out-of-flatness side wall and top surface) of the boundary protection layer 150, and 160 foot of interlayer dielectric layer
Enough thickness can fill up the gap in the out-of-flatness side wall of the boundary protection layer 150 of device region 100A and by boundary protection layer 150
In being completely buried in, interlayer dielectric layer 160 finally has flat sidewall surfaces and top surface.Then, contact hole can be passed through
The interlayer dielectric layer 160 of etched features area 100A and external zones 100B is located at device region 100A and external zones to be formed
Contact hole (not shown) in 100B, and the contact holes exposing in device region 100A goes out the top surface of top electrode filled layer 133, outside
Enclose the upper table for the conductive structure (e.g. transistor etc.) that the contact holes exposing in area 100B goes out in the substrate 100 of external zones 100B
Face.It is then possible to fill conductive metal material into each contact hole using techniques such as plating, sputterings, (its material includes
But it is not limited to tungsten), until filling up contact hole, and extra metallic conduction material is further removed by CMP process
Material, to form conductive contact plug 170 in the interlayer dielectric layer on the device region 100A and the external zones 100B
The top electrode filled layer in conductive contact plug 170 and the device region 100A in 160, in the device region 100A
133 upper surface is in electrical contact, the substrate 100 of conductive contact plug 170 and the external zones 100B in the external zones 100B
In conductive structure electrical contact.
In the above embodiments, the deposition thickness of the boundary protection layer 150 is relatively thin, is not enough to fill up top electrode covering
The gap of the out-of-flatness side wall of layer 140, but the technical solution of the utility model is not merely defined in this, in the utility model
Other embodiments in, the deposition thickness of the boundary protection layer 150 can thicken, and can fill up top electrode coating
The gap of 140 out-of-flatness side wall, so that array of capacitors boundary becomes smooth side wall, so as to connect subsequent conduction
A possibility that generating crack because of cross-brace layer in touching plug process is preferably minimized, farthest to avoid the crack from making
At conductive contact plug and capacitor array boundary between short circuit problem.
In conclusion the preparation method of the array of capacitors structure of the utility model, is being conductively connected touching plug process
Before, it is initially formed a borderline boundary protection layer of out-of-flatness for being at least covered on the array of capacitors, to reduce subsequent lead
Be in electrical contact plug process in into contact hole fill conductive metal material when due to array of capacitors uneven integral boundary and shape
A possibility that at crack, while the uneven integral boundary that would be possible to the crack generated and the array of capacitors separates, with
Short circuit problem between the conductive contact plug avoided the formation of and array of capacitors boundary improves device reliability.
Fig. 2 to Figure 17 is please referred to, the utility model also provides a kind of preparation method of semiconductor devices, comprising: using this
The preparation method of the array of capacitors structure of utility model prepares array of capacitors structure.The semiconductor devices of the utility model
Preparation method, the preparation suitable for semiconductor memories such as dynamic RAMs.Due to the semiconductor devices of the utility model
Preparation method, array of capacitors is prepared using the preparation method of the array of capacitors structure of the utility model of the utility model
Structure, therefore the semiconductor devices with higher reliability can be prepared.
Please refer to Figure 12, an embodiment of the present invention also provides a kind of array of capacitors structure, including substrate 100, under
Electrode layer 130, capacitor dielectric layer 131, upper electrode layer 132, top electrode filled layer 133, top electrode coating 140, boundary protection
Layer 150, cross-brace layer, interlayer dielectric layer 160 and the conductive contact plug 170 for being used to support the lower electrode layer 130.
Specifically, the substrate 100 has the device region 100A and external zones 100B positioned at the periphery device region 100A,
The device region 100A and external zones 100B can be kept apart by fleet plough groove isolation structure (not shown).The substrate
100 material can be monocrystalline silicon, polysilicon, unformed silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc. or ability
Other materials known to field technique personnel.It is also formed in the substrate 100 of the device region 100A multiple be arranged in array
Capacitance contact node 101, the capacitance contact node 101 are electrically connected with lower electrode layer 130；In the substrate of external zones 100B
It is also formed with conductive structure (can be transistor etc., not shown) in 100, is in electrical contact for corresponding conductive contact plug 170.
The lower electrode layer 130 is arranged on the substrate 100 of the device region 100A, and the lower electrode layer 130 has
Multiple tubular structures, the tubular structure can be inverted trapezoidal hole, rectangular opening etc., and side wall can be irregular pattern, such as have
There is curvilinear sidewall etc., is not particularly limited herein.All tubular structures are arranged in array, and arrange with capacitance contact node 101
Array it is corresponding so that the bottom of each tubular structure electrically connects with the capacitance contact node 101 in the device region 100A
It connects.The lower electrode layer 130 can be polysilicon electrode or metal electrode.It, can be with when lower electrode layer 130 is metal electrode
Using titanium nitride (TiN) and Ti stepped construction.When lower electrode layer 130 is polysilicon electrode, using zero doping and/or can mix
Miscellaneous polycrystalline silicon material is formed.
The cross-brace layer connects the outer wall of multiple tubular structures of the lower electrode layer 130 and along being parallel to substrate
The direction on 100 surfaces extends, including a base layer support layer 111, at least one layer of middle support layer 112 and a top support layer
113, wherein the top support layer 113 is located at the top periphery of multiple tubular structures of the lower electrode layer 130, it is described in
Between supporting layer 112 be located at the lower electrode layer 130 multiple tubular structures intermediate position, base layer support layer 111 is located at described
The bottom periphery of multiple tubular structures of lower electrode layer 130.The material of each supporting layer in the cross-brace layer can
It with identical, such as is silica；Can also be not exactly the same, such as base layer support layer is silica, middle support layer
112 and top support layer 113 be silica.
The capacitor dielectric layer 131 is set to the surfaces externally and internally and the cross-brace layer of the lower electrode layer 130
On surface, to make full use of two apparent surfaces of lower electrode layer 130, the capacitor with larger electrode surface area is constituted.It is excellent
Choosing, the capacitor dielectric layer 131 can be greater than 7 high-K dielectric layer for dielectric constants such as metal oxides.Further, institute
Stating capacitor dielectric layer 131 is multilayered structure, for example, oxidation Kazakhstan-zirconium oxide double-layer structure.The capacitor dielectric layer 131 extends
It is covered on the surface of entire device region 100A, the capacitor dielectric layer 131 has in the boundary for being located at lower electrode layer to be corresponded to
The out-of-flatness side wall of the cross-brace layer, the out-of-flatness side wall have uneven pattern.
The upper electrode layer 132 is set to the surfaces externally and internally of the capacitor dielectric layer 131, and the upper electrode layer 132 is right
It the outside of the inside and the tubular structure of answering the tubular structure can be with the capacitor dielectric layer 131 and the lower electricity
Pole layer 130 constitutes capacitor, and the upper electrode layer 132, capacitor dielectric layer 131 and lower electrode layer 130 are in the lower electricity as a result,
A capacitor is constituted at each tubular structure of pole layer 130, and then forms array of capacitors.The upper electrode layer 132 can be with
For single layer structure or multilayered structure, when the upper electrode layer 132 is single layer structure, for example, polysilicon electrode,
It can be metal electrode, when upper electrode layer 132 is metal electrode, such as can be formed using titanium nitride (TiN).In addition,
On device region 100A fringe region (i.e. the borderline region of capacitor hole array), due to cross-brace layer (i.e. middle support layer 112,
Top support layer 113) presence, the upper electrode layer 132 also with the outer side wall structure of uneven pattern, it is described it is concave-convex not
The outer side wall structure of flat pattern correspond to the middle support layer 112 outside the tubular structure cylinder of the lower electrode layer 130,
Top support layer 113, so that the upper electrode layer 132 is in the device region 100A fringe region (i.e. capacitor hole array
Borderline region) on part, the corresponding middle support layer 112, top support layer 113 are with far from the lower electrode layer 130
Direction protrusion, makes the array of capacitors boundary out-of-flatness in device region 100A.In addition, in the present embodiment, the capacitor dielectric layer
131 and the upper electrode layer 132 also successively extend over the surface of the base layer support layer 111 retained on the external zones 100B
On.
The top electrode filled layer 133 covers on the surface of the upper electrode layer 132, and fills the upper electrode layer 132
Between gap.The i.e. described top electrode filled layer 133 fills the gap between the tubular structure of full phase neighbour.Preferably, on described
The material of electrode filled layer 133 includes undoped or boron doped polysilicon.The top electrode coating 140 is covered on described
The outer surface of top electrode filled layer 133, the top electrode coating 160 are preferably laminated construction, including described for connecting
The conductive metal layer (its material is including but not limited to tungsten) on 132 surface of electrode filled layer and for avoiding conductive metal layer from aoxidizing
Oxide layer (its material is including but not limited to silica).Equally, the top electrode filled layer 133 and the top electrode coating
140 all have the outer side wall structure (i.e. out-of-flatness lateral wall) of uneven pattern, the out-of-flatness lateral wall it is uneven
Pattern corresponds to the middle support layer 112 and top support layer 113.
In addition, the top electrode coating 140, top electrode filled layer 133, upper electrode layer 132 and capacitor dielectric layer 131
The side wall being laminated at the boundary E2 of device region 100A can be parallel in vertical direction with the tubular structure of the lower electrode layer 130
Setting, can also be arranged with the gradient of 100 upper surface of substrate at an angle.
The boundary protection layer 150 is covered on the out-of-flatness of the top electrode coating 140 in the device region 100A
On lateral wall, conduction is avoided to connect to separate the crack and array of capacitors boundary in interlayer dielectric layer 160 as boundary side wall
Touch the short circuit problem between plug 170 and array of capacitors boundary E1.The boundary protection layer 150 is insulating materials, including nitrogen
At least one of SiClx, fire sand, silicon oxynitride.
The interlayer dielectric layer 160 is not placed only on the surface of the device region 100A with the boundary protection layer 150,
The surface of the entire external zones 100B is also extended over, it can be complete by boundary protection layer 150 and top electrode coating 140
In being buried in, and there are flat sidewall surfaces and top surface.It is formed in the interlayer dielectric layer 60 positioned at the device region
Conductive contact plug 170 in 100A and the conductive contact plug 170 in the external zones 100B, the device region
The top electrode filled layer 133 in conductive contact plug 170 and the device region 100A in 100A is in electrical contact, the periphery
The electrical contact (not shown) of the conductive structure in conductive contact plug 170 and the external zones 100B in area 100B.The interlayer
The material of dielectric layer 160 can be the low-K dielectric that dielectric constant K is lower than 4, be also possible to silica etc..The conductive contact is inserted
The material of plug 170 includes but is not limited to tungsten.
The array of capacitors structure of the present embodiment, the substantially out-of-flatness in interlayer dielectric layer 160 and array of capacitors
A boundary protection side wall is added between boundary (is placed only in the borderline boundary protection layer of out-of-flatness of array of capacitors
150), for by the uneven integral boundary of the crack that there may be in interlayer dielectric layer 160 and the array of capacitors every
It opens, to avoid between conductive contact plug 170 and array of capacitors boundary caused by the conductive metallic material filled in crack
Short circuit problem improves device reliability.
In above-described embodiment, boundary protection layer 150 is only placed only in the uneven integral boundary of array of capacitors, i.e., only covers
It covers on the out-of-flatness lateral wall that the corresponding cross-brace layer of top electrode coating 140 in device region 100A is formed, but this
The technical solution of utility model is not merely defined in this, in another embodiment of the utility model, please refers to Figure 14, described
The top electrode coating 140 that boundary protection layer 150 is not placed only in device region 100A corresponds to cross-brace layer and is formed not
It on smooth lateral wall, is also covered on the upper surface of the top electrode coating, the boundary protection layer 150 not only may be used as a result,
With the uneven integral boundary of protective condenser array (on the outside of the out-of-flatness that i.e. the corresponding cross-brace layer of top electrode coating 140 is formed
Wall), moreover it is possible to the entire top surface of protective condenser array increases the protection of array of capacitors, it is reliable to be conducive to device
Property further increases；In the another embodiment of the utility model, the boundary protection layer 150 is not placed only in device region
The corresponding cross-brace layer of top electrode coating 140 in 100A and on the out-of-flatness lateral wall that is formed, be also covered on described power on
On the upper surface of pole coating, and extend on the surface of the entire external zones 100B of 160 bottom of interlayer dielectric layer, by
This, boundary protection layer 150 not only can protect the array of capacitors in device region 100A, additionally it is possible to the knot in external zones 100B
Structure is protected, and prevents the formation process of conductive contact plug from causing adverse effect to external zones 100B and device region 100A.
In conclusion the array of capacitors structure of the utility model, increases between top electrode filled layer and interlayer dielectric layer
If one is at least covered on the borderline boundary protection layer of out-of-flatness of array of capacitors, will there may be in interlayer dielectric layer
Crack and the boundary of array of capacitors separate, effectively evaded in conductive contact plug process due to capacitor array boundary injustice
It is whole and form the short circuit problem that crack in turn results in, improve the reliability of device.
Correspondingly, the utility model also provides a kind of semiconductor devices, it include array of capacitors structure as described above.Institute
Stating semiconductor devices is preferably dynamic RAM.Since the semiconductor devices of the utility model uses the utility model
Array of capacitors structure, therefore reliability is improved.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Fixed, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content belong to right and want
Seek the protection scope of book.
Claims (9)
1. a kind of array of capacitors structure characterized by comprising
Substrate has the device region for being used to form array of capacitors；
Lower electrode layer is arranged on the device region of the substrate, and the lower electrode layer has the multiple tubulars being arranged in array
Structure；
Capacitor dielectric layer is covered on the surfaces externally and internally of the lower electrode layer；
Upper electrode layer is covered on the surface of the capacitor dielectric layer；
Top electrode filled layer；Be covered on the surface of the upper electrode layer and fill up the gap in the upper electrode layer, it is described on
Electrode filled layer has the lateral wall of uneven pattern；And
Boundary protection layer, the boundary protection layer are at least covered on the lateral wall of the top electrode filled layer, and described
Boundary protection layer is insulating materials.
2. array of capacitors structure as described in claim 1, which is characterized in that it further include top electrode coating, it is described to power on
Pole coating is covered on the surface of the top electrode filled layer, and has the lateral wall pair with the top electrode filled layer
The out-of-flatness lateral wall answered；And the capacitor dielectric layer, the upper electrode layer, the top electrode filled layer and the top electrode
Coating successively extends on the surface of the entire device region；The boundary protection layer at least covers the top electrode and covers
On the out-of-flatness lateral wall of cap rock.
3. array of capacitors structure as claimed in claim 2, which is characterized in that the boundary protection layer is covered on described power on
On the upper surface of pole coating and the out-of-flatness lateral wall.
4. array of capacitors structure as described in claim 1, which is characterized in that also have on the substrate and be located at the device
The external zones of area periphery is formed with conductive structure in the external zones；The array of capacitors structure further includes interlayer dielectric layer,
The interlayer dielectric layer is not placed only on the surface of the device region with the boundary protection layer, is also extended over described outer
It encloses in area；The conductive contact plug that is formed in the device region in the interlayer dielectric layer and it is located at the external zones
In conductive contact plug, the top electrode filled layer electricity in the conductive contact plug and the device region in the device region
It contacts, the conductive structure in conductive contact plug and the external zones in the external zones is in electrical contact.
5. array of capacitors structure as claimed in claim 4, which is characterized in that the boundary protection layer is extended over described
On the surface of external zones.
6. the array of capacitors structure as described in any one of claims 1 to 5, which is characterized in that it further include cross-brace layer,
The cross-brace layer is located on the substrate of the device region and multiple tubular structures of lower electrode layer described in lateral connection,
Wherein, the uneven pattern of the lateral wall of the top electrode filled layer corresponds to outside the tubular structure of the lower electrode
The cross-brace layer.
7. array of capacitors structure as claimed in claim 6, which is characterized in that the cross-brace layer is supported including a top layer
Layer, at least one layer of middle support layer and a base layer support layer, the top support layer are located at the tubular structure of the lower electrode layer
Top periphery, the middle support layer is located at the intermediate position of the tubular structure of the lower electrode layer, the base layer support layer
Positioned at the bottom periphery of the tubular structure of the lower electrode layer.
8. the array of capacitors structure as described in any one of claims 1 to 5, which is characterized in that also formed in the substrate
There are multiple capacitance contact nodes, bottom and the corresponding contact node phase of the lower electrode layer in each tubular structure
Connection.
9. a kind of semiconductor devices, which is characterized in that including array of capacitors knot such as described in any item of the claim 1 to 8
Structure.
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| US11925012B2 (en) | 2020-03-12 | 2024-03-05 | Changxin Memory Technologies, Inc. | Capacitor array structure and method for forming the same |
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