CN208706614U - Semiconductor fixture - Google Patents

Abstract

A kind of semiconductor fixture, it include: carrier, carrier includes the first center and the first edge area for surrounding the first center, with several mutually discrete wafer areas in first center, carrier includes the first face, several first pilot pins with the first opening of one first opening and encirclement in each wafer area, first pilot pin is located at the surface in the first face, first face exposes the first opening, for accommodating wafer in first opening, the surface in the first face of first edge area of carrier has the second pilot pin；Cover board, cover board includes the second center and the second edge area for surrounding the second center, there is the second opening through cover board in second edge area, there are several thirds through cover board to be open in second center, when the first face and cover plate lid are closed, second opening is used for the second pilot pin of accommodating portion, and each third opening exposes a wafer area.It can reduce the difficulty of positioning carrier and cover board using the semiconductor fixture.

Description

Semiconductor fixture

Technical field

The utility model relates to semiconductor field more particularly to a kind of semiconductor fixtures.

Background technique

It needs to use reflow soldering process in semiconductor flip Welding, carries out residual flux scavenger after completing Reflow Soldering In skill, wafer need to be fixed, so the effect of the cover board is to go out wafer when preventing high pressure water cleaning to fall using cover board It falls.

However, larger using the difficulty of current fixture positioning carrier and cover board.

Utility model content

The technical issues of the utility model solves is to provide a kind of semiconductor fixture, to reduce the difficulty of positioning carrier and cover board Degree.

In order to solve the above technical problems, the utility model provides a kind of semiconductor fixture, comprising: carrier, the carrier packet It includes the first center and surrounds the first edge area of the first center, have several mutually discrete in first center Wafer area, the carrier include the first face, in each wafer area with one first opening and surround first be open several the One pilot pin, and first pilot pin is located at the surface in the first face, first face exposes the first opening, and described first opens For accommodating wafer in mouthful, the surface in the first face of first edge area of the carrier has the second pilot pin；Cover board, the cover board Including the second center and the second edge area for surrounding the second center, have second through cover board in the second edge area It is open, there are several thirds through cover board to be open in second center, when the first face of carrier and cover plate lid conjunction, Second opening is used for the second pilot pin of accommodating portion, and each third opening exposes a wafer area.

Optionally, the first edge area includes opposite first area and second area；The carrier further include: respectively It is set to the pad level in the first face of first area and second area.

Optionally, the height of the pad level is more than or equal to the thickness of wafer.

Optionally, the thickness difference of the height of the pad level and wafer is 0 millimeter~0.5 millimeter.

Optionally, the height of the pad level is 0.8 millimeter~2 millimeters.

Optionally, the minimum range of the pad level to carrier edge is greater than 8 millimeters.

Optionally, for 1 or multiple positioned at the number of the pad level of the first area.

Optionally, for 1 or multiple positioned at the number of the pad level of second area.

Optionally, the height of second pilot pin is 2 millimeters~4 millimeters.

Optionally, the number of second pilot pin is for 1 or multiple.

Compared with prior art, the technical solution of the utility model has the advantages that

In semiconductor fixture provided by the utility model, each center of the carrier includes one first opening and surrounds Several first pilot pins of first opening, first opening is for placing wafer, and first pilot pin is for limiting crystalline substance Round position, prevents wafer from shifting.The number of first pilot pin is more, so that limitation of first pilot pin to wafer Ability is stronger.Although the number of the first pilot pin is more, first pilot pin is only used for the position of limitation wafer.And And each third opening in the cover board exposes a wafer area, so that the first pilot pin does not interfere cover board and carrier Lid close.Second pilot pin in carrier first edge area be partially submerged into cover board second opening in, can be realized cover board and The positioning of carrier.Also, since the number of the second pilot pin is less, opened so that each second pilot pin is embedded in corresponding second The difficulty of mouth is lower, therefore, advantageously reduces the difficulty of positioning cover plate and carrier.

Further, the first edge area includes opposite first area and second area；The carrier further includes difference It is set to the pad level of first area and second area.Since the height of the pad level is more than or equal to the thickness of wafer, So that after lid closing lid plate and carrier therefore the pressure that the cover board is not easy to generate wafer direction carrier is advantageously reduced to crystalline substance It causes to damage in round surface.

Detailed description of the invention

Fig. 1 is a kind of structural schematic diagram of semiconductor fixture；

Fig. 2 is the structural schematic diagram of the utility model semiconductor fixture；

Fig. 3 is the schematic diagram of the section structure of the Fig. 2 along L1 line；

Fig. 4 is the schematic diagram of the section structure of the Fig. 2 along L2 line.

Specific embodiment

As described in background, using existing semiconductor fixture, the difficulty of positioning carrier and cover board is larger.

Fig. 1 is a kind of structural schematic diagram of semiconductor fixture.

Referring to FIG. 1, carrier 100, the carrier 100 includes several mutually discrete wafer areas (not marking in figure), Pilot pin 102 with the first opening 101 of one first opening 101 and encirclement in each wafer area, the carrier 100 includes first Face 1, first face 1 expose the first opening 101, and the pilot pin 102 is located at the surface in the first face 1, first opening For accommodating wafer in 101；Cover board 103, interior the second opening 104 for running through cover board 103 with several of the cover board 103, when When first face 1 of carrier 100 is closed with the lid of cover board 103, second opening 104 is for accommodating first pilot pin 102.

In above-mentioned semiconductor fixture, one opening 101 for place a wafer, in order to once can to multiple wafers into Multiple first openings 101 are arranged in row processing in the carrier 100.The first pilot pin 102 around first opening 101 For limiting the position of wafer, prevent wafer from shifting.In order to preferably limit the position of wafer, one first opening 101 First pilot pin 102 of surrounding usually setting 4 or 4 or more, and the number of first opening 101 is also more, So that the number of the first pilot pin 102 is also more.First pilot pin 102 is other than limiting the position of wafer, each institute Stating the first pilot pin 102 need to be embedded in the second opening 104, can realize that the lid between cover board 103 and carrier 100 closes.

However, since the number of first pilot pin 102 is more, so that each first pilot pin 102 is embedded in Difficulty in two openings 104 is larger, if there is individual first pilot pins 102 to be distorted, the first pilot pin 102 distorted is difficult to It is embedded in corresponding second opening 104, then the cover board 103 and carrier 100 are difficult to realize lid conjunction, it can be seen that, only when each A first pilot pin 102 is embedded in the second opening 104, and the cover board 103 and carrier 100 can realize that lid closes, so that lid The difficulty of closing lid plate 103 and carrier 100 is larger.

In order to solve the above technical problems, the utility model provides a kind of semiconductor fixture, comprising: carrier, the carrier Including the first center and the first edge area for surrounding the first center, have several mutually discrete in first center Wafer area, with one first opening and surround several first pilot pins of the first opening in each wafer area, and described the One pilot pin is located at the surface in the first face, and first face exposes the first opening, is used to place wafer in first opening, The surface in the first face of first edge area of the carrier has the second pilot pin；Cover board, the cover board include the second center and The second edge area of the second center is surrounded, has in the second edge area and is open through the second of cover board, in described second There are several thirds through cover board to be open, when the first face is closed with cover plate lid, second opening is for accommodating in heart district The second pilot pin of part, each third opening expose a wafer area.It can reduce lid using the semiconductor fixture to close The difficulty of carrier and cover board.

It is understandable to enable the above-mentioned purpose, feature and beneficial effect of the utility model to become apparent, with reference to the accompanying drawing Specific embodiment of the utility model is described in detail.

Fig. 2 is the structural schematic diagram of the utility model semiconductor fixture.

Referring to FIG. 2, carrier 200, the carrier 200 includes the first center A and the first side for surrounding the first center A Edge area (does not mark) in figure, described with several mutually discrete wafer areas (not marking in figure) in the first center A Carrier includes the first face X, with one first opening 201 and surrounds several of the first opening 201 and first determines in each wafer area Position needle 202, and first pilot pin 202 is located at the surface of the first face X, the first face X exposes the first opening 201, institute It states for accommodating wafer in the first opening 201, the surface of 200 first edge area of carrier the first face X has the second pilot pin 204；Cover board 205, the cover board 205 include second edge area (not marking in figure), are had in the second edge area through lid Second opening 207 of plate 205, second center has several thirds opening 206 through cover board 205, when the load When the first face X and cover board 205 lid of tool 200 close, second opening 207 is used for the second pilot pin of accommodating portion 204, each described Third opening 206 exposes a wafer area.

The first face X and cover board 205 lid of the carrier 200 close, and for fixing wafer, prevent subsequent to wafer progress high pressure Water, which goes out wafer when cleaning, to be fallen.

In the present embodiment, the carrier 200 is flat (Flat Boat) carrier.In other embodiments, the carrier Both ends have difference in height (J Boat).

The material of the carrier 200 includes metal or plastics.

First center A of the carrier 200 be used to be arranged one first opening 201 and surround first be open 201 the One pilot pin 202.First opening 201 is conducive to subsequent in crystal column surface for exposing the middle position of a wafer Carry out semiconductor technology processing；First pilot pin 202 is only used for the position of positioning wafer, prevents wafer from shifting.

In the present embodiment, 8 the first pilot pins 202 are arranged in 201 surroundings of each first opening, and each first is open around 201 The number for the first pilot pin 202 being arranged is more, so that wafer is not susceptible to deviate, is conducive to subsequent in crystal column surface progress half Semiconductor process.

In other embodiments, 4~7 first pilot pins are arranged in 201 surroundings of each first opening；Alternatively, each 8 the first pilot pins of the above are arranged in one 201 surroundings of opening.

The first edge area includes opposite first area (not shown) and second area (not shown).? In the present embodiment, the carrier further include: be respectively arranged at the pad level 203 of the first face X of first area and second area.

The material of the pad level 203 includes metal or plastics.The height of the pad level 203 is more than or equal to crystalline substance Round thickness, specifically, the thickness difference of the height of the pad level 203 and wafer is 0 millimeter~0.5 millimeter, so that subsequent lid After closing lid plate 205 and carrier 200, the cover board 205 is not easy to generate wafer the pressure for being directed toward carrier 200, so that cover board 205 is not Easily to the damage of wafer, be conducive to the performance for improving wafer.

The height of the pad level 203 are as follows: 0.8 millimeter~2 millimeters.

Number positioned at the pad level 203 of first area is for 1 or multiple；Positioned at the pad level of second area Number is for 1 or multiple.

In the present embodiment, the number positioned at the pad level 203 of first area is 2, positioned at the pad of second area High-rise number is 2.In other embodiments, the number positioned at the pad level of first area is 1；Alternatively, being located at first The number of the pad level in region is greater than 2；Alternatively, the number for being located at the pad level of second area is 1, alternatively, being located at second The number of the pad level in region is greater than 2.

Fig. 3 is the schematic diagram of the section structure of the Fig. 2 along L1 line.

In the present embodiment, 2 pad levels 203 are located at first area, and 2 pad levels 203 are located at second area, then subsequent Cover board 205 and 200 Gai Hehou of carrier, the cover board 205 is horizontal positioned, caused by being beneficial to prevent cover board 205 because tilting to wafer Therefore damage is conducive to the performance for improving wafer.

The minimum range at the pad level 203 to 200 edge of carrier is greater than 8 millimeters, selects the pad level 203 to carrier The meaning of the minimum range at 200 edges is: if the pad level 203 to 200 edge of carrier minimum range less than 8 millimeters, So that setting pad level 203 gets too close to the edge of carrier 200, easily pad level 203 is caused to damage in use.

In the present embodiment, the pad level 203 and the second pilot pin 204 are located at the not same district in first edge area Domain is beneficial to prevent pad level 203 and the second pilot pin 204 positioned at same so that the space in first edge area is fully utilized When a region, so that the space that first edge area need to reserve is excessive, correspondingly, making that the first center A's is too small.Described first The first opening 201 in the A of center is for accommodating wafer, when the first center A is too small, so that the number of the first opening 201 Less, then the number for the wafer being once capable of handling using semiconductor fixture is less.

In other embodiments, second pilot pin and pad level are respectively positioned on first area；Alternatively, second positioning Needle and pad level are only located at second area；Alternatively, second pilot pin and pad level are only located at third region；Alternatively, described Second pilot pin and pad level are only located at the fourth region.

Fig. 4 is the schematic diagram of the section structure of the Fig. 2 along L2 line.

The first edge region of the carrier 200 further include: third region and the fourth region.

In the present embodiment, the number of second pilot pin 204 is 4, wherein 2 the second pilot pins 204 are located at the Three regions, 2 the second pilot pins 204 are located at the fourth region.In other embodiments, the number of second pilot pin is 1 Perhaps second pilot pin is only located at third region or is only located at the fourth region when multiple；Of second pilot pin When number is 2~3, several second pilot pins are located at third region, several second pilot pins are located at the fourth region；Or Person, when the number of the second pilot pin is greater than 4, several second pilot pins are located at third region, several second pilot pins Positioned at the fourth region.

The height of second pilot pin 204 is 2 millimeters~4 millimeters, selects the meaning of 204 height of the second pilot pin It is: in second opening 207 of the insertion of the second pilot pin 204, positioning carrier 200 and cover board 205 is used for, if described second is fixed The height of position needle 204 is less than 2 millimeters, so that carrier 200 and the positioning of cover board 205 are not secured enough, then carrier 200 and cover board 205 are easy It separates, so that carrier 200 and cover board 205 are difficult to clamp wafer, then when the subsequent progress high pressure water cleaning to wafer, the crystalline substance Circle, which is easily rushed out, to be fallen；If the height of second pilot pin 204 is greater than 4 millimeters, so that the material of required second pilot pin 204 Excessively, it is unfavorable for save the cost.

Although the number of first pilot pin 202 is more, first pilot pin 202 is only used for limitation wafer Position.Also, each third opening in the cover board 205 exposes a wafer area, so that the first pilot pin 202 does not interfere The lid of cover board 205 and carrier 200 closes.Second pilot pin 204 that is located through of the cover board 205 and carrier 200 partially passes through Two openings 207 are realized.And the number of second pilot pin 204 is less so that each second pilot pin 204 be inserted into it is corresponding The difficulty of second opening 207 is lower, therefore, advantageously reduces the difficulty that cover board 205 and carrier 200 position.

The material of the cover board 205 includes: metal or plastics.

When the first face X and the lid of cover board 205 close, second opening 207 is for accommodating the second pilot pin 204, therefore, institute It is identical by the number of the second pilot pin 204 for stating the number of the second opening 207.

In the present embodiment, the number of second pilot pin 204 is 4, and 2 the second pilot pins 204 are located at third Region, 2 the second pilot pins 204 are located at the fourth region, and therefore, the number of second opening 207 is 4, and 2 described the Two openings 207 are located at third region, and 2 second openings 207 are located at the fourth region.

Second opening 207 is for accommodating the second pilot pin 204, therefore, when wafer is placed in the first opening 201 it Afterwards, the second opening 207 is partially submerged by the second pilot pin 204 to realize the positioning of cover board 205 and carrier 200.

After the carrier 200 and cover board 205 position, the third opening 206 exposes the atop part surface of wafer, Be conducive to subsequent to wafer progress semiconductor technology processing.Also, each third opening 206 exposes a wafer area, makes Obtain the opening for corresponding to the first pilot pin 202 in cover board 205 without additional setting, then when carrier 200 and the lid of cover board 205 close, nothing First pilot pin 202 need to be positioned, and need to only guarantee to can be realized in each second opening 207 of the insertion of second pilot pin 204 The lid of carrier 200 and cover board 205 closes, and therefore, advantageously reduces the positioning difficulty of cover board 205 and carrier 200.

Although the utility model discloses as above, the utility model is not limited to this.Anyone skilled in the art, It does not depart from the spirit and scope of the utility model, can make various changes or modifications, therefore the protection scope of the utility model It should be defined by the scope defined by the claims..

Claims (10)

1. a kind of semiconductor fixture characterized by comprising

Carrier, the carrier includes the first center and the first edge area for surrounding the first center, in first center With several mutually discrete wafer areas, the carrier includes the first face, has one first opening and packet in each wafer area Several first pilot pins of the first opening are enclosed, and first pilot pin is located at the surface in the first face, the first face exposure First opening out, for accommodating wafer in first opening, the surface in the first face of first edge area of the carrier has the Two pilot pins；

Cover board, the cover board includes the second center and the second edge area for surrounding the second center, in the second edge area With the second opening through cover board, there are several thirds through cover board to be open for second center, when the of carrier When closing on one side with cover plate lid, second opening is used for the second pilot pin of accommodating portion, and each third opening exposes one Wafer area.

2. semiconductor fixture as described in claim 1, which is characterized in that the first edge area includes opposite first area And second area；The carrier further include: be respectively arranged at the pad level in the first face of first area and second area.

3. semiconductor fixture as claimed in claim 2, which is characterized in that the height of the pad level is more than or equal to wafer Thickness.

4. semiconductor fixture as claimed in claim 3, which is characterized in that the height of the pad level and the thickness difference of wafer are 0 millimeter~0.5 millimeter.

5. semiconductor fixture as claimed in claim 2, which is characterized in that the height of the pad level is 0.8 millimeter~2 millis Rice.

6. semiconductor fixture as claimed in claim 2, which is characterized in that the minimum range of the pad level to carrier edge is big In 8 millimeters.

7. semiconductor fixture as claimed in claim 2, which is characterized in that the number positioned at the pad level of the first area is 1 or multiple.

8. semiconductor fixture as claimed in claim 2, which is characterized in that the number positioned at the pad level of second area is 1 Or it is multiple.

9. semiconductor fixture as described in claim 1, which is characterized in that the height of second pilot pin is 2 millimeters~4 millis Rice.

10. semiconductor fixture as described in claim 1, which is characterized in that the number of second pilot pin is for 1 or more It is a.