CN208623394U - A kind of network interface concatenation listens to circuit card and telemechanical apparatus intelligent regulator analyzer - Google Patents

Abstract

The utility model relates to a kind of network interface concatenations to listen to circuit card and telemechanical apparatus intelligent regulator analyzer, wherein it includes the first PHY chip, the second PHY chip, the first high-speed buffer, the second high-speed buffer and double MAC chips that network interface concatenation, which listens to circuit card,；TX interface, RX interface and RJ interface are equipped in first PHY chip and the second PHY chip, the TX interface of first PHY chip is connected by the first high-speed buffer with the RX interface of the second PHY chip, and the TX interface of the second PHY chip is connected by the second high-speed buffer with the RX interface of the first PHY chip；The TX interface of first PHY chip also passes through the first high-speed buffer and is connected with a MAC interface in double MAC chips, and the TX interface of the second PHY chip also passes through the second high-speed buffer and is connected with another MAC interface in double MAC chips.The phenomenon that reflection superposition interferes original signal message can be avoided the occurrence of in the utility model, interference effect will not be generated to link.

Description

A kind of network interface concatenation listens to circuit card and telemechanical apparatus intelligent regulator analyzer

Technical field

The utility model relates to power grid regulation fields, and in particular to a kind of network interface concatenation listens to circuit card and telemechanical apparatus intelligence It can tune-up analyzer.

Background technique

With all-round popularization of the regulation integrated technique in power grid, the importance for regulating and controlling integrated telecontrol information table is convex It is aobvious.Regulate and control integrated telecontrol information table content and covers all of the professional equipments such as protection, automation, communication, switch, alternating current-direct current Remote control, telemetering, remote signalling, remote regulating information are that (including audit, comparison and parsing) is monitored to administrative substation by power system monitor class Unique foundation.And before monitoring starts, it needs to lead in scheduling station and establishes communication link between telemechanical apparatus, how to establish The communication link of high quality is current urgent problem to be solved.

Utility model content

The technical problem to be solved by the utility model is to provide a kind of network interface concatenations to listen to circuit and telemechanical apparatus intelligence Tune-up analyzer can establish the communication link of high quality.

The technical solution that the utility model solves above-mentioned technical problem is as follows: a kind of network interface concatenation listens to circuit card, including First PHY chip, the second PHY chip, the first high-speed buffer, the second high-speed buffer and double MAC chips；First PHY TX interface, RX interface and RJ interface are equipped on chip and the second PHY chip, the TX interface of first PHY chip passes through institute It states the first high-speed buffer to be connected with the RX interface of second PHY chip, the TX interface of second PHY chip passes through described Second high-speed buffer is connected with the RX interface of first PHY chip；The TX interface of first PHY chip also passes through described First high-speed buffer is connected with a MAC interface in double MAC chips, and the TX interface of second PHY chip is also logical Second high-speed buffer is crossed to be connected with another MAC interface in double MAC chips.

The beneficial effects of the utility model are: being listened in circuit card in a kind of network interface concatenation of the utility model, the first PHY core By MII interface inter-link between piece and the second PHY chip, the RJ interface between real first PHY chip and the second PHY chip is straight Logical concatenation.In addition, the intervention of high-speed buffer, can avoid the occurrence of the phenomenon that reflection superposition interferes original signal message. Meanwhile double MAC chips only receive PHY message, will not send message to the first PHY chip and the second PHY chip, for the high speed Link only unidirectionally will not generate interference effect to link.

Based on the above technical solution, the utility model can also do following improvement.

Further, double MAC chips are equipped with the pci interface for being connected with CPU core core.

Further, the pci interface is outlet structure.

Using the beneficial effect of above-mentioned further scheme is: the pci interface of double MAC chips can be inserted into PCI jack design The PCI slot of CPU core core, final PHY message is transferred to CPU core core through the pci interface of double MAC chips, for subsequent CPU Core board parses PHY message, listens to message content.

Circuit card is listened to based on a kind of network interface concatenation described above, and the utility model also provides a kind of telemechanical apparatus and intelligently adjusts Try analyzer.

A kind of telemechanical apparatus intelligent regulator analyzer, including CPU core core and a kind of network interface as described above concatenation Circuit card is listened to, the CPU core core listens to double MAC chips in circuit card with network interface concatenation and is connected.

Based on the above technical solution, the utility model can also do following improvement.

Further, double MAC chips are equipped with pci interface, and the CPU core core is equipped with PCI slot, described double Pci interface on MAC chip is plugged in the PCI slot on the CPU core core.

Further, the RJ interface of first PHY chip is used to communicate to connect with scheduling station, second PHY chip RJ interface be used for and telecontrol equipment communicate to connect.

Further, the CPU core core is equipped with USB interface.

Further, the CPU core core is equipped with wireless communication module.

The beneficial effects of the utility model are: a kind of telemechanical apparatus intelligent regulator analyzer of the utility model passes through network interface string It connects and listens to two network interfaces of circuit card and be serially linked into the telecontrol channel between scheduling station and telemechanical apparatus, the serial access The normal communication for not interfering with scheduling station and telemechanical apparatus realizes seamless concatenation function.

Detailed description of the invention

Fig. 1 is the chip connection schematic diagram that a kind of network interface concatenation of the utility model listens to circuit card；

Fig. 2 is the telemechanical apparatus intelligent regulator analyzer using the utility model circuit design；

Fig. 3 be using the utility model circuit design telemechanical apparatus intelligent regulator analyzer and scheduling station and telemechanical apparatus it Between connection structure diagram.

Specific embodiment

The principles of the present invention and feature are described below in conjunction with attached drawing, example is served only for explaining that this is practical It is novel, it is not intended to limit the scope of the utility model.

As shown in Figure 1, a kind of network interface concatenation listens to circuit card, including the first PHY chip, the second PHY chip, the first high speed Buffer, the second high-speed buffer and double MAC chips；Be equipped in first PHY chip and the second PHY chip TX interface, The TX interface of RX interface and RJ interface, first PHY chip passes through first high-speed buffer and second PHY chip RX interface be connected, the TX interface of second PHY chip passes through second high-speed buffer and first PHY chip RX interface is connected；The TX interface of first PHY chip also passes through in first high-speed buffer and double MAC chips One MAC interface is connected, and the TX interface of second PHY chip also passes through second high-speed buffer and double MAC cores Another MAC interface in piece is connected.

In the present invention: it is interconnected between first PHY chip and the second PHY chip by high-speed buffer, it is existing The straight-through concatenation of RJ interface power grid mouth between real first PHY chip and the second PHY chip.

The hair mouth (TX interface) of first PHY chip and the second PHY chip by corresponding first high-speed buffer and After second high-speed buffer, respectively correspond and a MAC interface (MAC1) of double MAC chips and another MAC interface (MAC2) It is connected.

The interconnection of first PHY chip and the second PHY chip；Signal is by the first PHY chip to the mistake of the second PHY chip Journey are as follows: in first PHY chip, serioparallel exchange is realized from RJ interface to TX interface, using the first high-speed buffer, The data delay of first high-speed buffer is picosecond, is then connected with the RX interface of the second PHY chip, delay is negligible not Meter；Then, in the second PHY chip, RX interface realizes parallel-serial conversion to RJ interface, finally there is the output of RJ interface.The link On serioparallel exchange and parallel-serial conversion respectively the inside of the first PHY chip and the second PHY chip realize, measure nanosecond, most Concatenation low latency requirement is realized eventually.Signal is by the process of the second PHY chip to the first PHY chip with signal by the first PHY core Process of the piece to the second PHY chip.

First high-speed buffer plays the role of inhibiting interference in circuit.If without the first high-speed buffer Intervention, the direct one-to-two of network interface high speed signal of the first PHY chip, portion give the second PHY chip, another gives double MAC chips. Two parts of high speed signals have rebound phenomena, and the two paths of signals to rebound back can merge superposition, generate interference to primitive network message. The exactly intervention of the first high-speed buffer, the input of original message signal generate reflection generation two paths of signals and give the 2nd PHY core respectively Piece and double MAC chips, the final signal that reflects terminate at the first high-speed buffer, reflection superposition do not occur and interfere original letter The phenomenon that number message.Similarly: second high-speed buffer plays the role of inhibiting interference in circuit.If high without second The intervention of fast buffer, the direct one-to-two of network interface high speed signal of the second PHY chip, portion give the first PHY chip, another is given Double MAC chips.Two parts of high speed signals have rebound phenomena, and the two paths of signals to rebound back can merge superposition, to primitive network report Text generates interference.The exactly intervention of the second high-speed buffer, the input of original message signal generate reflection and generate two paths of signals difference To the first PHY chip and double MAC chips, the final signal that reflects is terminated at the second high-speed buffer, reflection superposition is not occurred and is made The phenomenon that at interference original signal message.

Double MAC chips can dock the interface of two PHY chips (the first PHY chip and the second PHY chip), to receiving MAC packet converted, passed with pci interface.The PCI output expansion interface of the chip can be inserted into PCI jack design The PCI slot of CPU core core.

PHY chip is configured into 100,000,000 rates or gigabit rate, and network interface concatenation listens to circuit card and is suitable for 100,000,000 or gigabit It the concatenation of network interface and listens to.First PHY chip or/and the second PHY chip are configured into power port mode or optical port mode, this is practical Novel network interface concatenation listens to circuit card and may be designed to photoelectric conversion device interface card.

Circuit card is listened in a kind of network interface concatenation of the utility model to have the advantage that

1, the utility model network interface concatenates function, only takes up string inside PHY chip and turns and turn the conversion time of string, delay reaches To nanosecond, and high-speed buffer delay only has picosecond, needs to store a message than other schemes and gets off to forward again and is consumed Postpone small more.The novel low latency is truly realized the seamless connection of network transmission.

2, the utility model is based on the straight-through design of low latency concatenation, can be fully immersed into network communication circuit, i.e., not to communication line There is any influence on road, while can also precisely obtain online message.

3, double MAC chips in the utility model only receive PHY message, will not send message to PHY chip.For the high-speed chain Road only unidirectionally will not generate interference effect to link.

4, the utility model is using link layer original message data mode is directly acquired, not as other common schemes are by exchanging The intervention of equipment avoids wrong acquisition.

5, the utility model is because there is the participation of power supply circuit to network interface link layer, can to concatenate into network data signals again Adjustment, plays recovery signal function.Network interface concatenation, which listens to circuit card, can also regard as a network trunk card, allow network data Transmission range increases one times.

Circuit card is listened to based on a kind of network interface concatenation described above, and the utility model also provides a kind of telemechanical apparatus and intelligently adjusts Try analyzer.

As shown in Figures 2 and 3, a kind of telemechanical apparatus intelligent regulator analyzer, including CPU core core, and such as above-mentioned institute A kind of network interface concatenation stated listens to circuit card, and the CPU core core concatenates the double MAC chip phases listened in circuit card with network interface Even.

Specific: double MAC chips are equipped with pci interface, and the CPU core core is equipped with PCI slot, described double Pci interface on MAC chip is plugged in the PCI slot on the CPU core core.

The RJ interface of first PHY chip is used to communicate to connect with scheduling station, the RJ interface of second PHY chip For being communicated to connect with telecontrol equipment.

The CPU core core is equipped with USB interface, and USB interface is used to import in the telecontrol information table in external USB equipment Into CPU core core.The CPU core core is equipped with wireless communication module, and wireless communication module is for obtaining remote server In telecontrol information table and be stored in CPU core core, wireless communication module can specifically select 4G module.

A kind of telemechanical apparatus intelligent regulator analyzer of the utility model listens to two network interfaces of circuit card by network interface concatenation It is serially linked into the telecontrol channel between scheduling station and telemechanical apparatus, which does not interfere with scheduling station and remote The normal communication of dynamic device, realizes seamless concatenation function.Telemechanical apparatus intelligent regulator analyzer passes through double MAC chips and obtains far Dynamic device sends the network packet of scheduling station to, passes to CPU core core by pci interface and is handled, can be supervised online Telemechanical apparatus is listened to send the telecontrol information table of scheduling station to, CPU core core is existing for monitoring the core of motion information Processor, model can be TMS320LF2407A.

In the present invention:

Network relay equipment can be regarded as by merging network interface concatenation and listening to the telemechanical apparatus intelligent regulator analyzer of circuit card.

The utility model network interface concatenation listens to PHY chip in circuit card and is configured into 100,000,000 rates or gigabit rate, Home Network Mouth concatenation listens to the concatenation that circuit card is suitable for 100,000,000 or gigabit network interface, this telemechanical apparatus intelligent regulator analyzer is suitable for 100,000,000 Mouthful data or gigabit mouth data are listened to.

The utility model network interface concatenation listens to PHY chip in circuit card and is configured into power port mode or optical port mode, Home Network Mouth concatenation listens to circuit card and can be designed photoelectric conversion device interface card.This telemechanical apparatus intelligent regulator analyzer may be designed as light Electric converting interface device.

The first smooth network interface and the second smooth network interface are serially linked into scheduling station based on the embedded frame of Port Mirroring In telecontrol channel between telemechanical apparatus；The serial access does not interfere with the normal communication of scheduling station and telemechanical apparatus.

The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all practical at this Within novel spirit and principle, any modification, equivalent replacement, improvement and so on should be included in the guarantor of the utility model Within the scope of shield.

Claims (7)

1. a kind of network interface concatenation listens to circuit card, it is characterised in that: including the first PHY chip, the second PHY chip, the first high speed Buffer, the second high-speed buffer and double MAC chips；Be equipped in first PHY chip and the second PHY chip TX interface, The TX interface of RX interface and RJ interface, first PHY chip passes through first high-speed buffer and second PHY chip RX interface be connected, the TX interface of second PHY chip passes through second high-speed buffer and first PHY chip RX interface is connected；The TX interface of first PHY chip also passes through in first high-speed buffer and double MAC chips One MAC interface is connected, and the TX interface of second PHY chip also passes through second high-speed buffer and double MAC cores Another MAC interface in piece is connected.

2. a kind of network interface concatenation according to claim 1 listens to circuit card, it is characterised in that: set on double MAC chips There is pci interface, the pci interface is outlet structure.

3. a kind of telemechanical apparatus intelligent regulator analyzer, it is characterised in that: including CPU core core, and such as claims 1 or 2 A kind of network interface concatenation listens to circuit card, and the CPU core core concatenates the double MAC chip phases listened in circuit card with network interface Even.

4. a kind of telemechanical apparatus intelligent regulator analyzer according to claim 3, it is characterised in that: double MAC chips It is equipped with pci interface, the CPU core core is equipped with PCI slot, and the pci interface on double MAC chips is plugged on described In PCI slot on CPU core core.

5. a kind of telemechanical apparatus intelligent regulator analyzer according to claim 3 or 4, it is characterised in that: the first PHY The RJ interface of chip is used to communicate to connect with scheduling station, and the RJ interface of second PHY chip with telecontrol equipment for communicating Connection.

6. a kind of telemechanical apparatus intelligent regulator analyzer according to claim 3 or 4, it is characterised in that: the core cpu Plate is equipped with USB interface.

7. a kind of telemechanical apparatus intelligent regulator analyzer according to claim 3 or 4, it is characterised in that: the core cpu Plate is equipped with wireless communication module.