CN208580746U - A kind of chip-packaging structure - Google Patents
A kind of chip-packaging structure Download PDFInfo
- Publication number
- CN208580746U CN208580746U CN201821275297.2U CN201821275297U CN208580746U CN 208580746 U CN208580746 U CN 208580746U CN 201821275297 U CN201821275297 U CN 201821275297U CN 208580746 U CN208580746 U CN 208580746U
- Authority
- CN
- China
- Prior art keywords
- chip
- circuit board
- image sensing
- packaging structure
- gasket
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
The utility model discloses a kind of chip-packaging structures, control chip fitting is fixed on the first surface of circuit board by technical solutions of the utility model, the other side that control chip deviates from circuit board is arranged in image sensing chip, and there is gap between control chip, it is electrically connected respectively with circuit board convenient for control chip and image sensing chip, it is not necessary that package position is arranged according to the size of coremaking piece and image sensing chip.
Description
Technical field
The utility model relates to chip encapsulation technology fields, more specifically, being related to a kind of chip-packaging structure.
Background technique
With the continuous development of science and technology, more and more electronic equipments are widely used in daily life
And in work, huge convenience is brought for daily life and work, becomes the indispensable weight of current people
Want tool.Electronic equipment realizes that the main component of various functions is chip, binds for the ease of chip and electronic equipment, is simultaneously
Chip is protected, needs to be packaged chip, forms chip-packaging structure.
When the prior art is packaged two chips simultaneously, first chip is directly usually fixed on circuit board
On, the second chip is then fixed into the side surface that first chip deviates from circuit board, two chips are typically all to pass through conducting wire
With circuit board electrical connection.In the packaged type, first pad for the ease of the first chip surrounding passes through conducting wire and circuit board
Connection, therefore the size of second chip needs to be less than the size of first chip, to expose the weldering in first chip edge region
Disk.
As it can be seen that needing when two chips are encapsulated in the same side of circuit board simultaneously by the prior art based on two chips
Size sets package position.
Utility model content
To solve the above-mentioned problems, technical solutions of the utility model provide a kind of chip-packaging structure, without according to control
Package position is arranged in the size of coremaking piece and image sensing chip.
To achieve the goals above, the utility model provides the following technical solutions:
A kind of chip-packaging structure, the chip-packaging structure include:
Circuit board, the circuit board include opposite first surface and second surface；The circuit board further includes being used for
The interconnection circuit being connect with external circuit；
Fitting is fixed on the control chip of the first surface, and the control chip is connect with the interconnection circuit；
Be arranged in it is described control chip deviate from the circuit board side image sensing chip, the image sensing chip with
There is gap, the image sensing chip is connect with the interconnection circuit between the control chip；
The cover board that the image sensing chip deviates from the circuit board side is set；The cover board and the circuit board shape
At an enclosure space, the image sensing chip and the control chip are located in the enclosure space.
Preferably, in said chip encapsulating structure, the interconnection circuit includes:
The first contact jaw and the second contact jaw of the first surface are set；First contact jaw is for connecting institute
Control chip is stated, second contact jaw is for connecting the image sensing chip；
The third contact jaw of the second surface is set, and the third contact jaw is for connecting the external circuit；
Wherein, first contact jaw is by the first wiring route and corresponding third contact jaw connection, and described the
Two contact jaws are connected by the second wiring route with the corresponding third contact jaw, first wiring route and described second
Wiring route insulation.
Preferably, in said chip encapsulating structure, the third contact jaw is pad or tin ball.
Preferably, in said chip encapsulating structure, on the direction perpendicular to the circuit board, the control chip with
The image sensing chip is at least partly overlapping.
Preferably, in said chip encapsulating structure, on the direction perpendicular to the circuit board, the control chip position
In the image sensing chip in the projection of the circuit board.
Preferably, in said chip encapsulating structure, have first between the image sensing chip and the circuit board
Gasket, the image sensing chip are fixed by first gasket with the circuit board.
Preferably, in said chip encapsulating structure, the image sensing chip has opposite front and back, back
Face includes first area and second area；
First gasket is between the first area and the circuit board；
The control chip is located at the second area in the orthographic projection of the circuit board.
Preferably, in said chip encapsulating structure, first gasket is silicon spacer, ceramic gasket or metal gasket
Piece.
Preferably, in said chip encapsulating structure, the image sensing chip has opposite front and back；It is carried on the back
It is arranged facing towards the circuit board；The first weld pad that its front has photosensitive pixel and connect with the photosensitive pixel；
Wherein, first weld pad is connect by conducting wire with the interconnection circuit.
Preferably, have between setting in said chip encapsulating structure, between the cover board and the image sensing chip
Away from.
Preferably, in said chip encapsulating structure, the cover board is fixed by the second gasket and the circuit board.
Preferably, in said chip encapsulating structure, second gasket is silicon spacer, ceramic gasket or metal gasket
Piece.
Preferably, in said chip encapsulating structure, the cover board is glass plate.
As can be seen from the above description, in the chip-packaging structure that technical solutions of the utility model provide, by control chip patch
The first surface for being fixed on circuit board is closed, control chip is arranged in away from the other side of circuit board in image sensing chip, and with
Controlling has gap between chip, be electrically connected, be not necessarily to circuit board respectively convenient for control chip and image sensing chip
According to the size of coremaking piece and image sensing chip, package position is set.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is the embodiments of the present invention, for those of ordinary skill in the art, without creative efforts, also
Other attached drawings can be obtained according to the attached drawing of offer.
Fig. 1 is a kind of schematic diagram of chip-packaging structure provided by the embodiment of the utility model；
Fig. 2 is a kind of top view of circuit board provided by the embodiment of the utility model；
Fig. 3 is the schematic diagram of another chip-packaging structure provided by the embodiment of the utility model；
Fig. 4 is a kind of front plan view of image sensor provided by the embodiment of the utility model；
Fig. 5 is a kind of front plan view for controlling chip provided by the embodiment of the utility model；
Fig. 6-Figure 12 is a kind of flow diagram of chip packaging method provided by the embodiment of the utility model；
Figure 13 is a kind of sectional drawing of chip provided by the embodiment of the utility model；
Figure 14-Figure 16 is a kind of flow diagram of chip manufacture method provided by the embodiment of the utility model.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
When by two chips simultaneously encapsulate be fixed on the same side of circuit board when, if two chips be using conducting wire with
Circuit board is electrically connected, as stated in the background art, after fixing at the back side of the first chip on circuit boards, in its front surface
When fixing the second chip, in order to expose the pad of first chip front side fringe region, in order to the pad of first chip
With circuit board electrical connection, it is required that size of the size of second chip less than first chip, in order to expose first
The pad of chip front side.
But above-mentioned packaged type will will limit the type of encapsulation chip, can only carry out to the certain types of chip in part
Encapsulation, can not be packaged any two chip.It is such as control chip when two chip one, another is image sensing core
When piece, due to image sensing chip acquisition image region tool have the dimensions, therefore image sensor dice need have compared with
Big size, and the chip development integrated with integrated circuit height is controlled, size can be smaller.Such as image sensing core
Piece is for when acquiring fingerprint image, the area size that finger touches to be used to carry out fingerprint collecting generally in 1.5cm*1.5cm
Image sensing chip needs to have biggish specific dimensions.It should be noted that image sensing chip is not limited to for fingerprint
The image sensing chip of acquisition, can be to be any type of for acquiring the image sensing chip of optical signal.
As above-mentioned for image sensing chip and control chip, since the size of image sensing chip is larger, if using
The prior art is packaged, then needing for image sensing chip to be placed in control beneath chips, but will lead to control core in this way
Piece blocks its functional areas.Therefore, the prior art packaged type limitation chip encapsulated type, can not to any two kinds of chips into
Row encapsulation.
To solve the above-mentioned problems, the utility model embodiment provides a kind of chip-packaging structure and chip package side
Control chip fitting is fixed on the first surface of circuit board by method, and the setting of image sensing chip is deviated from circuit in control chip
The other side of plate, and control chip between have gap, convenient for control chip and image sensing chip respectively with circuit board
It is electrically connected, it is not necessary that package position is arranged according to the size of coremaking piece and image sensing chip.And control chip is placed in
Between image sensing chip and circuit board, the photosensitive pixel of image sensing chip will not be generated and be blocked.
To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, with reference to the accompanying drawing and have
Body embodiment is described in further detail the utility model.
With reference to Fig. 1, Fig. 1 is a kind of schematic diagram of chip-packaging structure provided by the embodiment of the utility model, chip envelope
Assembling structure includes: circuit board 11, and the circuit board 11 includes opposite first surface and second surface；The circuit board 11 is also
Including the interconnection circuit 110 for being connect with external circuit；Fitting is fixed on the control chip 12 of the first surface, the control
Coremaking piece 12 is connect with the interconnection circuit 11；Image of the control chip 12 away from 11 side of circuit board is arranged in pass
Sense chip 13, has a gap between the image sensing chip 13 and the control chip 12, the image sensing chip 13 with
The interconnection circuit connection；The cover board 14 that the image sensing chip 13 deviates from 11 side of circuit board is set；The lid
Plate 14 and the circuit board 11 form an enclosure space, and the image sensing chip 13 is located at the envelope with the control chip 12
It closes in space.Optionally, the cover board 14 is glass plate.
As it can be seen that the control fitting of chip 12 is directly fixed on electricity in chip-packaging structure described in the utility model embodiment
The surface of road plate 11, at it away from the side of the circuit board 11 setting image sensing chip 13, image sensing chip 13 and control
There is gap, in order to which the control chip 12 is electrically connected with the interconnection circuit, due to two cores between coremaking piece 12
There is gap, relative to the prior art that two chips are directly contacted to fixed fitting, the utility model embodiment institute between piece
Technical solution is stated to be not necessarily to that the relative position of two chips is arranged according to the size of two chips, it thus can be by image sensing core
The top of the setting control chip 12 of piece 13, so that control chip 12 will not generate screening to the photosensitive pixel of image sensing chip 13
Gear guarantees the imaging effect of image sensing chip 13.
As shown in Figure 1, the interconnection circuit 110 includes: the first contact jaw 111 and that the first surface is arranged in
Two contact jaws 112；First contact jaw 111 is for connecting the control chip 12, and second contact jaw 112 is for connecting
The image sensing chip 13；The third contact jaw 113 of the second surface is set, and the third contact jaw 113 is for connecting
Connect the external circuit；Wherein, first contact jaw 111 is contacted by the first wiring route 115 with the corresponding third
113 connection of end, second contact jaw 112 are connected by the second wiring route 114 with the corresponding third contact jaw 113,
First wiring route 115 insulate with second wiring route 114.First wiring route 115 and second cloth
Line route 114 is separately connected different third contact jaws 113.
On the direction perpendicular to the circuit board 11, the control chip 12 and the image sensing chip 13 at least portion
Divide overlapping.In mode shown in Fig. 1, on the direction perpendicular to the circuit board 11, the control chip 12 is located at the shadow
As sensing chip 13 is in the projection of the circuit board 11, that is to say, that the image sensing chip 13 is blocked completely described in this
Control chip 12.
As shown in Figure 1, having the first gasket 15, the image between the image sensing chip 13 and the circuit board 11
Sensing chip 13 is fixed by first gasket 15 and the circuit board 11.
The image sensing chip 13 has opposite front and back, and the back side includes first area and the secondth area
Domain；First gasket 15 is between the first area and the circuit board 11；The control chip 12 is located at described the
Two regions are in the orthographic projection of the circuit board 11.That is, the image sensing chip 13 by the first area with
The circuit board 11 is fixedly connected, and the control chip 12 being disposed below is blocked by the second area.
Optionally, first gasket 15 is silicon spacer, ceramic gasket or metal gasket.First gasket of these materials
15, on the one hand there is enough mechanical strengths to support the image sensing chip 13, on the other hand, have preferable thermal conductivity
Can, the heat that image sensing chip generates can be quickly transmitted on circuit board 11, pass through the backside radiator of circuit board 11.
And due to having gap between image sensing chip 13 and control chip 12, the heat that image sensing chip 13 generates passes through institute
It states the first gasket 15 and is transferred to the circuit board 11 and radiate, control chip 12 is directly by its back side by heat transmission to electricity
Road plate 11 radiates, and has gap between two chips, avoids interfering with each other for heat between two chips, is particularly located at
The heat of above-mentioned image sensing chip 13 will not increase the heat dissipation load of control chip 12, it is ensured that preferable heat dissipation effect.
As shown in Figure 1, there is setting spacing, to avoid installation institute between the cover board 14 and the image sensing chip 13
Touching is generated to the image sensing chip 13 fixed when stating cover board 14, the stability to image sensing chip 13 is avoided to make
At adverse effect.The cover board 14 is fixed by the second gasket 16 and the circuit board 11.The height of second gasket 16 is greater than the
The height of one gasket 15.Second gasket 16 divides for two parts.The image sensing chip 13 and the equal position of the control chip 12
Between the two parts.Optionally, second gasket 16 is silicon spacer, ceramic gasket or metal gasket.
With reference to Fig. 2, Fig. 2 is a kind of top view of circuit board provided by the embodiment of the utility model, in mode shown in Fig. 2,
Circuit board 11 is parallel to X/Y plane for the surface of binding chip, and in X-axis, which includes region 31 and be located at area
The region 32 and region 33 of 31 two sides of domain.Region 32 and region 33 are used to be respectively set two parts of the second disc 16.Region 31
With subregion 311 and subregion 312, circuit board 11 is run through in Y-axis in first area 311.Subregion 311 is for being arranged the
One gasket 15, subregion 312 is for being arranged control chip 12.In Y-axis, the width of the first gasket 15 can be with circuit board 11
Of same size, the width of image sensor 13 can be with the of same size of circuit board 11 or less than the width of circuit board 11.Control
Coremaking piece 12 is located in subregion 312.Subregion 312 is located in the both sides opposite in Y-axis of circuit board 11.
After the both sides of cover board 14 are separately fixed on two parts of the second gasket 12, in order to guarantee sealing effect, it can incite somebody to action
The other both sides of the 14 of the cover board are fixed by packaging plastic and the circuit board 11 sealing.Alternatively, using the of frame structure
Two gaskets, one end of the frame structure are fixed on the edge position of the circuit board 11, and the cover board 14 is fixed on institute
The other end of frame structure is stated, to form sealing structure.
In mode shown in Fig. 1, the third contact jaw 113 is pad.In other modes, the third contact jaw 113
It can also be structure as shown in Figure 3.
With reference to Fig. 3, Fig. 3 is the schematic diagram of another chip-packaging structure provided by the embodiment of the utility model, which
It is with mode difference shown in Fig. 1, the third contact jaw 113 is tin ball.
In order to reduce adverse effect of the reflected light to 13 image quality of image sensing chip, second gasket 16 is set
Inner wall has anti-reflection structure.The anti-reflection structure can be the antireflection layer that 16 inner wall of the second gasket is arranged in, or
The thickness that second gasket 16 is arranged in person is directed toward on the direction of the circuit board 11 by the cover board 14 and is gradually reduced, thus shape
At an inclined-plane, to reduce the light that the inner wall of the second gasket 16 is reflected into the image sensing chip 13.
In the utility model embodiment, the image sensor 13 is connect by conducting wire 18 with interconnection circuit 110, specifically
, connect by conducting wire 18 with the second contact jaw 112, to be connect with the second wiring route 114, by with the second wiring route
The third contact jaw 113 of 114 connections is connect with external circuit.The control chip 12 is connected by conducting wire 17 and interconnection circuit 110
Connect, specifically, by conducting wire 17 and the first contact jaw 111, thus with the first wiring route 115, by with the first wiring route
The third contact jaw 113 of 115 connections is connect with external circuit.
With reference to Fig. 4, Fig. 4 is a kind of front plan view of image sensor provided by the embodiment of the utility model, shown shadow
As sensing chip 13 has opposite front and back；Its back side is arranged towards the circuit board 11；Its front has light-sensitive image
Element and the first weld pad 131 being connect with the photosensitive pixel；Wherein, first weld pad 131 by conducting wire 18 and it is described mutually
Join circuit connection.The photosensitive pixel is not shown in Fig. 4.The front of the image sensing chip 13 have functional areas 132 and
Surround the peripheral region of functional areas 132.The photosensitive pixel is located in the functional areas 132.
It is firstth area at 12 back side of image sensing chip in chip-packaging structure described in example in view of the utility model
Domain is fixed by the first gasket 15 and circuit board 11.For the ease of the wiring of conducting wire 18, the first weld pad 131 is set and is located at the shadow
One end as 13 front of sensing chip close to the first area, as shown in figures 1 and 3 in this way, all first weld pads 131
To be electrically connected by the conducting wire 18 with circuit board 11 in the left side of the image sensing chip 13.First weld pad 131 can be with
The edge of 13 frontal left of image sensing chip flushes, can also be at regular intervals with edge tool, can be according to specific
The first weld pad 1311 is arranged in the position at the end in demand.
With reference to Fig. 5, Fig. 5 is a kind of front plan view for controlling chip provided by the embodiment of the utility model, the control
Chip 12 has opposite front and back, and the back side is fixed on the surface of the circuit board 11.Its front has functional areas 122
And the second weld pad 121 connected with functional areas 122, it is two groups that the second weld pad 121, which is divided to, in the X-axis direction, this two group second weldering
Pad 121 is separately positioned on the two sides of functional areas 122.
As can be seen from the above description, in chip-packaging structure provided by the embodiment of the utility model, control chip 12 is pasted
The first surface for being fixed on circuit board 11 is closed, control chip 12 is arranged in away from the another of circuit board 11 in image sensing chip 13
Side, and control chip 12 between have gap, convenient for control chip 12 and image sensing chip 13 respectively with circuit board 11
It is electrically connected, it is not necessary that package position is arranged according to the size of coremaking piece 12 and image sensing chip 13.And chip will be controlled
12 are placed between image sensing chip 13 and circuit board 11, will not generate and block to the photosensitive pixel of image sensing chip 13.
Based on said chip encapsulating structure embodiment, another embodiment of the utility model additionally provides a kind of chip package side
Method, for the chip packaging method as shown in Fig. 6-Figure 12, Fig. 6-Figure 12 is a kind of chip package provided by the embodiment of the utility model
The flow diagram of method, the chip packaging method include:
Step S11: as shown in fig. 6, providing a package substrate 100.
The package substrate 100 includes multiple circuit boards 11；There is cutting channel 10 between the adjacent circuit board 11；Institute
Stating circuit board 11 includes opposite first surface and second surface；The circuit board 11 further includes for connecting with external circuit
Interconnection circuit 110；
The interconnection circuit 110 includes: the first contact jaw 111 and the second contact jaw that the first surface is arranged in
112；And the third contact jaw 113 of the second surface is set, the third contact jaw 113 is for connecting the external electrical
Road；First contact jaw 111 is connected by the first wiring route 115 with the corresponding third contact jaw 113, and described second
Contact jaw 112 is connected by the second wiring route 114 with the corresponding third contact jaw 113, first wiring route 115
It insulate with second wiring route 114.
Step S12: as shown in fig. 7, in the fixed control chip 12 of first surface fitting of the circuit board 11, the control
Chip 12 is connect with the interconnection circuit 110.
In the step, the fixed control chip 12 of first surface fitting in the circuit board 11 includes: by described the
One contact jaw 111 is connect with the control chip 12.It can be by conducting wire 17 by the control chip 12 and the interconnection circuit
110 connections.
Step S13: as shown in Figure 8 and Figure 9, image is set away from 11 side of package substrate in the control chip 12
Sensing chip 13.
It is described that image sensing chip packet is set away from 11 side of package substrate in the control chip 12 in the step
It includes: second contact jaw 112 is connect with the image sensing chip 13.The image sensing chip 13 and the control core
There is gap, the image sensing chip 13 is connect with the interconnection circuit 110 between piece 12.By conducting wire 18 by the image
Sensing chip 13 is connect with the interconnection circuit 110.
On the direction perpendicular to the package substrate 100, the control chip 12 and the image sensing chip 13 to
Small part is overlapping.Preferably, on the direction perpendicular to the package substrate 100, the control chip 12 is located at the image
Sensing chip 13 is in the projection of the package substrate 100.
It is described that image sensing chip is set away from 100 side of package substrate in the control chip 12 in the step
13 include: that the image sensing chip 13 is fixed by the first gasket 15 and the package substrate 100.Firstly, such as Fig. 8 institute
Show, first gasket 15 is set in the predeterminable area of the first surface of each circuit board 11, the height of the first gasket 15 is higher than control
The height of chip 12.Then, as shown in figure 9, on first gasket 15 stabilized image sensing chip 13.
The image sensing chip 13 has opposite front and back, and the back side includes first area and the secondth area
Domain；Described by the image sensing chip 13 includes: described first by the first gasket 15 and the fixation of package substrate 100
Fixed first gasket 15 in region；Wherein, the control chip 12 is located at the second area in the package substrate 100
In orthographic projection.Wherein, first gasket 15 is silicon spacer, ceramic gasket or metal gasket.
The image sensing chip 13 has opposite front and back；Its back side is arranged towards the package substrate 100；
The first weld pad 131 that its front has photosensitive pixel and connect with the photosensitive pixel；It is described to be carried on the back in the control chip 12
It include: by first weld pad 131 and the interconnection circuit from 100 side of package substrate setting image sensing chip 13
110 are connected by conducting wire 18.
Step S14: as shown in Figure 10 and Figure 11, setting and the relatively-stationary capping 140 of the package substrate 100.
The capping 140 is glass plate.There is setting spacing between the capping 140 and the image sensing chip 13.
The capping 140 has multiple cover boards 14 corresponding with circuit board 11, and after subsequent technique is split, each chip of formation is sealed
In assembling structure, a relatively-stationary cover board 14 and circuit board 11 are all had.
In the step, the setting includes: by the capping 140 with the relatively-stationary capping 140 of the package substrate 100
It is fixed by the second gasket 16 and the package substrate 100.Wherein, second gasket 16 be silicon spacer, ceramic gasket or
Metal gasket.Firstly, as shown in Figure 10, the second gasket 16 is fixed on package substrate 100, then as shown in figure 11, second
Fixed capping 140 on gasket 16.The second gasket of part 16 between two neighboring chip-packaging structure can be structure as a whole, after
Continue and separated in cutting technique, or isolated two parts.
Step S15: as shown in figure 12, the package substrate 100 and the capping are divided based on the cutting channel 10
140, form the chip-packaging structure of multiple simple grains, in each chip-packaging structure, the cover board 14 and the circuit board
11 form an enclosure space, and the image sensing chip 13 is located in the enclosure space with the control chip 12.
In the mode shown in Fig. 6-Figure 12, the third contact jaw 113 is pad, for making chip envelope as shown in Figure 1
Assembling structure, in other modes, the third contact jaw 113 can also be tin ball as shown in Figure 3, at this time chip packaging method with
It is identical to make chip-packaging structure shown in Fig. 1, repeats no more again.
Packaging method described in the utility model embodiment can be used for making the encapsulating structure as described in above-described embodiment, can be with
It is not necessary that package position is arranged according to the size of coremaking piece and image sensing chip, manufacture craft is simple, low manufacture cost.
With reference to Figure 13, Figure 13 is a kind of sectional drawing of chip provided by the embodiment of the utility model, and shown chip 23 is just
The functional area 231 of mask and weld pad 232, and front covering matcoveredn 200, are used for functional section 231 and weld pad 232.
Can based on demand setting weld pad 232 and functional areas 231 in the positive layout type of chip 23, formed above-mentioned control chip with
And image sensing chip.
With reference to Figure 14-Figure 16, Figure 14-Figure 16 is a kind of process of chip manufacture method provided by the embodiment of the utility model
Schematic diagram, the production method include:
Step S21: as shown in Figure 14 and Figure 15, providing a wafer 43, which has multiple chips 23, adjacent chips
There is cutting channel 41 between 23.Figure 14 is the top view of wafer 43, and Figure 15 is sectional drawing of the Figure 14 in P-P '.
Step S22: as shown in figure 16, the wafer 43 is divided based on cutting channel 41, forms the chip 23 of multiple simple grains.
Production method described in Figure 14-Figure 16 can prepare multiple chips 23, manufacture craft letter simultaneously by wafer scale technique
It is single, low manufacture cost.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For chip disclosed in embodiment
For packaging method, since it is corresponding with chip-packaging structure disclosed in embodiment, so be described relatively simple, correlation
Place illustrates referring to chip-packaging structure corresponding part.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments can be realized professional and technical personnel in the field or using originally practical new
Type.Various modifications to these embodiments will be readily apparent to those skilled in the art, and determine herein
The General Principle of justice can be realized in other embodiments without departing from the spirit or scope of the present utility model.Cause
This, the present invention will not be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The widest scope consistent with features of novelty.
Claims (13)
1. a kind of chip-packaging structure, which is characterized in that the chip-packaging structure includes:
Circuit board, the circuit board include opposite first surface and second surface；The circuit board further include for it is outer
The interconnection circuit of portion's circuit connection；
Fitting is fixed on the control chip of the first surface, and the control chip is connect with the interconnection circuit；
Be arranged in it is described control chip deviate from the circuit board side image sensing chip, the image sensing chip with it is described
Controlling has gap between chip, the image sensing chip is connect with the interconnection circuit；
The cover board that the image sensing chip deviates from the circuit board side is set；The cover board and the circuit board form one
Enclosure space, the image sensing chip and the control chip are located in the enclosure space.
2. chip-packaging structure according to claim 1, which is characterized in that the interconnection circuit includes:
The first contact jaw and the second contact jaw of the first surface are set；First contact jaw is for connecting the control
Coremaking piece, second contact jaw is for connecting the image sensing chip；
The third contact jaw of the second surface is set, and the third contact jaw is for connecting the external circuit；
Wherein, first contact jaw is connected by the first wiring route with the corresponding third contact jaw, and described second connects
Contravention is connected by the second wiring route with the corresponding third contact jaw, first wiring route and second wiring
Line insulation.
3. chip-packaging structure according to claim 2, which is characterized in that the third contact jaw is pad or tin
Ball.
4. chip-packaging structure according to claim 1, which is characterized in that on the direction perpendicular to the circuit board,
The control chip and the image sensing chip are at least partly overlapping.
5. chip-packaging structure according to claim 4, which is characterized in that on the direction perpendicular to the circuit board,
The control chip is located at the image sensing chip in the projection of the circuit board.
6. chip-packaging structure according to claim 1, which is characterized in that the image sensing chip and the circuit board
Between there is the first gasket, the image sensing chip fixed by first gasket with the circuit board.
7. chip-packaging structure according to claim 6, which is characterized in that the image sensing chip have it is opposite just
Face and the back side, the back side include first area and second area；
First gasket is between the first area and the circuit board；
The control chip is located at the second area in the orthographic projection of the circuit board.
8. chip-packaging structure according to claim 6, which is characterized in that first gasket is silicon spacer, ceramic blanket
Piece or metal gasket.
9. chip-packaging structure according to claim 1, which is characterized in that the image sensing chip have it is opposite just
Face and the back side；Its back side is arranged towards the circuit board；Its front has photosensitive pixel and connect with the photosensitive pixel
First weld pad；
Wherein, first weld pad is connect by conducting wire with the interconnection circuit.
10. chip-packaging structure according to claim 1, which is characterized in that the cover board and the image sensing chip
Between have setting spacing.
11. chip-packaging structure according to claim 1, which is characterized in that the cover board by the second gasket with it is described
Circuit board is fixed.
12. chip-packaging structure according to claim 11, which is characterized in that second gasket is silicon spacer, ceramics
Gasket or metal gasket.
13. chip-packaging structure according to claim 1, which is characterized in that the cover board is glass plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821275297.2U CN208580746U (en) | 2018-08-08 | 2018-08-08 | A kind of chip-packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821275297.2U CN208580746U (en) | 2018-08-08 | 2018-08-08 | A kind of chip-packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208580746U true CN208580746U (en) | 2019-03-05 |
Family
ID=65512045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821275297.2U Active CN208580746U (en) | 2018-08-08 | 2018-08-08 | A kind of chip-packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208580746U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766974A (en) * | 2018-08-08 | 2018-11-06 | 苏州晶方半导体科技股份有限公司 | A kind of chip-packaging structure and chip packaging method |
-
2018
- 2018-08-08 CN CN201821275297.2U patent/CN208580746U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108766974A (en) * | 2018-08-08 | 2018-11-06 | 苏州晶方半导体科技股份有限公司 | A kind of chip-packaging structure and chip packaging method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100449754C (en) | Semiconductor device and its aking method | |
| CN107134443B (en) | The packaging method of flip chip, display device and integrated circuit | |
| US10600830B2 (en) | Sensor package structure | |
| US20110012250A1 (en) | Semiconductor device and method of fabrication | |
| CN104094405A (en) | Imaging unit and imaging apparatus | |
| TW200406912A (en) | Solid-state photographing apparatus and its manufacturing method | |
| CN103383931B (en) | Electronic system with composite base material | |
| JP2005079536A (en) | Method of manufacturing solid-state imaging apparatus | |
| TWI228317B (en) | Semiconductor device having clips for connecting to external elements | |
| JP3173006U (en) | Sensor element | |
| CN105590926B (en) | Electronic building brick, electronic module, its manufacturing method and electronic device | |
| JP2017191895A (en) | Semiconductor device and method of manufacturing the same | |
| JP2008124176A (en) | Power semiconductor device | |
| TWI270963B (en) | Package module with alignment structure and electronic device with the same | |
| CN105448860B (en) | Semiconductor device | |
| CN208580746U (en) | A kind of chip-packaging structure | |
| US8049244B2 (en) | Package substrate and light emitting device using the same | |
| CN102782875B (en) | Solar module II | |
| CN108766974A (en) | A kind of chip-packaging structure and chip packaging method | |
| US20040012095A1 (en) | Semiconductor integrated device and method for manufacturing semiconductor integrated device | |
| CN105185804B (en) | The encapsulating structure and packaging method of focal plane array device | |
| TWI625833B (en) | Packaging structure | |
| US20190139875A1 (en) | Flat no-lead package with surface mounted structure | |
| US20240161534A1 (en) | Fingerprint sensor module and method for manufacturing a fingerprint sensor module | |
| WO2011108051A1 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |