CN208540179U - A kind of LTE_Advanced eats dishes without rice or wine signal analysis device - Google Patents

A kind of LTE_Advanced eats dishes without rice or wine signal analysis device Download PDF

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CN208540179U
CN208540179U CN201721723931.XU CN201721723931U CN208540179U CN 208540179 U CN208540179 U CN 208540179U CN 201721723931 U CN201721723931 U CN 201721723931U CN 208540179 U CN208540179 U CN 208540179U
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fpga
input
output terminal
output end
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陈向民
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Transcom Shanghai Technologies Co Ltd
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Shanghai TransCom Instruments Co Ltd
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Abstract

It eats dishes without rice or wine signal analysis device the utility model discloses a kind of LTE_Advanced, the radiofrequency signal of eating dishes without rice or wine inputs four frequency mixing modules by four road ports and analyzed, and the analytical equipment includes local oscillator module, frequency mixing module, A/D control module, FPGA module, ARM module.The utility model analyzes the signal of different antennae port by independent signal analysis channel, the real-time analysis of spacing wave is realized using multistage FPGA moduleization processing FFT (Fourier transformation), synchronization, channel estimation, channel equalization and cell traversal search, the above downlink space interface signaling analysis of protocol schedule, Base-Band Processing is realized using the high speed operation system of RTOS system, user can pass through removable computer simultaneously, cell phone application controls utility model device, while satisfaction is stablized signal of eating dishes without rice or wine and analyzed, user is also facilitated.

Description

A kind of LTE_Advanced eats dishes without rice or wine signal analysis device
Technical field
It eats dishes without rice or wine signal analysis device the utility model relates to the communications field more particularly to a kind of LTE_Advanced.
Background technique
LTE_Advanced is the evolution of LTE, meets the demand of the IMT-Advanced technology collection of ITU-R, LTE is with it The advantages that high-speed low time delay, obtains the extensive concern of the world each mainstream communication equipment vendor and operator.
With the propulsion that deepens continuously that LTE_Advanced technology develops, gradually mature, the fortune of LTE_Advanced technology Battalion quotient's arranges net on a large scale, key components extensive pass by industry of the signal analytical and testing instrument as industrial chain of eating dishes without rice or wine Note.As carrier network stabilization, important leverage is normally run, signal analytical and testing instrument of eating dishes without rice or wine plays more and more important Effect.Signal analyzer table of eating dishes without rice or wine is arranged net and an important link of the later period network optimization as early period, is played more next Important role.
For signal analysis of eating dishes without rice or wine, traditional measuring device would generally carry out magnanimity to data using data collecting card and adopt Then collection carries out off-line analysis, this mode can be very slow toward speed, wastes a large amount of human and material resources, while also needing profession Research staff analyzes, and accidental problem is less susceptible to capture.
Therefore, there are also to be developed for the prior art.
Utility model content
Place in view of above-mentioned deficiencies of the prior art, it is empty that the purpose of this utility model is to provide a kind of LTE_Advanced Mouth signal analysis device, it is intended to which realization can in real time be monitored spacing wave, analyze, and report problem clew, while can be real When measurement data and fault location information are stored according to time and geographical position coordinates, so as to engineers and technicians Check the purpose of analysis.
In order to achieve the above object, the utility model takes following technical scheme:
A kind of LTE_Advanced eats dishes without rice or wine signal analysis device, and the radiofrequency signal of eating dishes without rice or wine inputs four by four road ports Frequency mixing module is analyzed, and the analytical equipment includes local oscillator module, frequency mixing module, A/D control module, FPGA module, at ARM Manage device module, the first local oscillator module output end connect with the first frequency mixing module output end, first frequency mixing module it is defeated Outlet is connected with the input terminal of the first A/D control module, the output end and the first FPGA input terminal of the first A/D control module Connection, the first FPGA input/output terminal are connected with the 2nd FPGA input/output terminal；
The second local oscillator module output end is connect with the second frequency mixing module output end, the second frequency mixing module output end It is connected with the 2nd A/D control module input terminal, the output end of the 2nd A/D control module is connect with the 2nd FPGA input terminal；
The third local oscillator module output end is connect with third frequency mixing module output end, the third frequency mixing module output end It is connected with the 3rd A/D control module input terminal, the 3rd A/D control module output end is connected with the 3rd FPGA input terminal, institute The 3rd FPGA input/output terminal is stated to be connected with the 2nd FPGA input/output terminal；
The 4th local oscillator module output end is connect with the 4th frequency mixing module output end, the 4th frequency mixing module output end It is connected with the 4th A/D control module input terminal, the 4th A/D control module output end is connected with the 4th FPGA input terminal, institute The 4th FPGA input/output terminal is stated to be connected with the 3rd FPGA input/output terminal；
The 2nd FPGA input/output terminal is also connected with the 5th FPGA input/output terminal, the 3rd FPGA input and output End is also connected with the 6th FPGA input/output terminal, and the 5th FPGA input/output terminal is connected with the 6th FPGA input/output terminal, The 5th FPGA input/output terminal is also connected with the 7th FPGA input/output terminal respectively with the 6th FPGA input/output terminal, described 7th FPGA input/output terminal is connected with the first arm processor input/output terminal, the first arm processor input/output terminal with Second arm processor input/output terminal is connected, and the input of the second arm processor input/output terminal and control display module is defeated Outlet is connected.
Further, the first A/D control module, the 2nd A/D control module, the 3rd A/D control module, the 4th A/D Control module uses 245.76MHZ sampling clock.
Further, first FPGA module, the second FPGA module, third FPGA module, the 4th FPGA module, are used for Synchronous different antennae port signal and Fourier transformation.
Further, the 5th FPGA module of the channel estimation and channel equalization of the responsible different antennae port data In channel estimation use the channel estimation method based on least square.
Further, the 7th FPGA module includes CRC, convolution, Turbo, rate-matched and Viterbi decoding etc..
The utility model compared with prior art the utility model has the advantages that the utility model by independent signal analysis channel come point The signal for analysing different antennae port handles FFT (Fourier transformation), synchronization, channel estimation, channel using multistage FPGA moduleization Balanced and cell traversal search realizes the real-time analysis of spacing wave, realizes agreement tune using the high speed operation system of RTOS system The above downlink space interface signaling analysis of degree, Base-Band Processing, while user can be by removable computer, cell phone application is to the utility model Device is controlled, and while satisfaction is stablized signal of eating dishes without rice or wine and analyzed, also facilitates user.
Detailed description of the invention
Fig. 1 is that LTE_Advanced provided by the embodiment of the utility model eats dishes without rice or wine the schematic illustration of signal analysis device；
Fig. 2 be LTE_Advanced provided by the embodiment of the utility model eat dishes without rice or wine signal analysis device space interface signaling parsing Result figure；
Fig. 3 is that LTE_Advanced provided by the embodiment of the utility model eats dishes without rice or wine signal analysis device cell search results Figure.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain The utility model is not used to limit the utility model.
It should be noted that it can be directly another when element is referred to as " being fixed on " or " being set to " another element On one element or it may be simultaneously present centering elements.When an element is known as " being connected to " another element, it can To be directly to another element or may be simultaneously present centering elements.
It is only each other relatively it should also be noted that, the positional terms such as left and right, upper and lower in the utility model embodiment Concept or be reference with the normal operating condition of product, and should not be regarded as restrictive.
As shown in Figure 1, a kind of LTE_Advanced for the utility model specific embodiment eats dishes without rice or wine signal analysis device,
A kind of LTE_Advanced eats dishes without rice or wine signal analysis device, and the radiofrequency signal of eating dishes without rice or wine inputs four by four road ports Frequency mixing module is analyzed, and the analytical equipment includes local oscillator module, frequency mixing module, A/D control module, FPGA module, at ARM Device module is managed, 1 output end of the first local oscillator module is connect with 5 output end of the first frequency mixing module, first frequency mixing module 5 Output end is connected with the input terminal of the first A/D control module 9, the output end and the first FPGA13 of the first A/D control module 9 Input terminal connection, the first FPGA13 input/output terminal are connected with the 2nd FPGA14 input/output terminal；
Second local oscillator module, 2 output end is connect with 6 output end of the second frequency mixing module, and second frequency mixing module 6 is defeated Outlet is connected with 10 input terminal of the 2nd A/D control module, and the output end and the 2nd FPGA14 of the 2nd A/D control module 10 are defeated Enter end connection；
3 output end of third local oscillator module is connect with 7 output end of third frequency mixing module, and the third frequency mixing module 7 is defeated Outlet is connected with 11 input terminal of the 3rd A/D control module, and 11 output end of the 3rd A/D control module and the 3rd FPGA15 are inputted End is connected, and the 3rd FPGA15 input/output terminal is connected with the 2nd FPGA14 input/output terminal；
4th local oscillator module, 4 output end is connect with the 4th 8 module output ends of mixing, and the 4th frequency mixing module 8 is defeated Outlet is connected with 12 input terminal of the 4th A/D control module, and 12 output end of the 4th A/D control module and the 4th FPGA16 are inputted End is connected, and the 4th FPGA16 input/output terminal is connected with the 3rd FPGA15 input/output terminal；
The 2nd FPGA14 input/output terminal is also connected with the 5th FPGA17 input/output terminal, and the 3rd FPGA11 is defeated Enter output end to be also connected with the 6th FPGA18 input/output terminal, the 5th FPGA17 input/output terminal and the 6th FPGA18 are inputted Output end is connected, and the 5th FPGA17 input/output terminal and the 6th FPGA18 input/output terminal are also defeated with the 7th FPGA19 respectively Entering output end to be connected, the 7th FPGA19 input/output terminal is connected with 20 input/output terminal of the first arm processor, and described first 20 input/output terminal of arm processor is connected with 21 input/output terminal of the second arm processor, and second arm processor 21 inputs Output end is connected with the input/output terminal of control display module 22.
Specifically, the first A/D control module 9, the 2nd A/D control module 10, the 3rd A/D control module the 11, the 4th The sampling clock of four road D/A conversion units of A/D control module 12 is 245.76MHZ.It is sampled for intermediate frequency data.
Specifically, first FPGA module 13, the second FPGA module 14, third FPGA module 15, the 4th FPGA module 16, for synchronizing different antennae port signal and Fourier transformation.The antenna port signals pass through primary synchronization signal and auxiliary same Step signal synchronizes to position the wireless frame start position of current spatial master base station, generates different community number using following equation calculation Primary synchronization signal and secondary synchronization signal:
Wherein, wherein du(n) for main synchronizing sequence and sequence length be 62, u is ZC root sequence index, j is imaginary unit, N is sequence location；D (n) is secondary synchronization sequences and sequence length be 62, m0/m1 is physical-layer cell identifier,WithFor cyclic shift, c0(n) and c1It (n) is scrambler sequence,WithFor scramble sequence, n is sequence location. It can produce the local primary synchronization signal and secondary synchronization signal of different community number using above-mentioned formula.
It is obtained according to previous step, local primary synchronization signal and secondary synchronization signal, later the main synchronous letter of different community number Number and secondary synchronization signal by Fourier transformation, it is related to data progresss received, obtain master base station cell ID and wirelessly Frame start position.
Specifically, the 5th FPGA module 17 is responsible for the channel estimation and channel equalization of different antennae port data.
So channel estimation uses the channel estimation method based on least square.
As shown in figure 3, the 6th FPGA module 18 is responsible for the traversal search of different community, generated using following equation Locally generated cell special reference:
Cell special reference is related to data progress is received, adjudicate the number of cells under current environment, whereinFor reference signal sequence, j is imaginary unit, nsFor timeslot number, L is the character position in time slot, and RB is resource unit, DL is down channel, and c (i) is random sequence.After locally generated cell special reference, with the data that receive into Row is related, takes different community correlation peak compared with preset peak value decision threshold to determine the cell number under current environment Amount.
Specifically, the 7th FPGA module 19 is responsible for the decoding process of MAC layer, including CRC, convolution, Turbo, rate The channel decoding procedures such as matching and Viterbi decoding.
The first arm processor module 20 is mainly responsible for base band and protocol schedule, and auxiliary SIC is calculated, parsing and MIMO signal analysis, UE signalling analysis；
The second arm processor module 21 is mainly responsible for interface display control module 22 and the first arm processor module 20 interface data transmission and the transmitting of interface display parameter.Due to requiring the real time parsing of soul, the first ARM processing 20 operating system of device module uses RTOS system, which can satisfy the fast resolving of protocol signaling by rapid computations, by In data processing without too high request, therefore 21 operating system of the second arm processor module uses linux system.
The utility model analyzes the signal of different antennae port by independent signal analysis channel, using multistage FPGA mould Blockization handles the reality of FFT (Fourier transformation), synchronization, channel estimation, channel equalization and cell traversal search realization spacing wave When analyze, realize that the above downlink space interface signaling of protocol schedule, Base-Band Processing is analyzed using the high speed operation system of RTOS system, together When user utility model device can be controlled by removable computer, cell phone application, meet stablize eat dishes without rice or wine signal analysis While, also facilitate the monitoring and use of user.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model Protection scope within.

Claims (5)

  1. A kind of signal analysis device 1. LTE_Advanced eats dishes without rice or wine, it is characterised in that: the analytical equipment packet described in signal of eating dishes without rice or wine Include local oscillator module, frequency mixing module, A/D control module, FPGA module, arm processor module, the first local oscillator module output end and The connection of one frequency mixing module output end, the output end of first frequency mixing module are connected with the input terminal of the first A/D control module, institute The output end for stating the first A/D control module is connect with the first FPGA input terminal, the first FPGA input/output terminal and second FPGA input/output terminal is connected；
    Second local oscillator module output end is connect with the second frequency mixing module output end, the second frequency mixing module output end and the 2nd A/ D control module input terminal is connected, and the output end of the 2nd A/D control module is connect with the 2nd FPGA input terminal；
    Third local oscillator module output end is connect with third frequency mixing module output end, the third frequency mixing module output end and the 3rd A/ D control module input terminal is connected, and the 3rd A/D control module output end is connected with the 3rd FPGA input terminal, the third FPGA input/output terminal is connected with the 2nd FPGA input/output terminal；
    4th local oscillator module output end is connect with the 4th frequency mixing module output end, the 4th frequency mixing module output end and the 4th A/ D control module input terminal is connected, and the 4th A/D control module output end is connected with the 4th FPGA input terminal, and the described 4th FPGA input/output terminal is connected with the 3rd FPGA input/output terminal；
    The 2nd FPGA input/output terminal is also connected with the 5th FPGA input/output terminal, and the 3rd FPGA input/output terminal is also It is connected with the 6th FPGA input/output terminal, the 5th FPGA input/output terminal is connected with the 6th FPGA input/output terminal, described 5th FPGA input/output terminal is also connected with the 7th FPGA input/output terminal respectively with the 6th FPGA input/output terminal, and the described 7th FPGA input/output terminal is connected with the first arm processor input/output terminal, the first arm processor input/output terminal and second Arm processor input/output terminal is connected, the input/output terminal of the second arm processor input/output terminal and control display module It is connected.
  2. The signal analysis device 2. LTE_Advanced according to claim 1 eats dishes without rice or wine, it is characterised in that: the first A/D Control module, the 2nd A/D control module, the 3rd A/D control module, the 4th A/D control module, when being sampled with 245.76MHZ Clock.
  3. The signal analysis device 3. LTE_Advanced according to claim 1 eats dishes without rice or wine, it is characterised in that: the first FPGA Module, the second FPGA module, third FPGA module, the 4th FPGA module, for synchronizing different antennae port signal and Fourier Transformation.
  4. The signal analysis device 4. LTE_Advanced according to claim 1 eats dishes without rice or wine, it is characterised in that: the responsible difference Channel estimation in the channel estimation of antenna port data and the 5th FPGA module of channel equalization, which uses, is based on least square Channel estimation method.
  5. The signal analysis device 5. LTE_Advanced according to claim 1 eats dishes without rice or wine, it is characterised in that: the 7th FPGA Module includes CRC, convolution, Turbo, rate-matched and Viterbi decoding etc..
CN201721723931.XU 2017-12-12 2017-12-12 A kind of LTE_Advanced eats dishes without rice or wine signal analysis device Active CN208540179U (en)

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Application Number Priority Date Filing Date Title
CN201721723931.XU CN208540179U (en) 2017-12-12 2017-12-12 A kind of LTE_Advanced eats dishes without rice or wine signal analysis device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201721723931.XU CN208540179U (en) 2017-12-12 2017-12-12 A kind of LTE_Advanced eats dishes without rice or wine signal analysis device

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Address after: Block C, No. 7, Lane 205, Gaoji Road, Songjiang District, Shanghai, 201601

Patentee after: Chuangyuan Xinke (Shanghai) Technology Co.,Ltd.

Address before: 200000 building 6, No. 351, siban Road, Sijing Town, Songjiang District, Shanghai

Patentee before: TRANSCOM INSTRUMENTS Co.,Ltd.

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