CN208460001U - A kind of nonvolatile semiconductor memory - Google Patents
A kind of nonvolatile semiconductor memory Download PDFInfo
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- CN208460001U CN208460001U CN201820823814.9U CN201820823814U CN208460001U CN 208460001 U CN208460001 U CN 208460001U CN 201820823814 U CN201820823814 U CN 201820823814U CN 208460001 U CN208460001 U CN 208460001U
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Abstract
The utility model discloses a kind of nonvolatile semiconductor memories, are related to chip technical field of memory.The memory includes: memory cell array, wherein being stored at least a system parameter；Data buffer area is connected with the memory cell array and codec respectively；It include the codec of default decoding process；Wherein, when the memory, which receives, powers on triggering command, the data buffer area reads to obtain system parameter from the memory cell array；The codec reads the system parameter from the data buffer area, is decoded error correction according to the system parameter and coding parameter, and the data buffer area is written in the system parameter after decoding and error；The coding parameter is to obtain after being encoded by the pre-arranged code mode to the system parameter；The pre-arranged code mode is corresponding with the default decoding process.Achieve the beneficial effect for powering on success rate and service life for improving nonvolatile semiconductor memory.
Description
Technical field
The utility model relates to chip technical field of memory, and in particular to a kind of nonvolatile semiconductor memory.
Background technique
With the continuous development and progress of integrated circuit technology, the size of the devices such as memory is smaller and smaller, and then causes
Electrical property interference between adjacent devices is increasing.For example, Nor-Flash, Nand-Flash, EEPROM (Electrically
Erasable Programmable Read-Only Memory, electrically erasable read-only memory) etc. non-volatile semiconductor storages
Device aging with the increase for using the time changes or is lost so as to cause partial system parameters, and then during electrification reset
It can not be read correctly system parameter, systematic parameter configuration is caused to fail.And the electrification reset of nonvolatile semiconductor memory is used
To realize the important parameter for reading and being stored in chip, it can correctly read parameter and the nonvolatile semiconductor of configuration successful is deposited
Reservoir can work normally, and the nonvolatile semiconductor memory that cannot be read correctly parameter or parameter configuration failure can not
Normal use leads to thrashing.
The prior art uses the mode repeatedly backed up to parameter mainly to prevent the change or loss of data, but with
The aging of device, the parameter of backup also can change or lose, reduce powering on the effect of failure and be not obvious by Backup Data；
And for more Backup Datas, it can be increase accordingly parameter memory module, and then increase the area and cost of chip；In addition, with
The aging of device, power up is also required to read more backup parameters, and then power-on time is caused to be multiplied, and influences device
The performance of part.
Utility model content
In view of the above problems, the utility model is proposed to overcome the above problem in order to provide one kind or at least partly solve
A kind of certainly nonvolatile semiconductor memory of the above problem.
According to the one aspect of the utility model, a kind of nonvolatile semiconductor memory is provided, which is characterized in that institute
Stating memory includes:
Memory cell array, wherein being stored at least a system parameter；
Data buffer area is connected with the memory cell array and codec respectively；
It include the codec of default decoding process；
Wherein, when the memory, which receives, powers on triggering command, the data buffer area is from the storage unit battle array
Column read and obtain system parameter；
The codec reads the system parameter from the data buffer area, according to the system parameter and volume
Code parameter is decoded error correction, and the data buffer area is written in the system parameter after decoding and error；The coding parameter is
It is obtained after being encoded by the pre-arranged code mode to the system parameter；The pre-arranged code mode and the default solution
Code mode is corresponding.
Optionally, the memory cell array, including element storing unit array and code storage cell array, and it is described
Element storing unit array is connected with the code storage cell array；
The data buffer area, including primary data cache area and coded data buffer area, and the primary data cache
Area is connected with the coded data buffer area；
Wherein, when the memory, which receives, powers on triggering command, the data buffer area is from the storage unit battle array
Column read and obtain system parameter and coding parameter.
Optionally, the memory cell array, including element storing unit array and code storage cell array, and it is described
Element storing unit array is mutually not connected to the code storage cell array；
The data buffer area, including primary data cache area and coded data buffer area, and the primary data cache
Area and the coded data buffer area are mutually not connected to；
Wherein, when the memory, which receives, powers on triggering command, the primary data cache area original is deposited from described
Storage unit array reads to obtain system parameter；The coded data buffer area reads from the code storage cell array and is compiled
Code parameter.
Optionally, the codec, including encoding and decoding mould group and coded data memory block；
Wherein, when the memory, which receives, powers on triggering command, the codec is read from the data buffer area
The system parameter is taken, based on the coding parameter that the coded data memory block is stored, by the encoding and decoding mould group to institute
It states system parameter and is decoded error correction.
Optionally, the codec include error checking and correct codec, in forward error correction codec extremely
Few one kind.
Optionally, further includes:
For the parameter configuration module of parameter configuration to be carried out to the memory according to the system parameter after error correction；The ginseng
Number configuration module is connected with the data buffer area；
Wherein, when the codec, which issues error correction, successfully to be instructed, the parameter configuration module is from the data buffer storage
Area reads the system parameter after error correction, and carries out parameter configuration to the memory.
Optionally, further includes:
For detecting the whether stable voltage detection module of upper piezoelectric voltage；The voltage detection module and the data buffer storage
Area is connected；
Wherein, when the memory, which receives, powers on triggering command, touching is powered on described in the voltage detection module judgement
Within a preset range whether the variation range for the corresponding upper piezoelectric voltage that sends instructions；
If the variation range of the upper piezoelectric voltage is within a preset range, the voltage detection module sends voltage stabilization
It instructs to the data buffer area；
When the data buffer area receives voltage stabilization instruction, is read from the memory cell array and be
System parameter.
Optionally, the codec is connected with the memory cell array, deposits in a manner of through pre-arranged code to described
System parameter in storage unit array is encoded.
A kind of nonvolatile semiconductor memory according to the present utility model, comprising: memory cell array, wherein being stored with
At least a system parameter；Data buffer area is connected with the memory cell array and codec respectively；It include default
The codec of decoding process；Wherein, when the memory, which receives, powers on triggering command, the data buffer area is from described
Memory cell array reads to obtain system parameter；The codec reads the system parameter, root from the data buffer area
It is decoded error correction according to the system parameter and coding parameter, and the data are written into the system parameter after decoding and error and are delayed
Deposit area；The coding parameter is to obtain after being encoded by the pre-arranged code mode to the system parameter；It is described default
Coding mode is corresponding with the default decoding process.Thus existing nonvolatile semiconductor memory power up is solved
Time-consuming, powers on failure rate height, the shorter technical problem of life of storage.Achieve raising non-volatile semiconductor storage
The beneficial effect for powering on success rate and service life of device.
The above description is merely an outline of the technical solution of the present invention, in order to better understand the skill of the utility model
Art means, and being implemented in accordance with the contents of the specification, and in order to allow above and other purpose, feature of the utility model
It can be more clearly understood with advantage, it is special below to lift specific embodiment of the present utility model.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as practical to this
Novel limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 shows a kind of structural representation of nonvolatile semiconductor memory according to the utility model one embodiment
Figure；
Fig. 2 shows the step flow charts powered on according to a kind of FLASH memory of the utility model one embodiment；
Fig. 3 shows a kind of structural representation of nonvolatile semiconductor memory according to the utility model one embodiment
Figure；
Fig. 4 shows a kind of structural representation of nonvolatile semiconductor memory according to the utility model one embodiment
Figure；
Fig. 5 shows a kind of structural representation of nonvolatile semiconductor memory according to the utility model one embodiment
Figure；
Fig. 6 shows a kind of structural representation of nonvolatile semiconductor memory according to the utility model one embodiment
Figure；
Fig. 7 shows a kind of structural representation of nonvolatile semiconductor memory according to the utility model one embodiment
Figure；And
Fig. 8 shows a kind of structural representation of nonvolatile semiconductor memory according to the utility model one embodiment
Figure.
Specific embodiment
Exemplary embodiments of the present disclosure are described in more detail below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
It is fully disclosed to those skilled in the art.
Embodiment one
A kind of nonvolatile semiconductor memory provided by the embodiment of the utility model is discussed in detail.
Referring to Fig.1, a kind of structural schematic diagram of nonvolatile semiconductor memory in the utility model embodiment is shown.
It specifically includes:
Memory cell array 10, wherein being stored at least a system parameter；
Data buffer area (sram) 20 is connected with the memory cell array 10 and codec 30 respectively；
It include the codec 30 of default decoding process；
Wherein, when the memory, which receives, powers on triggering command, the data buffer area 20 is from the storage unit
The reading of array 10 obtains system parameter；
The codec 30 reads the system parameter from the data buffer area 20, according to the system parameter with
And coding parameter is decoded error correction, and the data buffer area 20 is written in the system parameter after decoding and error；The coding
Parameter is to obtain after being encoded by the pre-arranged code mode to the system parameter；The pre-arranged code mode with it is described
Default decoding process is corresponding.
Memory in the utility model embodiment can any nonvolatile semiconductor memory, such as it is above-mentioned
Nor-Flash, Nand-Flash, EEPROM etc. are not limited this utility model embodiment.
For the process that memory powers on, it is referred to the step of a kind of FLASH (flash memory) memory shown in Fig. 2 powers on
Flow chart can specifically include following steps:
1, FLASH memory is in original state；
2, exclusive signal is applied to FLASH memory, starts to power；Whether piezoelectric voltage is stable in judgement；If so, executing
Step 3, if it is not, then return step 1；
3, FLASH memory reads the internal configuration information worked normally；
4, judge whether normally to read internal configuration information, if so, 5 are thened follow the steps, if it is not, thening follow the steps 1；
5, FLASH memory carries out parameter configuration according to the internal configuration information read, completes to work on power, Ke Yijin
The operations such as the normal read-write of row.
The triggering command that powers in the utility model embodiment may include the above-mentioned exclusive signal applied to memory,
System parameter may include the internal configuration information in memory above-mentioned.System parameter therein can memory dispatch from the factory or
It is arranged among memory when processing, can system parameter work normally memory and be of crucial importance.
It has been observed that due to aging of device etc., pre-stored system in existing nonvolatile semiconductor memory
System parameter is easy to happen change or loss, so as to cause that can not read correct system parameter in power up, and then leads
Cause powers on failure, and nonvolatile semiconductor memory is not available.It is non-volatile in order to reduce in the utility model embodiment
The error rate of system parameter in semiconductor memory, so that the damage rate of nonvolatile semiconductor memory is reduced, it can be preparatory
It is encoded according to system parameter of the pre-arranged code mode to memory, while the coding parameter obtained after coding being stored in
In reservoir.So after reading obtains system parameter, then can by presetting decoding process, based on the system parameter and
Coding parameter is decoded error correction.It is obvious that pre-arranged code mode is corresponding with default decoding process.For example, if default
Coding mode is error checking and correcting encoder mode, then default decoding process is error checking and correcting decoder side accordingly
Formula；And if pre-arranged code mode is forward error correction coding mode, default decoding process is decoding FEC accordingly
Mode；Etc..
Therefore, it in the utility model embodiment, is decoded and entangles based on system parameter and coding parameter for convenience
Mistake, add in memory one include default decoding process codec, codec is connected with data buffer area, with
The system parameter is read from data buffer area.
It should be noted that coding parameter is by pre-arranged code mode, the system parameter initial to memory is compiled
Code obtain namely coding parameter corresponding to system parameter be the corresponding initial system parameter of memory itself, such as deposit
System parameter when reservoir dispatches from the factory.And the system parameter stored in memory cell array may with memory use and
It changes, such as parameter jump, parameter loss, etc. occurs.Moreover, coding parameter can in the utility model embodiment
To be stored in any free memory of memory, this utility model embodiment is not limited.
Optionally, referring to Fig. 3, the memory cell array 10, including element storing unit array 11 and code storage list
Element array 12, and the element storing unit array 11 is connected with the code storage cell array 12；The data buffer storage
Area 20, including primary data cache area 21 and coded data buffer area 22, and the primary data cache area 21 and the coding
Data buffer area 22 is connected；Wherein, when the memory, which receives, powers on triggering command, the data buffer area 20 is from institute
It states the reading of memory cell array 10 and obtains system parameter and coding parameter.
The memory cell array of memory can be divided into two subarrays at this time, one is for storage system parameter
Element storing unit array, secondly for code storage cell array for storing coding parameter；Either deposited in original
Memory cell array is added on storage unit array, the memory cell array added is original as code storage cell array 12
Memory cell array is as element storing unit array 11.
So at this time receive power on triggering command when, data buffer area 20 can be from element storing unit array 11
Reading obtains system parameter, reads from code storage cell array 12 and obtains coding parameter.Moreover, as above-mentioned it is found that at this time
Primary data cache area 21 and the coded data buffer area 22 can share same data-interface respectively from element storing unit
Array 11 and the code storage cell array 12 read system parameter and coding parameter, naturally it is also possible to utilize respectively different
Data-interface is not limited this utility model embodiment.Moreover, coding parameter and system parameter at this time can store
In same memory page, different memory pages are stored in, this utility model embodiment is not limited.Moreover, because
At least a system parameter is stored in memory cell array, then a system can only be read from memory cell array every time
System parameter can also read more parts of either whole system parameters from memory cell array every time, specifically can basis
Demand carries out customized setting, is not limited to this utility model embodiment.Wherein, the specific system parameter number of storage
It can be preset according to demand, and the system parameter number of different memory may be the same or different, to this
The utility model embodiment is not limited.Moreover, each part system parameter can store in same memory page, also can store
In different memory pages, this utility model embodiment is not limited.
Optionally, referring to Fig. 4, the memory cell array 10, including element storing unit array 13 and code storage list
Element array 14, and the element storing unit array 13 is mutually not connected to the code storage cell array 14；The data are slow
Deposit area 20, including primary data cache area 23 and coded data buffer area 24, and the primary data cache area 23 and the volume
Code data buffer area 24 is mutually not connected to；Wherein, when the memory, which receives, powers on triggering command, the primary data cache
Area 23 obtains system parameter from the element storing unit array 13 reading；The coded data buffer area 24 is deposited from the coding
The reading of storage unit array 14 obtains coding parameter.
At this point, since element storing unit array 13 and code storage cell array 14 are mutually not connected to, and initial data is slow
Deposit area 23 and coded data buffer area 24 be mutually not connected to, then when receive power on triggering command when, primary data cache area 23
It needs to read from the element storing unit array 13 and obtains system parameter；The coded data buffer area 24 is needed from the volume
The reading of code memory unit array 14 obtains coding parameter.
Optionally, referring to Fig. 5, the codec 30, including encoding and decoding mould group 31 and coded data memory block 32；
Wherein, when the memory, which receives, powers on triggering command, the codec 30 is from the data buffer area
20, which read the system parameter, passes through the encoding and decoding mould based on the coding parameter that the coded data memory block 32 is stored
31 pairs of system parameters of group are decoded error correction.
Coding parameter can be stored in encoder, then encoder is then not necessarily to obtain coding from data buffer area at this time
Coding parameter is read without from memory cell array in parameter namely data buffer area.
Optionally, in the utility model embodiment, the codec includes error checking and correction (Error
Checking and Correcting, ECC) codec, forward error correction (Forward Error Correction, FEC) volume
At least one of decoder.
Wherein, forward error correction is also in forward error correction, is the method for increasing data communication confidence level.In one-way communication channel
In, once mistake is found, receiver will have no right to request to transmit again.FEC is the side for transmit using data tediously long information
Method will allow receiver to build data again when occurring mistake in transmission.Forward error correction codec can be based on any one FEC
Technology carries out encoding and decoding, correspondingly, ECC codec can carry out encoding and decoding based on any corresponding ECC technology, to this
The utility model embodiment is not limited.
For same memory, any two parts of system parameters in each part system parameter initially stored are identical
, but in the use process of memory, due to the uncertainty of corrupted data, the impaired feelings of the system parameter of different location
Condition will be different, then the damage situations of each part system parameter would also vary from, and coding parameter is based on storage always
The initial system parameter of device encodes to obtain, so coding parameter is fixed for same memory, then for each
For part system parameter, it is based on coding parameter, the system parameter obtained after decoded error correction would also vary from, and system is joined
Deviation between several and initial memory system parameters would also vary from.For example, for the system parameter having, based on volume
Obtained system parameter may be still damaged more after the code decoded error correction of parameter, then for the system parameter obtained at this time,
Memory is still unable to complete and powers on.
It therefore,, can be in memory in order to further decrease the fraction defective of memory in the utility model embodiment
At least two parts of system parameters are stored with, and according to the sequence of each part system parameter, successively judgement is based on each part system parameter, with
And whether coding parameter, the system parameter obtained after decoded error correction can satisfy requirement of the memory to system parameter, make it
Power on completion.If this part of system parameter and coding parameter are based on, after decoded error correction for a copy of it system parameter
Obtained system parameter can satisfy requirement of the memory to system parameter, it is made to power on completion, then without to subsequent system
Parameter is judged.
So receive power on triggering command when, can first read first part of system parameter of memory.Wherein, it stores
Principle of ordering in device between each part system parameter can carry out customized setting according to demand, to this utility model embodiment
It is not limited.For example, can the storage location of each part system parameter determine to the reading order of each part system parameter, or with
The sequencing of each part system parameter write-in memory determines the reading order, etc. to each part system parameter.
Moreover, the system parameter in memory can be read by any methods availalbe in the utility model embodiment
And coding parameter, this utility model embodiment is not limited.
Optionally, referring to Fig. 6, the memory further include: for according to the system parameter after error correction to the memory
Carry out the parameter configuration module 40 of parameter configuration；The parameter configuration module 40 is connected with the data buffer area 20；Wherein, when
When the sending of codec 30 error correction successfully instructs, the parameter configuration module 40 reads error correction from the data buffer area 20
System parameter afterwards, and parameter configuration is carried out to the memory.
Relative to the system parameter that memory is stored, obtained system parameter is closer to depositing after decoding and error
The initial system parameter of reservoir, therefore then parameter can be carried out to memory according to the system parameter after decoding and error at this time and matched
It sets, to complete to work on power.Parameter Configuration process therein can be with parameter configuration mistake any in existing power up
Journey is similar, will not be repeated here to this utility model embodiment.
Optionally, referring to Fig. 7, the memory further include: for detecting the whether stable voltage detecting mould of upper piezoelectric voltage
Block 50；The voltage detection module 50 is connected with the data buffer area 20；
Wherein, when the memory, which receives, powers on triggering command, the voltage detection module 50 judges described power on
Within a preset range whether the variation range of the corresponding upper piezoelectric voltage of triggering command；
If the variation range of the upper piezoelectric voltage is within a preset range, it is steady that the voltage detection module 50 sends voltage
It is fixed to instruct to the data buffer area 20；
When the data buffer area 20 receives voltage stabilization instruction, read from the memory cell array 10
To system parameter.
It, just can be further when the upper piezoelectric voltage applied to memory reaches certain stationary value in power up
The system parameter in memory is read, therefore in the utility model embodiment, in order to further increase read system ginseng
Several validity can also add a voltage detection module 50 in memory.Wherein, preset range can carry out according to demand
Customized setting is not limited this utility model embodiment.Moreover, the particular content of voltage stabilization instruction can also root
It is preset according to demand, this utility model embodiment is also not limited.
Optionally, referring to Fig. 8, the codec 30 is connected with the memory cell array 10, to pass through pre-arranged code
Mode encodes the system parameter in the memory cell array 10.
It may include above-mentioned pre-arranged code mode in encoding and decoding, then then can use the codec at this time, lead to
It crosses pre-arranged code mode in advance to encode system parameter, codec 30 and 10 phase of memory cell array at this time
Even, the system parameter in the memory cell array 10 is encoded in a manner of through pre-arranged code.
A kind of nonvolatile semiconductor memory according to the present utility model, comprising: memory cell array, wherein being stored with
At least a system parameter；Data buffer area is connected with the memory cell array and codec respectively；It include default
The codec of decoding process；Wherein, when the memory, which receives, powers on triggering command, the data buffer area is from described
Memory cell array reads to obtain system parameter；The codec reads the system parameter, root from the data buffer area
It is decoded error correction according to the system parameter and coding parameter, and the data are written into the system parameter after decoding and error and are delayed
Deposit area；The coding parameter is to obtain after being encoded by the pre-arranged code mode to the system parameter；It is described default
Coding mode is corresponding with the default decoding process.Thus existing nonvolatile semiconductor memory power up is solved
Time-consuming, powers on failure rate height, the shorter technical problem of life of storage.Achieve raising non-volatile semiconductor storage
The beneficial effect for powering on success rate and service life of device.
Algorithm and display are not inherently related to any particular computer, virtual system, or other device provided herein.
Various general-purpose systems can also be used together with teachings based herein.As described above, it constructs required by this kind of system
Structure be obvious.In addition, the utility model is also not for any particular programming language.It should be understood that can use
Various programming languages realize the content of the utility model described herein, and the description that language-specific is done above be in order to
Disclose the preferred forms of the utility model.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that the utility model
Embodiment can be practiced without these specific details.In some instances, be not been shown in detail well known method,
Structure and technology, so as not to obscure the understanding of this specification.
Similarly, it should be understood that in order to simplify the disclosure and help to understand one or more in each utility model aspect
A, in the description above to the exemplary embodiment of the utility model, each feature of the utility model is divided together sometimes
Group is into single embodiment, figure or descriptions thereof.However, the method for the disclosure should not be construed to reflect following meaning
Figure: the requires of the utility model features more more than feature expressly recited in each claim i.e. claimed.
More precisely, as reflected in the following claims, it is in terms of utility model single less than disclosed above
All features of embodiment.Therefore, it then follows thus claims of specific embodiment are expressly incorporated in the specific embodiment party
Formula, wherein separate embodiments of each claim as the utility model itself.
Those skilled in the art will understand that can be carried out adaptively to the module in the equipment in embodiment
Change and they are arranged in one or more devices different from this embodiment.It can be the module or list in embodiment
Member or component are combined into a module or unit or component, and furthermore they can be divided into multiple submodule or subelement or
Sub-component.Other than such feature and/or at least some of process or unit exclude each other, it can use any
Combination is to all features disclosed in this specification (including adjoint claim, abstract and attached drawing) and so disclosed
All process or units of what method or apparatus are combined.Unless expressly stated otherwise, this specification is (including adjoint power
Benefit require, abstract and attached drawing) disclosed in each feature can carry out generation with an alternative feature that provides the same, equivalent, or similar purpose
It replaces.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included certain features rather than other feature, but the combination of the feature of different embodiments mean it is practical new in this
Within the scope of type and form different embodiments.For example, in the following claims, embodiment claimed
It is one of any can in any combination mode come using.
The utility model is limited it should be noted that above-described embodiment illustrates rather than the utility model,
And those skilled in the art can be designed alternative embodiment without departing from the scope of the appended claims.In right
In it is required that, any reference symbol between parentheses should not be configured to limitations on claims.Word "comprising" is not arranged
Except there are element or steps not listed in the claims.Word "a" or "an" located in front of the element does not exclude the presence of more
A such element.The utility model can be by means of including the hardware of several different elements and by means of properly programmed
Computer is realized.In the unit claims listing several devices, several in these devices can be by same
One hardware branch embodies.The use of word first, second, and third does not indicate any sequence.It can be by these lists
Word is construed to title.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Although the preferred embodiment of the utility model embodiment has been described, those skilled in the art are once learnt
Basic creative concept, then additional changes and modifications can be made to these embodiments.So appended claims are intended to solve
It is interpreted as including preferred embodiment and all change and modification for falling into the utility model embodiment range.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements not only wrap
Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, article
Or the element that terminal device is intrinsic.In the absence of more restrictions, being wanted by what sentence "including a ..." limited
Element, it is not excluded that there is also other identical elements in process, method, article or the terminal device for including the element.
It above to a kind of nonvolatile semiconductor memory provided by the utility model, is described in detail, herein
In apply specific case the principles of the present invention and embodiment be expounded, the explanation of above embodiments is only used
The structure and its core concept of the utility model are understood in help；At the same time, for those skilled in the art, according to this reality
With novel thought, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification is not
It is interpreted as limitations of the present invention.
Claims (8)
1. a kind of nonvolatile semiconductor memory, which is characterized in that the memory includes:
Memory cell array, wherein being stored at least a system parameter；
Data buffer area is connected with the memory cell array and codec respectively；
It include the codec of default decoding process；
Wherein, when the memory, which receives, powers on triggering command, the data buffer area is read from the memory cell array
Obtain system parameter；
The codec reads the system parameter from the data buffer area, is joined according to the system parameter and coding
Number is decoded error correction, and the data buffer area is written in the system parameter after decoding and error；The coding parameter is to pass through
The pre-arranged code mode obtains after encoding to the system parameter；The pre-arranged code mode and the default decoding side
Formula is corresponding.
2. memory according to claim 1, which is characterized in that the memory cell array, including element storing unit
Array and code storage cell array, and the element storing unit array is connected with the code storage cell array；
The data buffer area, including primary data cache area and coded data buffer area, and the primary data cache area and
The coded data buffer area is connected；
Wherein, when the memory, which receives, powers on triggering command, the data buffer area is read from the memory cell array
Obtain system parameter and coding parameter.
3. memory according to claim 1, which is characterized in that the memory cell array, including element storing unit
Array and code storage cell array, and the element storing unit array is mutually not connected to the code storage cell array；
The data buffer area, including primary data cache area and coded data buffer area, and the primary data cache area and
The coded data buffer area is mutually not connected to；
Wherein, when the memory, which receives, powers on triggering command, the primary data cache area is from the original storage list
Element array reads to obtain system parameter；The coded data buffer area reads to obtain coding ginseng from the code storage cell array
Number.
4. memory according to claim 1, which is characterized in that the codec, including encoding and decoding mould group and coding
Data storage area；
Wherein, when the memory, which receives, powers on triggering command, the codec reads institute from the data buffer area
System parameter is stated, based on the coding parameter that the coded data memory block is stored, by the encoding and decoding mould group to the system
System parameter is decoded error correction.
5. memory according to claim 1-4, which is characterized in that the codec include error checking and
Correct at least one of codec, forward error correction codec.
6. memory according to claim 1-4, which is characterized in that further include:
For the parameter configuration module of parameter configuration to be carried out to the memory according to the system parameter after error correction；The parameter is matched
Module is set to be connected with the data buffer area；
Wherein, when the codec, which issues error correction, successfully to be instructed, the parameter configuration module is read from the data buffer area
System parameter after taking error correction, and parameter configuration is carried out to the memory.
7. memory according to claim 1-4, which is characterized in that further include:
For detecting the whether stable voltage detection module of upper piezoelectric voltage；The voltage detection module and the data buffer area phase
Even；
Wherein, when the memory, which receives, powers on triggering command, triggering is powered on described in the voltage detection module judgement and is referred to
Whether within a preset range to enable the variation range of corresponding upper piezoelectric voltage；
If the variation range of the upper piezoelectric voltage is within a preset range, the voltage detection module sends voltage stabilization instruction
To the data buffer area；
When the data buffer area receives voltage stabilization instruction, read to obtain system ginseng from the memory cell array
Number.
8. memory according to claim 1-4, which is characterized in that the codec and the storage unit
Array is connected, and encodes in a manner of through pre-arranged code to the system parameter in the memory cell array.
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| CN111949433A (en) * | 2019-05-15 | 2020-11-17 | 北京兆易创新科技股份有限公司 | Processing method of working parameters of nonvolatile memory, control device and memory |
| CN116189745A (en) * | 2023-04-26 | 2023-05-30 | 长鑫存储技术有限公司 | Memory and command sequence processing system |
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| CN111949433A (en) * | 2019-05-15 | 2020-11-17 | 北京兆易创新科技股份有限公司 | Processing method of working parameters of nonvolatile memory, control device and memory |
| CN116189745A (en) * | 2023-04-26 | 2023-05-30 | 长鑫存储技术有限公司 | Memory and command sequence processing system |
| CN116189745B (en) * | 2023-04-26 | 2023-09-15 | 长鑫存储技术有限公司 | Memory and command sequence processing system |
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