CN208283773U - A kind of ultra-wideband ground-penetrating radar (uw-gpr) control system - Google Patents
A kind of ultra-wideband ground-penetrating radar (uw-gpr) control system Download PDFInfo
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- CN208283773U CN208283773U CN201820893603.2U CN201820893603U CN208283773U CN 208283773 U CN208283773 U CN 208283773U CN 201820893603 U CN201820893603 U CN 201820893603U CN 208283773 U CN208283773 U CN 208283773U
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Abstract
The utility model discloses a kind of ultra-wideband ground-penetrating radar (uw-gpr) control systems, including synchronised clock generative circuit;GPS positioning module;Measure turns encoder module;Numerical control delay circuit, ADC analog to digital conversion circuit for equivalent sampling;And master controller.The synchronised clock generative circuit, GPS positioning module measure turns encoder module, numerical control delay circuit, and analog to digital conversion circuit is connected with master controller.The synchronised clock generative circuit is also connected with external ULTRA-WIDEBAND RADAR transmitter.The numerical control delay circuit also occurs circuit with external equivalent sampling sampling pulse and is connected.The ADC analog to digital conversion circuit is also connected with external equivalent sampling sampling gate.The master controller also passes through Ethernet and is connected with external server.The utility model reduces the volume of ultra-wideband ground-penetrating radar (uw-gpr) control system, simplifies the connection cables of system, improves ultra wideband radar system reliability.
Description
Technical field
The utility model relates to ground penetrating radar exploration field more particularly to a kind of control systems for ultra-wideband ground-penetrating radar (uw-gpr)
System.
Background technique
Ultra-wideband ground-penetrating radar (uw-gpr) is used for the detection of security risk below Municipal Underground Piping and means of transportation in recent years.Its
Working principle is that lower section emits ultra-wideband pulse electromagnetic wave signal to radar to the ground, due to the difference of all kinds of dielectric distributions in underground,
There are the differences in amplitude and propagation time for the ultra-wideband pulse electromagnetic wave signal of dieletric reflection.Ultra-wideband ground-penetrating radar (uw-gpr) by pair
The reflection signal received is handled, and all kinds of dielectric distribution situations in underground can be obtained, and is existed to analyze below road
Security risk.
Traditional ultra-wideband ground-penetrating radar (uw-gpr) uses computer as master control equipment, while this radar system uses data
The high-cost data acquisition device such as capture card causes radar overall volume big, at high cost.
Utility model content
Purpose of utility model: in order to overcome the deficiencies in the prior art, the utility model provide a kind of high reliablity,
Small in size, low-cost ultra-wideband ground-penetrating radar (uw-gpr) control system.
Technical solution: to achieve the above object, the technical solution adopted in the utility model are as follows:
A kind of ultra-wideband ground-penetrating radar (uw-gpr) control system, including synchronised clock generative circuit, GPS positioning module, measurement wheel are compiled
Code device module, numerical control delay circuit, analog to digital conversion circuit and master controller for equivalent sampling;The wherein synchronised clock
Generative circuit, GPS positioning module, measurement turns encoder module, numerical control delay circuit, analog to digital conversion circuit with master controller phase
Connection;The synchronised clock generative circuit is connected with ultra-broadband emitter and receiver, and the numerical control delay circuit, modulus turn
Circuit is changed to be connected with external equivalent sampling sampling gate;Master controller is connected with external server.
Preferred: the synchronised clock generative circuit includes crystal oscillator Y1, chip U2, one R1 of resistance, five R5 of resistance, resistance six
R6,50 R50 of resistance, one C1 of capacitor, two C2 of capacitor, three C3 of capacitor, five C5 of capacitor, 50 C50 of capacitor, one L1 of inductance, inductance
Two L2, wherein the pin one of the crystal oscillator Y1 is connect by one L1 of inductance with positive pole, described two one end C2 of capacitor and crystal oscillator
The pin one of Y1 connects, and other end ground connection, described one one end C1 of capacitor is connect with positive pole, and the other end and two C2 of capacitor are grounded
End connection;Described five one end R5 of resistance is connect with the pin two of crystal oscillator Y1, and the other end connects the pin one and pin two of chip U2;
The pin three, four, five, nine, ten, 11,13 of chip U2 links together;Pin 14, positive pole, the capacitor of chip U2
One end of 50 C50 connects, and the other end of 50 C50 of capacitor is grounded;The pin six of chip U2, six R6 of resistance, two L2 of inductance,
One R1 of resistance, output interface P1 are sequentially connected, and the output interface P1 ground connection, output interface P1 is connect with ultra-broadband emitter;
Six R6 of resistance is connect with the connecting pin of two L2 of inductance and five one end C5 of capacitor, the other end ground connection of five C5 of capacitor;Institute
It states one R1 of resistance to connect with the connecting pin of two L2 of inductance and three one end C3 of capacitor, the other end and five C5 of capacitor of three C3 of capacitor
Ground terminal connection;The pin 11 of chip U2 connects 50 one end C50 of capacitor, and the other end of 50 C50 of capacitor is connected to master
Controller.
Preferred: the GPS positioning module includes GPS chip U1, the low noise amplifier chip U3, SAW filter
Chip U4, two R2 of resistance, three R3 of resistance, four R4 of resistance, six C6 of capacitor, seven C7 of capacitor, three L3 of inductance, four L4 of inductance, diode
D1, LED light emitting diode D2, battery B1 and antennal interface P1;Wherein, the pin 11 of GPS chip U1 connects surface acoustic wave filter
The pin four of wave device chip U4, one end of four R4 of resistance are connect with the pin eight, nine of GPS chip U1, and four R4 of resistance
The other end is connect by three L3 of inductance with antennal interface P1, antennal interface P1 ground connection;Pin 22, the resistance of GPS chip U1
Two R2, diode D1, positive pole are sequentially connected;And the anode of battery B1 is connect with the pin 22 of GPS chip U1, cathode
Ground connection, while the pin 24 of GPS chip U1 connects the cathode of battery B1;Pin three, resistance three R3, LED hair of GPS chip U1
Optical diode D2 is sequentially connected, and LED light emitting diode D2 cathode is grounded;The pin 18,19,20, two of GPS chip U1
11 be spi bus interface, and pin one, pin two and the spi bus interface of GPS chip U1 is connected to master controller;Sound table
The pin one of surface wave filter chip U4 is connected to the pin four of low-noise amplifier U3, the pin three of low-noise amplifier U3,
Four L4 of inductance, six C6 of capacitor, antennal interface P1 are sequentially connected;Pin five, the pin six of low-noise amplifier U3 is connecting power supply just
Pole, and seven one end C7 of the capacitor is connect with positive pole, other end ground connection.
Preferred: numerical control delay circuit includes delay chip U5, seven R7 of resistance, eight R8 of resistance, nine R9 of resistance, resistance ten
R10,11 R11 of resistance, 12 R12 of resistance, eight C8 of capacitor;The pin one, two, three, four, five, 23, two of delay chip U5
16,27,29,30,31,32 are connected to master controller;The pin 20,20 of delay chip U5
One is difference output mouth, wherein the pin 20 of delay chip U5, seven R7 of resistance, ten R10 of resistance, 11 R11 of resistance, ground connection
Mouth is sequentially connected;Described 12 one end R12 of resistance is connect with ten R10 of resistance, and the ground terminal of the other end and 11 R11 of resistance connect
It connects;Nine R9 mono- of resistance terminates positive pole, and another ten R10 of terminating resistor deviates from one end of 11 R11 of resistance, the capacitor
One end of eight C8 is connect with the ground terminal of 11 R11 of resistance, and the other end is connect with the connecting pin of ten R10 of nine R9 of resistance and resistance;
The pin 21 of the delay chip U5 is connect by output interface Po with external equivalent sampling sampling gate, eight R8 of resistance
One end is connect with the pin 21 of delay chip U5, and the other end is connect with the connecting pin of ten R10 of nine R9 of resistance and resistance.
It is preferred: analog to digital conversion circuit include ADC chip U6,13 R13 of exclusion, 14 R14 of exclusion, 15 R15 of exclusion,
Nine C9 of capacitor, ten C10 of capacitor, 11 C11 of capacitor, 12 C12 of capacitor, 49 C49 of capacitor, wherein, the pin of ADC chip U6
23,24,25 are connected to external equivalent sampling sampling gate, ADC chip U6 pin 19,20,21, two
12 are respectively connected to nine C9 of capacitor, ten C10 of capacitor, 11 C11 of capacitor, 12 C12 of capacitor, later nine C9 of capacitor, capacitor ten
C10,11 C11 of capacitor, 12 C12 of capacitor ground connection;ADC chip U6 pin 15 is connected to 49 one end C49 of capacitor and electricity
Source, and the other end of 49 C49 of capacitor is grounded;ADC chip U6 pin two, three, four, five is connected to the one of 13 R13 of exclusion
End, pin six, seven, eight, nine are connected to one end of 14 R14 of exclusion, and pin ten, 11,14 is connected to 15 R15's of exclusion
One end, 13 R13 of exclusion, 14 R14 of exclusion, 15 R15 of exclusion the other end be connected to master controller;ADC chip U6 pin
One, 13 ground connection, ADC chip U6 pin 13 connect power supply.
Preferred: master controller includes XC7Z020CLG484 chip, DDR3 memory, network card chip and SD storage card,
XC7Z020CLG484 chip includes FPGA and arm processor, wherein FPGA includes GPS control module, measurement turns encoder letter
Number receiving module meets transceiver synchronization control module, global control module, AXI DataMover, AXI Interconnect two
A IP kernel, two IP kernels of AXI DataMover and AXI Interconnect for GPS control module, global control module and
It connects transceiver synchronization control module and arm processor carries out data communication;GPS control module external connection GPS positioning module, it is interior
Portion connects AXI Interconnect IP kernel by AXI4-Lite bus, in addition which connects global control module and ARM
Processor;It measures turns encoder signal receiving module external connection and measures turns encoder, inside connects global control module and connects
Transceiver synchronization control module;Connect transceiver synchronization control module external connection synchronised clock generative circuit, numerical control delay circuit
And analog to digital conversion circuit, inside connect AXI DataMover IP kernel by AXI4-Stream bus;AXI DataMover
IP kernel also passes through AXI4-Stream bus connection global control module, additionally by the high property of AXI4 bus connection arm processor
It can data/address bus;ARM processing connects external SD card, network card chip and DDR3 memory by the controller carried in piece.
The utility model compared with prior art, has the advantages that
The utility model reduces ultra-wideband ground-penetrating radar (uw-gpr) control system volume, simplifies ULTRA-WIDEBAND RADAR control system company
Wiring cable improves ultra wideband radar system reliability.
Detailed description of the invention
Fig. 1 is the application schematic diagram of the ultra-wideband ground-penetrating radar (uw-gpr) control system of the utility model embodiment;
Fig. 2 is the synchronised clock generative circuit circuit diagram of the utility model embodiment;
Fig. 3 is the GPS positioning module circuit diagram of the utility model embodiment;
Fig. 4 is the numerical control delay circuit circuit diagram of the utility model embodiment;
Fig. 5 is the ADC analog to digital conversion circuit figure of the utility model embodiment;
Fig. 6 is the Host Controller Architecture schematic diagram of the utility model embodiment;
Fig. 7 is the Control System Software schematic diagram of the utility model;
Fig. 8 is the ultra-wideband ground-penetrating radar (uw-gpr) control system schematic diagram of the utility model.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the utility model is furtherd elucidate, it should be understood that these examples are only used for
Bright the utility model rather than limitation the scope of the utility model, after having read the utility model, those skilled in the art
Member falls within the application range as defined in the appended claims to the modification of the various equivalent forms of the utility model.
As shown in Figure 1, being a kind of ultra-wideband ground-penetrating radar (uw-gpr) control system in dotted line frame, as shown in figure 8, including synchronised clock
Generative circuit, GPS positioning module, measurement turns encoder module, the numerical control delay circuit for equivalent sampling, ADC analog-to-digital conversion
Circuit and master controller;Modular circuit is the circuit designed using digital device.Wherein the synchronised clock generative circuit,
GPS positioning module, measurement turns encoder module, numerical control delay circuit, ADC analog to digital conversion circuit are connected with master controller;
The synchronised clock generative circuit is connected with ultra-broadband emitter and receiver, the numerical control delay circuit, ADC analog-to-digital conversion
Circuit is connected with external equivalent sampling sampling gate;Master controller is connected with external server.
It is as shown in Figure 2: synchronised clock generative circuit include crystal oscillator Y1,74HC00 chip U2, one R1 of resistance, five R5 of resistance,
Six R6 of resistance, 50 R50 of resistance, one C1 of capacitor, two C2 of capacitor, three C3 of capacitor, five C5 of capacitor, 50 C50 of capacitor, inductance one
L1, two L2 of inductance, wherein the pin one of the crystal oscillator Y1 is connect by one L1 of inductance with positive pole, two C2 mono- of capacitor
End is connect with the pin one of crystal oscillator Y1, and other end ground connection, described one one end C1 of capacitor is connect with positive pole, the other end and capacitor
The connection of two C2 ground terminals;Described five one end R5 of resistance is connect with the pin two of crystal oscillator Y1, and the other end connects the pin one of chip U2
With pin two;The pin three, four, five, nine, ten, 11,13 of 74HC00 chip U2 links together;The pin ten of chip U2
Four, one end connection of 5V positive pole, 50 C50 of capacitor, and the other end of 50 C50 of capacitor is grounded;The pin six of chip U2,
Six R6 of resistance, two L2 of inductance, one R1 of resistance, output interface P1 are sequentially connected, output interface P1 ground connection, output interface P1 with
Ultra-broadband emitter connection;Six R6 of resistance is connect with the connecting pin of two L2 of inductance and five one end C5 of capacitor, the capacitor five
The other end of C5 is grounded;One R1 of resistance is connect with the connecting pin of two L2 of inductance and three one end C3 of capacitor, three C3 of capacitor
The other end connect with the ground terminal of five C5 of capacitor;The pin 11 of 74HC00 chip U2 connects 50 one end C50 of capacitor, capacitor
The other end of 50 C50 is connected to master controller.
As shown in figure 3, GPS positioning module include NEO-M8N GPS chip U1, MAX2659 the low noise amplifier chip U3,
F6QA1G582H2JM SAW filter chip U4, two R2 of resistance, three R3 of resistance, four R4 of resistance, six C6 of capacitor, capacitor seven
C7, three L3 of inductance, four L4 of inductance, diode D1, LED light emitting diode D2, battery B1 and antennal interface P1;Wherein, GPS chip
The pin 11 of U1 connects the pin four of SAW filter chip U4, and one end of four R4 of resistance is with GPS chip U1's
Pin eight, nine connects, and the other end of four R4 of resistance is connect by three L3 of inductance with antennal interface P1, antennal interface P1 ground connection;
Pin 22, two R2 of resistance, diode D1,3.3V positive pole of GPS chip U1 is sequentially connected;And battery B1 anode with
The pin 22 of GPS chip U1 connects, cathode ground connection, while the pin 24 of GPS chip U1 connects the cathode of battery B1;
Pin three, three R3, LED light emitting diode D2 of resistance of GPS chip U1 is sequentially connected, and LED light emitting diode D2 cathode is grounded;
The pin 18,19,20,21 of GPS chip U1 is spi bus interface, pin one, two and of pin of GPS chip U1
Spi bus interface is connected to master controller;The pin one of SAW filter chip U4 is connected to low-noise amplifier U3
Pin four, pin three, four L4 of inductance, six C6 of capacitor, the antennal interface P1 of low-noise amplifier U3 be sequentially connected;Low noise is put
Pin five, the pin six of big device U3 connects 3.3V positive pole, and seven one end C7 of the capacitor is connect with positive pole, the other end
Ground connection.
As shown in figure 4, numerical control delay circuit includes the programmable delay chip U5 of MC100EP195B, seven R7 of resistance, resistance
Eight R8, nine R9 of resistance, ten R10 of resistance, 11 R11 of resistance, 12 R12 of resistance, eight C8 of capacitor;The pin one of delay chip U5,
Two, three, four, five, 23,26,27,29,30,31,32 it is connected to master controller;Delay
The pin 20,21 of chip U5 is difference output mouth, and according to MC100EP195B databook, the two pins are both needed to pass through
50 Ω resistance are connected on the level voltage of 2V lower than supply voltage VCC, VCC 3.3V, use resistance nine R9, ten R10 of resistance, electricity
Hinder 11 R11,12 R12 potential-divider network of resistance obtains 1.3V voltage, delay chip is connected to by seven R7 of resistance, eight R8 of resistance
U5 pin 20,21.Delay chip U5 pin 21, which is connected on output interface Po, simultaneously connects external equivalent sampling
Sampling gate.Wherein, the pin 20 of delay chip U5, seven R7 of resistance, ten R10 of resistance, 11 R11 of resistance, ground connection mouth successively connect
It connects;Described 12 one end R12 of resistance is connect with ten R10 of resistance, and the other end is connect with the ground terminal of 11 R11 of resistance;The electricity
Hinder nine R9 mono- termination positive pole, another ten R10 of terminating resistor deviate from 11 R11 of resistance one end, the one of eight C8 of capacitor
End is connect with the ground terminal of 11 R11 of resistance, and the other end is connect with the connecting pin of ten R10 of nine R9 of resistance and resistance;The delay
The pin 21 of chip U5 by output interface Po with outside equivalent sampling sampling gate connect, described eight one end R8 of resistance with prolong
When chip U5 pin 21 connect, the other end is connect with the connecting pin of ten R10 of nine R9 of resistance and resistance.
As shown in figure 5, ADC analog to digital conversion circuit includes the ADC chip U6 of model ADS822,13 R13 of exclusion, exclusion
14 R14,15 R15 of exclusion, nine C9 of capacitor, ten C10 of capacitor, 11 C11 of capacitor, 12 C12 of capacitor, 49 C49 of capacitor,
Wherein, the pin 23,24,25 of ADC chip U6 is connected to external equivalent sampling sampling gate, and ADC chip U6 draws
Foot 19,20,21,22 is respectively connected to nine C9 of capacitor, ten C10 of capacitor, 11 C11 of capacitor, capacitor 12
C12, nine C9 of capacitor, ten C10 of capacitor, 11 C11 of capacitor, 12 C12 of capacitor are grounded later;ADC chip U6 pin 15 connects
To 49 one end C49 of capacitor and 5V power supply, and the other end of 49 C49 of capacitor is grounded;ADC chip U6 pin two, three,
Four, five one end for being connected to 13 R13 of exclusion, pin six, seven, eight, nine are connected to one end of 14 R14 of exclusion, pin ten, ten
One, 14 one end for being connected to 15 R15 of exclusion, 13 R13 of exclusion, 14 R14 of exclusion, 15 R15 of exclusion the other end connect
It is connected to master controller;ADC chip U6 pin one, 13 is grounded, and ADC chip U6 pin 13 connects power supply.
As shown in fig. 6, master controller includes XC7Z020CLG484 chip, 1GB DDR3 memory, 88E1518 network card chip
With SD storage card, XC7Z020CLG484 chip includes FPGA and arm processor, wherein FPGA includes GPS control module, measurement
Turns encoder signal receiving module meets transceiver synchronization control module, global control module, AXI DataMover, AXI
Two IP kernels of Interconnect, by calling two IP kernels of AXI DataMover and AXI Interconnect to control for GPS
It molding block, global control module and connects transceiver synchronization control module and arm processor and carries out data communication;GPS control module
External connection GPS positioning module, inside connect AXI Interconnect IP kernel by AXI4-Lite bus, and the IP kernel is in addition
Connect global control module and arm processor;It measures turns encoder signal receiving module external connection and measures turns encoder, it is internal
It connects global control module and connects transceiver synchronization control module;It is raw to connect transceiver synchronization control module external connection synchronised clock
At circuit, numerical control delay circuit and analog to digital conversion circuit, inside connects AXI DataMover by AXI4-Stream bus
IP kernel;AXI DataMover IP kernel also passes through AXI4-Stream bus connection global control module, additionally by AXI4 bus
Connect the high-performance data bus of arm processor;ARM processing connects external SD card, network interface card core by the controller carried in piece
Piece and DDR3 memory.
As shown in fig. 7, Control System Software includes (SuSE) Linux OS, radar hardware drive program, radar control journey
Sequence.(SuSE) Linux OS is stored in SD card, and arm processor is carried to the operating system in SD card in DDR3 memory and transports
Row.Radar control program operates on (SuSE) Linux OS, by calling radar hardware drive program to ultra-wideband ground-penetrating radar (uw-gpr)
Control system hardware circuit is controlled and is obtained radar data, while the net that radar control program is included by calling Linux
The radar data obtained by hardware is sent to server by card driving.
The above is only the preferred embodiment of the utility model, it should be pointed out that: for the common skill of the art
For art personnel, without departing from the principle of this utility model, several improvements and modifications can also be made, these improve and
Retouching also should be regarded as the protection scope of the utility model.
Claims (6)
1. a kind of ultra-wideband ground-penetrating radar (uw-gpr) control system, it is characterised in that: including synchronised clock generative circuit, GPS positioning module,
Measure turns encoder module, numerical control delay circuit, analog to digital conversion circuit and master controller for equivalent sampling;It is wherein described
Synchronised clock generative circuit, GPS positioning module, measurement turns encoder module, numerical control delay circuit, analog to digital conversion circuit with master
Controller is connected;The synchronised clock generative circuit is connected with ultra-broadband emitter and receiver, the numerical control delay electricity
Road, analog to digital conversion circuit are connected with external equivalent sampling sampling gate;Master controller is connected with external server.
2. ultra-wideband ground-penetrating radar (uw-gpr) control system according to claim 1, it is characterised in that: the synchronised clock generative circuit
Including crystal oscillator Y1, chip U2, one R1 of resistance, five R5 of resistance, six R6 of resistance, 50 R50 of resistance, one C1 of capacitor, two C2 of capacitor, electricity
Hold three C3, five C5 of capacitor, 50 C50 of capacitor, one L1 of inductance, two L2 of inductance, wherein the pin one of the crystal oscillator Y1 passes through inductance
One L1 is connect with positive pole, and described two one end C2 of capacitor is connect with the pin one of crystal oscillator Y1, other end ground connection, the capacitor one
The one end C1 is connect with positive pole, and the other end is connect with two C2 ground terminal of capacitor;Draw with crystal oscillator Y1's described five one end R5 of resistance
Foot two connects, and the other end connects the pin one and pin two of chip U2;The pin three, four, five, nine, ten, 11, ten of chip U2
Three link together;One end connection of the pin 14, positive pole, 50 C50 of capacitor of chip U2, and 50 C50 of capacitor
Other end ground connection;Pin six, six R6 of resistance, two L2 of inductance, one R1 of resistance, the output interface P1 of chip U2 is sequentially connected, described
Output interface P1 ground connection, output interface P1 are connect with ultra-broadband emitter;The connecting pin of six R6 of resistance and two L2 of inductance and
The connection of five one end C5 of capacitor, the other end ground connection of five C5 of capacitor;The connecting pin of one R1 of resistance and two L2 of inductance and electricity
Hold the connection of three one end C3, the other end of three C3 of capacitor is connect with the ground terminal of five C5 of capacitor;The pin 11 of chip U2 connects
50 one end C50 of capacitor is connect, the other end of 50 C50 of capacitor is connected to master controller.
3. ultra-wideband ground-penetrating radar (uw-gpr) control system according to claim 1, it is characterised in that: the GPS positioning module includes
GPS chip U1, the low noise amplifier chip U3, SAW filter chip U4, two R2 of resistance, three R3 of resistance, four R4 of resistance,
Six C6 of capacitor, seven C7 of capacitor, three L3 of inductance, four L4 of inductance, diode D1, LED light emitting diode D2, battery B1 and antennal interface
P1;Wherein, the pin four of the connection of the pin 11 SAW filter chip U4 of GPS chip U1, the one of four R4 of resistance
End is connect with the pin eight, nine of GPS chip U1, and the other end of four R4 of resistance is connect by three L3 of inductance with antennal interface P1,
Antennal interface P1 ground connection;Pin 22, two R2 of resistance, diode D1, the positive pole of GPS chip U1 is sequentially connected;And it is electric
The anode of pond B1 is connect with the pin 22 of GPS chip U1, cathode ground connection, while the pin 24 of GPS chip U1 connects electricity
The cathode of pond B1;Pin three, three R3, LED light emitting diode D2 of resistance of GPS chip U1 is sequentially connected, and LED light emitting diode
D2 cathode ground connection;The pin 18,19,20,21 of GPS chip U1 is spi bus interface, the pin of GPS chip U1
One, pin two and spi bus interface are connected to master controller;The pin one of SAW filter chip U4 is connected to low noise
The pin four of acoustic amplifier U3, pin three, four L4 of inductance, six C6 of capacitor, the antennal interface P1 of low-noise amplifier U3 successively connect
It connects;Pin five, the pin six of low-noise amplifier U3 connects positive pole, and seven one end C7 of the capacitor and positive pole connect
It connects, other end ground connection.
4. ultra-wideband ground-penetrating radar (uw-gpr) control system according to claim 1, it is characterised in that: numerical control delay circuit includes delay
Chip U5, seven R7 of resistance, eight R8 of resistance, nine R9 of resistance, ten R10 of resistance, 11 R11 of resistance, 12 R12 of resistance, eight C8 of capacitor;
The pin one, two, three, four, five, 23,26,27,29,30,31,32 of delay chip U5
It is connected to master controller;The pin 20,21 of delay chip U5 is difference output mouth, wherein the pin of delay chip U5
20, seven R7 of resistance, ten R10 of resistance, 11 R11 of resistance, ground connection mouth are sequentially connected;Described 12 one end R12 of resistance and resistance
Ten R10 connections, the other end are connect with the ground terminal of 11 R11 of resistance;Nine R9 mono- of resistance terminates positive pole, another termination
Ten R10 of resistance deviates from one end of 11 R11 of resistance, and one end of eight C8 of capacitor is connect with the ground terminal of 11 R11 of resistance, separately
One end is connect with the connecting pin of ten R10 of nine R9 of resistance and resistance;The pin 21 of the delay chip U5 passes through output interface
Po is connect with external equivalent sampling sampling gate, and described eight one end R8 of resistance is connect with the pin 21 of delay chip U5, another
End is connect with the connecting pin of ten R10 of nine R9 of resistance and resistance.
5. ultra-wideband ground-penetrating radar (uw-gpr) control system according to claim 1, it is characterised in that: analog to digital conversion circuit includes ADC
Chip U6,13 R13 of exclusion, 14 R14 of exclusion, 15 R15 of exclusion, nine C9 of capacitor, ten C10 of capacitor, 11 C11 of capacitor, electricity
Hold 12 C12,49 C49 of capacitor, wherein, the pin 23,24,25 of ADC chip U6 is connected to outside etc.
Effect sampling sampling gate, ADC chip U6 pin 19,20,21,22 are respectively connected to nine C9 of capacitor, capacitor ten
C10,11 C11 of capacitor, 12 C12 of capacitor, nine C9 of capacitor, ten C10 of capacitor, 11 C11 of capacitor, 12 C12 of capacitor connect later
Ground;ADC chip U6 pin 15 is connected to 49 one end C49 of capacitor and power supply, and another termination of 49 C49 of capacitor
Ground;ADC chip U6 pin two, three, four, five is connected to one end of 13 R13 of exclusion, and pin six, seven, eight, nine is connected to exclusion
One end of 14 R14, pin ten, 11,14 are connected to one end of 15 R15 of exclusion, 13 R13 of exclusion, exclusion 14
R14,15 R15 of exclusion the other end be connected to master controller;ADC chip U6 pin one, 13 is grounded, ADC chip U6 pin
13 connect power supply.
6. ultra-wideband ground-penetrating radar (uw-gpr) control system according to claim 1, it is characterised in that: master controller includes
XC7Z020CLG484 chip, DDR3 memory, network card chip and SD storage card, XC7Z020CLG484 chip include FPGA and ARM
Processor, wherein FPGA includes GPS control module, measurement turns encoder signal receiving module, connects transceiver synchronously control mould
Two block, global control module, AXI DataMover, AXI Interconnect IP kernels, AXI DataMover and AXI
Two IP kernels of Interconnect are for GPS control module, global control module and connect at transceiver synchronization control module and ARM
It manages device and carries out data communication;GPS control module external connection GPS positioning module, inside connect AXI by AXI4-Lite bus
In addition Interconnect IP kernel, the IP kernel connect global control module and arm processor;Turns encoder signal is measured to receive
Module-external connection measurement turns encoder, inside connects global control module and connects transceiver synchronization control module;Connect transceiver
Synchronization control module external connection synchronised clock generative circuit, numerical control delay circuit and analog to digital conversion circuit, inside pass through
AXI4-Stream bus connects AXI DataMover IP kernel;AXI DataMover IP kernel also passes through AXI4-Stream bus
Global control module is connected, additionally by the high-performance data bus of AXI4 bus connection arm processor;ARM processing passes through piece
Interior included controller connects external SD card, network card chip and DDR3 memory.
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