CN208270713U - The resistance value measurement circuit device of semiconductor memory - Google Patents
The resistance value measurement circuit device of semiconductor memory Download PDFInfo
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- CN208270713U CN208270713U CN201820946073.3U CN201820946073U CN208270713U CN 208270713 U CN208270713 U CN 208270713U CN 201820946073 U CN201820946073 U CN 201820946073U CN 208270713 U CN208270713 U CN 208270713U
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Abstract
The utility model provides a kind of resistance value measurement circuit device of semiconductor memory, and first including being connected between first voltage interface and the first reading interface is calibrated unit, and first is calibrated between unit and first voltage interface and forms the first tie point；The first protection location being connected between second voltage interface and the first reading interface；And first be connected between the first tie point and the second reading interface measures switching transistor；Wherein, first voltage interface and second voltage interface are calibrated unit and the first protection location for providing voltage difference to pass the current through first；In the case where the first measurement switching transistor is in the conductive state, the electric current of unit is calibrated by the voltage and first that measure the first reading interface and the second reading interface, to obtain the first resistance value for being calibrated unit, so as to avoid contact with the influence of resistance, the resistance value of the internal resistor of the data-interface of accurate measurement semiconductor memory.
Description
Technical field
The utility model relates to semiconductor integrated circuit technology field more particularly to a kind of resistance values of semiconductor memory
Measurement circuit device.
Background technique
Memory (Memory) is for protecting stored memory device in modern information technologies, as dynamic randon access is deposited
Reservoir (Dynamic Random Access Memory, abbreviation DRAM).It can be via a resistance in the reading-port design of DRAM
Reading-port current potential is high or low and its magnitude of current of required consumption controlling for device, therefore the resistance value of resistor is needed in a fixation
Specification in, but because manufacture during its resistance value that will cause the resistor manufactured be it is inhomogenous, therefore need by
The measurement of test machine corrects for it.
It is as shown in Figure 1 the measurement circuit 100 of the resistance value of the reading-port of the DRAM of the prior art, including first is calibrated
Unit 130 and second is calibrated unit 150 and three interfaces being packaged in outside DRAM: first voltage interface 111, second
Voltage interface 112 and reading-port 121.
When measurement first is calibrated the resistance value of unit 130, apply operating voltage in first voltage interface 111, first
Switching transistor T1 ' conducting, second switch transistor T2 ' shutdown, r130=(V111-V121)/I130, wherein r130It is first by school
The resistance value summation of quasi- unit 130, contact resistance R5 ' and R7, V111It is the voltage value of first voltage interface 111, that is, work electricity
Pressure, V121It is the voltage value of reading-port 121, I130It is the electric current for being calibrated unit 130 by first.That is, carrying out self-test
The contact resistance R5 ' and R7 of the interface card of board will affect measurement.Similarly, the electricity of unit 150 is calibrated in measurement second
When resistance value, contact resistance R7 and R6 ' will affect measurement.
Therefore, in the prior art, because the contact resistance of the interface card of tester table and the interface of semiconductor memory is by shadow
The measurement of the internal resistance value of reading-port is rung, and then influences resistance value calibration result.
Utility model content
The utility model embodiment provides a kind of resistance value measurement circuit device of semiconductor memory, to solve or alleviate
One or more technical problems in the prior art.
Utility model embodiment provides a kind of resistance value measurement circuit device of semiconductor memory, comprising:
First is calibrated unit, is connected to first voltage interface and first and reads between interface, wherein described first by school
The first tie point is formed between quasi- unit and the first voltage interface；
First protection location is connected to second voltage interface and described first and reads between interface；And
First measures switching transistor, is connected to first tie point and second and reads between interface；
Wherein, the first voltage interface and the second voltage interface are for providing voltage difference, to pass the current through
It states first and is calibrated unit and first protection location；In the case where the first measurement switching transistor is in the conductive state, lead to
Cross the voltage for measuring the first reading interface and the second reading interface and described first be calibrated unit electric current, with
Obtain the described first resistance value for being calibrated unit.
Preferably, it described first is calibrated unit and includes:
First calibration switch transistor, the source electrode of the first calibration switch transistor are connected to first tie point；
And
First is calibrated resistance, be connected to the first calibration switch transistor drain electrode and it is described first read interface it
Between；
Wherein, the first calibration switch transistor turns pass the current through described first and are calibrated resistance.
Preferably, first protection location includes:
First protective switch transistor, the drain electrode of the first protective switch transistor are connected to first reading and connect
Mouthful；And
First protective resistance, be connected to the first protective switch transistor source electrode and the second voltage interface it
Between；
Wherein, the first protective switch transistor turns pass the current through first protective resistance.
In some embodiments, resistance value measurement circuit device further include:
Second is calibrated unit, is connected to the second voltage interface and described first and reads between interface, wherein is described
Second is calibrated between unit and the second voltage interface and forms the second tie point；And
Second protection location is connected to the first voltage interface and described first and reads between interface；
Second measures switching transistor, is connected to second tie point and third is read between interface；
Wherein, the voltage difference passes the current through second protection location and described second and is calibrated unit；Described
Under second measurement switching transistor is in the conductive state, the electricity for being calibrated unit and the first protection location by described first is disconnected
Stream is calibrated the electricity of unit by the voltage and described second that measure the first reading interface and third reading interface
Stream, to obtain the described second resistance value for being calibrated unit.
Preferably, it described second is calibrated unit and includes:
Second calibration switch transistor, the source electrode of the second calibration switch transistor are connected to second tie point；
And
Second is calibrated resistance, be connected to the second calibration switch transistor drain electrode and it is described first read interface it
Between；
Wherein, the second calibration switch transistor turns pass the current through described second and are calibrated resistance.
Preferably, second protection location includes:
Second protective switch transistor, the drain electrode of the second protective switch transistor are connected to first reading and connect
Mouthful；And
Second protective resistance, be connected to the second protective switch transistor source electrode and the first voltage interface it
Between；
Wherein, the second protective switch transistor turns pass the current through second protective resistance.
Preferably, the first voltage interface and the second voltage interface, described first read interface and described the
Two reading interfaces expose to the package outside of the semiconductor memory.
Preferably, the first voltage interface, the second voltage interface, described first read interface, second reading
Interface and the third is taken to read the package outside that interface exposes to the semiconductor memory.
The utility model embodiment by adopting the above technical scheme, can avoid contact with the influence of resistance, and accurate measurement is partly led
The resistance value of the internal resistor of the data-interface of body memory.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one
Aspect, embodiment and the feature of step, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to originally practical
Novel disclosed some embodiments, and should not be taken as the limitation to the scope of the utility model.
Fig. 1 is the resistance value measurement circuit device figure of semiconductor memory in the prior art.
Fig. 2 is the resistance value measurement circuit device figure of the semiconductor memory of embodiment one.
Fig. 3 is the circuit diagram of the resistance value method for measurement of the semiconductor memory of embodiment one.
Fig. 4 is the resistance value measurement circuit device figure of the semiconductor memory of embodiment two.
Fig. 5 is the circuit diagram of the resistance value method for measurement of the semiconductor memory of embodiment two.
Fig. 6 is the circuit diagram of the resistance value method for measurement of the semiconductor memory of embodiment three.
Description of symbols:
The prior art:
100: resistance value measurement circuit device
111: first voltage interface 121: reading-port 112: second voltage interface
Be calibrated unit 150: the second at 130: the first is calibrated unit
T1 ', T2 ': switching transistor R5 ', R6 ', R7: contact resistance.
The utility model embodiment:
200: resistance value measurement circuit device
211: first voltage interface 212: second voltage interface 221: the first reads interface
222: the second reading interfaces 230: the first are calibrated 240: the first protection location of unit
T1: the first calibration switch transistor the T4: the first protective switch transistor
T5: the first measurement switching transistor R1: the first is calibrated resistance
R4: the first the A1: the first tie point of protective resistance
G1, G4, G5: grid S1, S4, S5: source electrode
D1, D4, D5: drain electrode R51, R52: contact resistance
VDD: operating voltage VSS: ground voltage
300: resistance value measurement circuit device
323: third reads interface 350: the second and is calibrated 360: the second protection location of unit
T2: the second calibration switch transistor the T3: the second protective switch transistor
T6: the second measurement switching transistor R2: the second is calibrated resistance
R3: the second the A2: the second tie point of protective resistance
R61, R62: contact resistance R71, R72: contact resistance
G2, G3, G6: grid S2, S3, S6: source electrode.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present utility model, it can be modified by various different modes described real
Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it should be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside",
The orientation or positional relationship of the instructions such as " clockwise ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " is based on the figure
Orientation or positional relationship is merely for convenience of describing the present invention and simplifying the description, rather than the dress of indication or suggestion meaning
It sets or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to the utility model
Limitation.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.The meaning of " plurality " is two or two in the description of the present invention,
More than, unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " Gu
It is fixed " etc. terms shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be
Mechanical connection, is also possible to be electrically connected, can also be communication；It can be directly connected, the indirect phase of intermediary can also be passed through
Even, the connection inside two elements or the interaction relationship of two elements be can be.For those of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features directly contact, and also may include that the first and second features are not direct contacts but lead to
Cross the other characterisation contact between them.Moreover, fisrt feature includes above the second feature " above ", " above " and " above "
One feature is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.First is special
Sign includes fisrt feature right above second feature and oblique upper under the second feature " below ", " below " and " below ", or only
Indicate that first feature horizontal height is less than second feature.
Following disclosure provides many different embodiments or example is used to realize the different structure of the utility model.
In order to simplify the disclosure of the utility model, hereinafter the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.
The reading speed of the reading data mouth of semiconductor memory will be continuously improved, and the resistance value of internal resistance just needs
More and more precisely.For example, common semiconductor memory DRAM has multiple reading interfaces (DQ), need with tester table amount
The resistance value of its internal resistance is surveyed, but contacts electricity because existing between the interface card and the interface of semiconductor memory of tester table
Resistance, will affect the measurement of resistance value.The utility model is intended to provide a kind of resistance value of the reading-port of semiconductor memory
Measurement circuit device, to reduce or avoid contact with influence of the resistance to measurement.
Embodiment one
As shown in Fig. 2, the resistance value measurement circuit device 200 of the present embodiment is calibrated unit 230, first including first
Protection location 240 and first measures switching transistor T5, by measuring the first resistance value for being calibrated unit 230, and then to the
One is calibrated the calibration that unit 230 carries out resistance value.
First, which is calibrated unit 230, is connected to first voltage interface 211 and first and reads between interface 221, also, the
One, which is calibrated the place being connected between unit 230 and first voltage interface 211, forms the first tie point A1；First measures switch
Transistor T5 is connected to the first tie point A1 and second and reads between interface 222；First protection location 240 is connected to the second electricity
Mouth 212 and first is crimped to read between interface 221.
Preferably, first switching transistor T5 is measured as N-type metal-oxide semiconductor (MOS) (Negative channel
Metal Oxide Semiconductor, abbreviation NMOS) transistor, it is further preferred that first measures switching transistor T5's
Source S 5 is connected to the first tie point A1, and drain D 5 is connected to the second reading interface 222, and grid G 5 is in control signal (figure
In be not shown) control under on or off.When first measures switching transistor T5 conducting, it is applied to first voltage interface
Voltage on 211 will feed back to the second reading interface 222.
In a various embodiments, the first measurement switching transistor T5 may be P type metal oxide semiconductor
(Positive channel Metal Oxide Semiconductor, abbreviation PMOS) transistor.
In a various embodiments, the source S 5 of the first measurement switching transistor T5, which can connect, reads interface in second
222, drain D 5 can connect in the first tie point A1, as long as can pass through when first measures switching transistor T5 conducting
Measure the voltage at the first tie point A1 of voltage acquisition of the second reading interface 222.
When being provided with voltage difference between first voltage interface 211 and second voltage interface 212, electric current passes through the first quilt
Calibration unit 230 and the first protection location 240, by measure first read interface 221 and second read interface 222 voltage with
And pass through the first electric current for being calibrated unit 230, the first resistance value for being calibrated unit 230 can be obtained.
Preferably, first voltage interface 211, second voltage interface 212, first read interface 221 and second and read interface
222 expose to the package outside of semiconductor memory, can be used for connecting external equipment, such as tester table.
Preferably, first be calibrated unit 230 include the first calibration switch transistor T1 and first be calibrated resistance R1,
In, first, which is calibrated resistance R1, is connected to the first reading interface 221；First calibration switch transistor T1 can be NMOS crystal
Pipe, or PMOS transistor, in the present embodiment, the first calibration switch transistor T1 is PMOS transistor, and further excellent
Selection of land, the source S 1 of the first calibration switch transistor T1 are connected to the first tie point A1, and drain D 1 is connected to first and is calibrated
Resistance R1, grid G 1 are connected to control signal (in figure for show), with control the first calibration switch transistor T1 conducting or
Shutdown.
When the first calibration switch transistor T1 conducting, between first voltage interface 211 and second voltage interface 212
Voltage difference will pass the current through first and be calibrated resistance R1, and measuring the resistance value that first is calibrated unit 230 is to measure first
It is calibrated the resistance value of resistance R1.When the first calibration switch transistor T1 shutdown, first can be made to be calibrated resistance R1 disconnection
Connection disconnects the electric current for being calibrated unit 230 by first.
Preferably, the first protection location 240 includes the first protective switch transistor T4 and the first protective resistance R4, wherein
First protective resistance R4 is connected to second voltage interface 212；First protective switch transistor T4 can be NMOS transistor,
It can be PMOS transistor, in the present embodiment, the first protective switch transistor T4 is NMOS transistor, and it is further preferred that
The source S 4 of first protective switch transistor T4 is connected to the first protective resistance R4, and drain D 4 is connected to the first reading interface
221, grid G 4 is connected to control signal (showing in figure), to control conducting or the pass of the first protective switch transistor T4
It is disconnected.
When the first protective switch transistor T4 conducting, between first voltage interface 211 and second voltage interface 212
Voltage difference will pass the current through the first protective resistance R4, read interface 221 with protection first, and make first voltage interface 211, the
One, which is calibrated unit 230, the first protection location 240 and second voltage interface 212, forms current path.When the first protective switch
When transistor T4 is turned off, the first protective resistance R4 can be made to disconnect, that is, disconnect the electric current for passing through the first protection location 240.
The present embodiment also provides a kind of semiconductor memory, including above-described resistance value measurement circuit device 200,
Preferably, the semiconductor memory of the present embodiment can be DRAM, first read interface 221 and second read interface 222 can be with
For the DQ mouth of DRAM, resistance value measurement circuit device 200 can be used to measure the resistance value of DQ mouthfuls of internal resistance, and can keep away
Influence of the contact-free resistance to measurement.
The present embodiment also provides a kind of resistance value method for measurement of semiconductor memory, can be based on above-described resistance
It is worth measurement circuit device 200, is described below with reference to Fig. 3.
It provides voltage to be worse than between first voltage interface 211 and second voltage interface 212, for example, applying operating voltage VDD
In first voltage interface 211, applies ground voltage VSS in second voltage interface 212, be calibrated unit to pass the current through first
230 and first protection location 240.Preferably, the first calibration switch transistor T1 and the first protective switch transistor T4 conducting, with
It passes the current through first and is calibrated resistance R1 and the first protective resistance R4.
Wherein, operating voltage VDD and ground voltage VSS may come from the interface card of tester table.
The control signal in grid G 5 by being applied to the first measurement switching transistor T5 makes the first measurement switch crystal
Pipe T5 conducting measures the first voltage for reading interface 221, for example, V11；The second voltage for reading interface 222 is measured, for example,
V1.The voltage that can use external equipment measures tolerance and surveys the first voltage for reading interface 221 and the second reading interface 222, such as
DQ voltage measurer (force 1nA measure DQ voltage, ISVM).
The electric current for being calibrated unit 230 by first is measured, for example, I1 can read interface 221 by measuring first
Electric current to obtain the first electric current for being calibrated unit 230.
Then, the first resistance value r1=(V11-V2)/I1 for being calibrated unit 230.For example, VSS=1.2 volt (V), V11
=0.55V, V2=1.15V, I1=5 milliamperes (mA), then, r1=30 ohm.
There are contact resistance R51, the interface cards of tester table between the interface card and first voltage interface 211 of tester table
There are contact resistance R52 between second voltage interface 212, the resistance value of contact resistance R51 and R52 are uncertain, when contact not
When good, resistance value may be up to hundreds of ohms.And the resistance value measurement circuit device 200 of the present embodiment and resistance value measurement side
Method, the first measurement for being calibrated the resistance value of unit 230 will not use first voltage interface 211 and second voltage interface
212 voltage value, i.e., first be calibrated unit 230 resistance value it is unrelated with contact resistance R51 and R52, thus can accurately obtain
Measurement is obtained, for example, can be with the resistance value of the internal resistance of the DQ mouth of accurate measurement DRAM.
Embodiment two
As shown in figure 4, the present embodiment provides a kind of measurement circuits 300 of semiconductor memory, the difference with embodiment one
It is, increases and second be calibrated unit 350, the second protection location 360 and second measures switching transistor T6, by measures the
Two are calibrated the resistance value of unit 350, and then are calibrated the calibration that unit 360 carries out resistance value to second.
Second, which is calibrated unit 350, is connected to second voltage interface 212 and first and reads between interface 221, also, the
Two, which are calibrated the place being connected between unit 350 and second voltage interface 212, forms the second tie point A2；Second measures switch
Transistor T6 is connected to the second tie point A2 and third is read between interface 323；Second protection location 360 is connected to the first electricity
Mouth 211 and first is crimped to read between interface 221.
Preferably, second switching transistor T6 is measured as PMOS transistor, it is further preferred that second measures switch crystal
The source S 6 of pipe T6 is connected to the second tie point A2, and drain D 6 is connected to third and reads interface 323, and grid G 6 is believed in control
On or off under the control of number (not shown).When second measures switching transistor T6 conducting, it is applied to second voltage
Voltage on interface 212 will feed back to third and read interface 323.
When measurement first is calibrated unit 230, switching transistor T6 can be measured on or off second；When measuring the
Two when being calibrated unit 350, can measure switching transistor T5 on or off first.
In a various embodiments, the second measurement switching transistor T6 may be NMOS transistor.
In a various embodiments, the source S 6 of the second measurement switching transistor T6, which can connect, reads interface in third
323, drain D 6 can connect in the second tie point A2, as long as can pass through when second measures switching transistor T6 conducting
Measure the voltage at the second tie point A2 of voltage acquisition of third reading interface 323.
When being provided with voltage difference between first voltage interface 211 and second voltage interface 212, electric current passes through the second quilt
Calibration unit 350 and the second protection location 360 disconnect the electricity for being calibrated unit 230 and the first protection location 240 by first
Stream reads the voltage of interface 323 and passes through second and be calibrated unit 350 by measuring the first reading interface 221 and third
Electric current can obtain the second resistance value for being calibrated unit 350.
Preferably, third reads the package outside that interface 323 exposes to semiconductor memory, can be used for connecting outside and sets
It is standby, such as tester table.
Preferably, second be calibrated unit 350 include the second calibration switch transistor T2 and second be calibrated resistance R2,
In, second, which is calibrated resistance R2, is connected to the first reading interface 221；Second calibration switch transistor T2 can be NMOS crystal
Pipe, or PMOS transistor, in the present embodiment, the second calibration switch transistor T2 is NMOS transistor, and further excellent
Selection of land, the source S 2 of the second calibration switch transistor T2 are connected to the second tie point A2, and drain D 2 is connected to second and is calibrated
Resistance R2, grid G 2 are connected to control signal (in figure for show), with control the second calibration switch transistor T2 conducting or
Shutdown.
When the second calibration switch transistor T2 conducting, between first voltage interface 211 and second voltage interface 212
Voltage difference will pass the current through second and be calibrated resistance R2, and measuring the resistance value that second is calibrated unit 350 is to measure second
It is calibrated the resistance value of resistance R2.When the second calibration switch transistor T2 shutdown, second can be made to be calibrated resistance R2 disconnection
Connection disconnects the electric current for being calibrated unit 350 by second.
Preferably, the second protection location 360 includes the second protective switch transistor T3 and the second protective resistance R3, wherein
Second protective resistance R3 is connected to first voltage interface 211；Second protective switch transistor T3 can be NMOS transistor,
It can be PMOS transistor, in the present embodiment, the second protective switch transistor T3 is NMOS transistor, and it is further preferred that
The source S 3 of second protective switch transistor T3 is connected to the second protective resistance R3, and drain D 3 is connected to the first reading interface
221, grid G 3 is connected to control signal (showing in figure), to control conducting or the pass of the second protective switch transistor T3
It is disconnected.
When the second protective switch transistor T3 conducting, between first voltage interface 211 and second voltage interface 212
Voltage difference will pass the current through the second protective resistance R3, read interface 221 with protection first, and make first voltage interface 211, the
Two protection locations 360, second are calibrated unit 350 and the formation current path of second voltage interface 212.When the second protective switch
When transistor T3 is turned off, the second protective resistance R3 can be made to disconnect, that is, disconnect the electric current for passing through the second protection location 360.
The present embodiment also provides a kind of semiconductor memory, including above-described resistance value measurement circuit device 300,
Preferably, the semiconductor memory of the present embodiment can be DRAM, and third reads the DQ mouth that interface 323 can be DRAM, resistance
Value measurement circuit device 300 can be used to measure the resistance value of DQ mouthfuls of internal resistance, and can avoid contact with resistance to measurement
As a result influence.
The present embodiment also provides a kind of resistance value method for measurement of semiconductor memory, can be based on above-described resistance
It is worth measurement circuit device 300, wherein the first method for measurement for being calibrated the resistance value of unit 230 is found in embodiment one, needs
Illustrate, when measurement first is calibrated the resistance value of unit 230, should disconnect and be calibrated unit 350 and second by second
The electric current of protection location 360, but the second measurement switching transistor T6 can be tended to remain on.
The method for measurement for the resistance value that second is calibrated unit 350, the method for the present embodiment are described below with reference to Fig. 5
Including disconnecting the electric current for being calibrated unit 230 and the first protection location 240 by first, therefore, Fig. 5 is shown in shutdown first
Calibration switch transistor T1, the first protective switch transistor T4 and first measure switching transistor T5 when equivalent circuit diagram.
It should be noted that first measures switching transistor T5 when measurement second is calibrated the resistance value of unit 350
It can tend to remain on.
The resistance value method for measurement of the present embodiment further include: voltage is provided and is worse than first voltage interface 211 and second voltage
Between interface 212, for example, applying operating voltage VDD in first voltage interface 211, applies ground voltage VSS and connect in second voltage
Mouth 212, is calibrated unit 350 and the second protection location 360 to pass the current through second.Preferably, the second calibration switch crystal
Pipe T2 and the second protective switch transistor T3 conducting, is calibrated resistance R2 and the second protective resistance R3 to pass the current through second.
Wherein, operating voltage VDD and ground voltage VSS may come from the interface card of tester table.
The control signal in grid G 6 by being applied to the second measurement switching transistor T6 makes the second measurement switch crystal
Pipe T6 conducting measures the first voltage for reading interface 221, for example, V12；The voltage that third reads interface 323 is measured, for example,
V3.The voltage that can use external equipment measures tolerance and surveys the first voltage for reading interface 221 and third reading interface 323, such as
DQ voltage measurer.
The electric current for being calibrated unit 350 by second is measured, for example, I2 can read interface 221 by measuring first
Electric current to obtain the second electric current for being calibrated unit 350.
Then, the second resistance value r2=(V12-V3)/I2 for being calibrated unit 350.
There are contact resistance R61, the interface cards of tester table between the interface card and first voltage interface 211 of tester table
There are contact resistance R62 between second voltage interface 212, the resistance value of contact resistance R61 and R62 are uncertain, when contact not
When good, resistance value may be up to hundreds of ohms.And the resistance value measurement circuit device 300 of the present embodiment and resistance value measurement side
Method, the second measurement for being calibrated the resistance value of unit 350 will not use first voltage interface 211 and second voltage interface
212 voltage value, i.e., second be calibrated unit 350 resistance value it is unrelated with contact resistance R61 and R62, thus can accurately obtain
Measurement is obtained, for example, can be with the resistance value of the internal resistance of the reading-port of accurate measurement semiconductor memory.
Embodiment three
The present embodiment provides a kind of resistance value method for measurement of semiconductor memory, can be based on above-described resistance value
Measurement circuit device 300.
It is worse than between first voltage interface 211 and second voltage interface 212 as shown in fig. 6, providing voltage, for example, applying
Operating voltage VDD applies ground voltage VSS in second voltage interface 212 in first voltage interface 211.
Wherein, operating voltage VDD and ground voltage VSS may come from the interface card of tester table.
Conducting first measures switching transistor T5 and conducting second measures switching transistor T6, it should be noted that first
Measuring the measurement of switching transistor T5 and second switching transistor T6 can be without constantly on, for example, being calibrated in measurement first
When unit 230, conducting first, which measures switching transistor T5 and turns off second, measures switching transistor T6；It is calibrated in measurement second
When unit 350, shutdown first, which measures switching transistor T5 and is connected second, measures switching transistor T6.
When measurement first is calibrated unit 230, the first calibration switch transistor T1 and the first protective switch crystal is connected
Pipe T4 passes the current through first and is calibrated unit 230 and the first protection location 240；Meanwhile turning off the second calibration switch transistor
T2 and the second protective switch transistor T3, to disconnect the electric current for being calibrated unit 350 and the second protective switch 360 by second；
Then, the voltage of the first reading-port 221 is measured, for example, V13 measures the voltage of the second reading-port 222, and for example, V4 is measured
The electric current for being calibrated unit 230 by first, for example, I3, then, first is calibrated the resistance value r1=(V13- of unit 230
V4)/I3。
When measurement second is calibrated unit 350, the second calibration switch transistor T2 and the second protective switch crystal is connected
Pipe T3 passes the current through second and is calibrated unit 350 and the second protective switch 360；Meanwhile turning off the first calibration switch transistor
T1 and the first protective switch transistor T4, to disconnect the electric current for being calibrated unit 230 and the first protection location 240 by first；
Then, the voltage of the first reading-port 221 is measured, for example, V14 measures the voltage of third reading-port 223, and for example, V5 is measured
The electric current for being calibrated unit 350 by second, for example, I4, then, second is calibrated the resistance value r2=(V14- of unit 350
V5)/I4。
Wherein, the measurement method of voltage and current can be found in embodiment one and embodiment two.
As shown in fig. 6, during the test, existing between the interface card and first voltage interface 211 of tester table and contacting
Resistance R71, there are contact resistance R72 between the interface card and second voltage interface 212 of tester table, contact resistance R71 and
The resistance value of R72 is uncertain, and when contacting bad, resistance value may be up to hundreds of ohms.And the resistance value of the present embodiment measures
Circuit device 300 and resistance value method for measurement, the second measurement for being calibrated the resistance value of unit 350 will not use the first electricity
The voltage value of mouth 211 and second voltage interface 212 is crimped, i.e., second is calibrated the resistance value and contact resistance R71 of unit 350
It is unrelated with R72, thus measurement can be accurately obtained, for example, can be in the reading-port of accurate measurement semiconductor memory
The resistance value of portion's resistance.
Above description is only a specific implementation of the present invention, but the protection scope of the utility model is not limited to
In this, anyone skilled in the art within the technical scope disclosed by the utility model, it is each can to readily occur in it
Kind change or replacement, these should be covered within the scope of the utility model.Therefore, the protection scope of the utility model
It should be based on the protection scope of the described claims.
Claims (8)
1. a kind of resistance value measurement circuit device of semiconductor memory characterized by comprising
First is calibrated unit, is connected to first voltage interface and first and reads between interface, wherein described first is calibrated list
It is first to form the first tie point between the first voltage interface；
First protection location is connected to second voltage interface and described first and reads between interface；And
First measures switching transistor, is connected to first tie point and second and reads between interface；
Wherein, the first voltage interface and the second voltage interface is for providing voltage difference, to pass the current through described the
One is calibrated unit and first protection location；In the case where the first measurement switching transistor is in the conductive state, throughput
The voltage of the first reading interface and the second reading interface is surveyed and electric current that described first is calibrated unit, to obtain
Described first is calibrated the resistance value of unit.
2. resistance value measurement circuit device according to claim 1, which is characterized in that described first is calibrated unit packet
It includes:
First calibration switch transistor, the source electrode of the first calibration switch transistor are connected to first tie point；And
First is calibrated resistance, and the drain electrode and described first for being connected to the first calibration switch transistor are read between interface；
Wherein, the first calibration switch transistor turns pass the current through described first and are calibrated resistance.
3. resistance value measurement circuit device according to claim 1, which is characterized in that first protection location includes:
First protective switch transistor, the drain electrode of the first protective switch transistor are connected to described first and read interface；With
And
First protective resistance is connected between the source electrode of the first protective switch transistor and the second voltage interface；
Wherein, the first protective switch transistor turns pass the current through first protective resistance.
4. resistance value measurement circuit device according to any one of claims 1 to 3, which is characterized in that further include:
Second is calibrated unit, is connected to the second voltage interface and described first and reads between interface, wherein described second
It is calibrated between unit and the second voltage interface and forms the second tie point；And
Second protection location is connected to the first voltage interface and described first and reads between interface；
Second measures switching transistor, is connected to second tie point and third is read between interface；
Wherein, the voltage difference passes the current through second protection location and described second and is calibrated unit；Described second
Under measurement switching transistor is in the conductive state, the electric current for being calibrated unit and the first protection location by described first is disconnected,
The electric current of unit is calibrated by the voltage and described second that measure the first reading interface and third reading interface,
To obtain the described second resistance value for being calibrated unit.
5. resistance value measurement circuit device according to claim 4, which is characterized in that described second is calibrated unit packet
It includes:
Second calibration switch transistor, the source electrode of the second calibration switch transistor are connected to second tie point；And
Second is calibrated resistance, and the drain electrode and described first for being connected to the second calibration switch transistor are read between interface；
Wherein, the second calibration switch transistor turns pass the current through described second and are calibrated resistance.
6. resistance value measurement circuit device according to claim 4, which is characterized in that second protection location includes:
Second protective switch transistor, the drain electrode of the second protective switch transistor are connected to described first and read interface；With
And
Second protective resistance is connected between the source electrode of the second protective switch transistor and the first voltage interface；
Wherein, the second protective switch transistor turns pass the current through second protective resistance.
7. resistance value measurement circuit device according to any one of claims 1 to 3, which is characterized in that the first voltage
Interface and the second voltage interface, the first reading interface and the second reading interface expose to the semiconductor
The package outside of memory.
8. resistance value measurement circuit device according to claim 4, which is characterized in that the first voltage interface, described
Second voltage interface, the first reading interface, the second reading interface and the third read interface and expose to institute
State the package outside of semiconductor memory.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820946073.3U CN208270713U (en) | 2018-06-19 | 2018-06-19 | The resistance value measurement circuit device of semiconductor memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820946073.3U CN208270713U (en) | 2018-06-19 | 2018-06-19 | The resistance value measurement circuit device of semiconductor memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031082A (en) * | 2018-06-19 | 2018-12-18 | 长鑫存储技术有限公司 | The resistance value measurement circuit device and method of semiconductor memory |
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2018
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031082A (en) * | 2018-06-19 | 2018-12-18 | 长鑫存储技术有限公司 | The resistance value measurement circuit device and method of semiconductor memory |
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