CN208208340U - A kind of DRAM memory based on 3D encapsulation - Google Patents

Abstract

The utility model discloses a kind of DRAM memory based on 3D encapsulation, the DRAM memory is integrated with Read-write Catrol logic, refresh control logic and storage array, and Read-write Catrol logic, refresh control logic and storage array layer stack are on DRAM memory silicon substrate；Wherein, the division of entire DRAM memory space is independent bank by doped structure wordline and bit line contact hole by storage array；Refresh control logic, for controlling the refresh operation of bank, including delay refreshing and interruption refreshing；Read-write Catrol logic, the collision signal in signal and access process for being exported according to refresh control logic, reads and writes the data in the storage array.Compared with the existing technology, the interface bandwidth of DRAM memory is improved.

Description

A kind of DRAM memory based on 3D encapsulation

Technical field

The utility model relates to IC design field more particularly to a kind of DRAM memories based on 3D encapsulation.

Background technique

With the development of the times, microelectronic technique level is constantly progressive, and the 3D encapsulation technology nowadays occurred allows will be different The logic unit of technique integrates, and passes through TSV (Through Silicon Vias) technology between each layer logic unit It is interconnected with fine copper post, TSV can provide thousands of interconnections in the longitudinal direction, support multiple-level stack, this is substantially reduced The distance of data transmission, reduces power consumption.The stacking of multilayer logic unit brings highdensity pin arrangements.Relative to common The IC of encapsulation improves the density stored in IC, shortens access delay, improve data bandwidth.With to artificial class nerve Network (ANN) research deepens continuously, and modern science and technology technology has made great progress in artificial intelligence field, and artificial class Neural network learning is also required to the support of mass storage, and ability of data processing requires also very high, above-mentioned new technology Appearance utilize 3D encapsulation technology, computing unit is integrated in the logic circuit layer of memory, computing unit can be where data Position complete to calculate, to reduce the mobile distance of data.

, as in the embedded design stored, because constantly to refresh to DRAM, and refresh using DRAM While when conflicting and being generally limited in refreshing not can be carried out normal reading and writing data with read-write operation in order to prevent, so brush New process actually also occupies the access bandwidth of memory interface.In order to which the memory of large capacity can be embedded in IC, only DRAM can be selected as memory.In the prior art in order to improve the access bandwidth of interface data, increase other auxiliary of interface Data width and raising clock frequency in logic, this will lead to resource used in entire logical design and becomes more, and interface is set It counts difficulty to increase, IC area increases, and finally also has led to the increase of IC cost.

Utility model content

A kind of DRAM memory based on 3D encapsulation, which is integrated with Read-write Catrol logic, refresh control is patrolled Volume and storage array, Read-write Catrol logic, refresh control logic and storage array layer stack are on DRAM memory silicon substrate； Wherein, the division of entire DRAM memory space is independent bank by doped structure wordline and bit line contact hole by storage array； Refresh control logic, for controlling the delay and interruption of bank refresh operation；Read-write Catrol logic, for being patrolled according to refresh control The refreshing result collected is written and read.

Further, doped structure wordline surface applies covering photoresist.

Further, the storage array has a memory space, and the minimum unit for defining data storage cell first is 192B, as a BufUnit；The memory space of 6MB is divided into 24576 minimum unit BufUnit, minimum unit BufUnit contains 3 64B；

Wherein, the memory space is split into 3 independent memory spaces, is defined as 3 data transmission packets, correspondingly, It actually include 16 Bank in each data transmission packet, specified memory space is divided into 48 Bank.

Further, the Read-write Catrol is logically divided into read operation logic and write operation logic, patrols in the refresh control It is worked alternatively under the control action collected.

Further, further include conflict avoidance logic in the Read-write Catrol logic, deposited for detecting and notifying to described The conflict between the reading or write-access and refreshing access of the Bank in array is stored up, and uses embedded cyclic redundancy check Logic debugging.

The purpose of this utility model is to provide a kind of using the above-mentioned DRAM memory based on 3D encapsulation, is not increasing as far as possible Under conditions of adding logical design complexity (resource usage amount), coordinates read-write and conflict with refreshing, avoid the interface of DRAM memory Bandwidth is occupied, improves interface data access bandwidth and data throughout based on 3D encapsulation DRAM memory.

The other of the utility model is specifically suggested in appended independence and dependent claims with preferred aspect. The feature of dependent claims can with the features of independent claims suitably according to clearly proposed in claim The different combination of those combinations is combined.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of the DRAM memory based on 3D encapsulation in the utility model embodiment；

Fig. 2 is the architecture diagram of the DRAM memory in the utility model embodiment；

Fig. 3 is the logical framework figure of the DRAM memory based on 3D encapsulation in the utility model embodiment；

Fig. 4 is the refreshing timing diagram in the utility model embodiment；

Fig. 5 is the flow chart of the access method of the DRAM memory based on 3D encapsulation in the utility model embodiment.

Specific embodiment

Specific embodiment of the present utility model is described further with reference to the accompanying drawing:

It will be wrapped below with one in the design of DDR chip based on DRAM memory block and the transmission of the data of memory interface The reservoir designs example of data access exchange explains the design scheme of the utility model, be directed to access interface bandwidth and The problem of pipeline processes.However, it is desirable to explanation, the application of the utility model is not limited to dram chip.

The utility model is implemented to disclose a kind of DRAM memory based on 3D encapsulation, as shown in figure 3, the DRAM memory It is integrated with Read-write Catrol logic, refresh control logic and storage array, Read-write Catrol logic, refresh control logic and storage array Layer stack is on DRAM memory silicon substrate；Wherein, storage array will be entire by doped structure wordline and bit line contact hole The division of DRAM memory space is independent bank；Refresh control logic, for controlling the refresh operation of bank, including delay refreshing Refresh with interrupting；Read-write Catrol logic, the collision signal in signal and access process for being exported according to refresh control logic, Read and write the data in the storage array.

As shown in Figure 1, the DRAM memory is integrated with Read-write Catrol logic 102, refresh control logic 101 and storage battle array Column 103, Read-write Catrol logic 102, refresh control logic 101 and 103 layer stack of storage array are in DRAM memory silicon substrate On 104.Specifically, entire DRAM memory uses 3D encapsulation technology, the Read-write Catrol logic 102 and refreshing of silicon substrate 104 Control logic 101 is responsible for the sequence of storage array 103, refreshing, reading and writing data and high speed interconnection task to each other, and described point Body silicon can be used in Read-write Catrol logic 102, refresh control logic 101 and the storage array 103 of layer or silicon-on-insulator is real It is existing.It is interconnected between each layer by TSV (Through Silicon Vias) technology and fine copper post.TSV can be in the longitudinal direction Thousands of interconnections is provided, supports multiple-level stack, this has substantially reduced the distance of data transmission, also improves the utilization of silicon wafer Rate reduces manufacturing cost.The stacking of multi-layer logic brings highdensity pin arrangements, improves storage density and IC benefit With rate, access delay is shortened, improves data bandwidth.

Entire DRAM memory space is divided into solely by the storage array 103 by doped structure wordline and bit line contact hole Vertical bank specifically first in 103 Surface Creation of storage array, one layer of thin oxide, is then mixed in already oxidised Miscellaneous structure wordline surface and already oxidised silicon substrate surface coat photoresist, pass through bit line contact hole when to avoid subsequent ion from adulterating It is doped, has between several doped structure wordline and already oxidised silicon substrate surface need to coat photoresist already oxidised.It connects Using developer solution removal the silicon substrate surface already oxidised between doped structure wordline to be doped photoresist, wherein The silicon base is located between the adjacent doped structure wordline for bit line contact hole.Finally by the bit line contact for having removed photoresist Hole carries out ion doping to active area in silicon base, and the division of entire DRAM memory space is independent bank.The DRAM Memory passes through above-mentioned technique in terms of data problem is lost in the electric leakage that capacitor storage information generates compared to traditional DRAM Improve the refresh cycle, to reduce power consumption.Generally one skilled in the art that if storage unit is not kept in data Refreshed in time, storage information will lose.

The utility model provides a kind of 3D of high storage density DRAM memory encapsulated in implementing, and clock frequency is set to The Pipeline series of 400MHz, DRAM are 2.Memory interface bus width is 64B, and memory has a specified storage empty Between, total capacity in other embodiments, can choose certain total capacity for 6MB(as needed).It is every in DRAM memory The width of a Bank is 64B, and depth 2048 includes 192 row addresses, and refresh interval under the conditions of 0-105 DEG C is 41.0 microseconds, that is to say, that it is required that the mistake entirely refreshed can just be completed by refreshing 192 times in 41.0 microseconds to a Bank Journey.

For convenience of description, as shown in Fig. 2, the utility model embodiment provides the storage battle array built in a kind of DRAM memory Column, the storage array have a specified memory space, and the minimum unit for defining data storage cell first is 192B, and claims it For a BufUnit.The specified memory space of 6MB is divided into 24576 minimum unit BufUnit.One data transmission packet is most It is few also to occupy a BufUnit.If this data transmission packet is greater than 192B, it will be assigned in multiple BufUnit Storage.Because a BufUnit contains 3 64B, it is possible to it is empty that entire memory space be split into 3 independent storages Between, referred to as 3 data transmission packets.Minimum unit BufUnit includes three 64B being stored respectively in different data transmission packet Memory space.It actually include (2048 ÷ 3=of 6MB ÷ 64B ÷) 16 Bank in such a data transmission packet.Entire storage Space is divided into 48 Bank.The storage array further includes a column decoder and a line decoder, for according to address The result of signal interpretation selects a certain number of BufUnit.

Continue to join shown in Fig. 2, in the present embodiment, wherein three 64B storages in the minimum unit BufUnit The storage principle in space are as follows: according to the decoding information that line decoder exports, the 0th BufUnit is located at three data transmission packets On the 0th address of 0th Bank, the 1st BufUnit is located on the 1st the 0th address Bank of three data transmission packets, successively Analogize, the 15th BufUnit is located on the 15th the 0th address Bank of third data transmission packet.Then according to column decoding The decoding information of device output, then redistributed since the 0th Bank of corresponding data transmission packet and the 1st address, further according to The decoding information of line decoder output correspondingly continues to distribute the 1st the 1st address Bank, until all 24576 BufUnit All it is assigned.

It should be noted that when refreshing the setting refresh cycle of refresh control logic described in timing less than data holding Between, it is ensured that sampled signal by the DRAM memory refresh sampling after data-signal still need maintain before level state not Become, the parameter of the retention time determines whether the data after sampling can correctly be written register.

Specifically, the Read-write Catrol is logically divided into read operation logic and write operation logic, and the Read-write Catrol logic is just Any one read operation logic or write operation logic therein is selected to enter wait state.That is, reading the last one Without other selections when the Read-write Catrol logic where data, if at this moment write operation also cannot just select again again The data are selected, that can only just take the mode of ping-pong operation that one of read operation and write operation operation is allowed to be handed in the case where refreshing timing Alternately enter wait state, and another kind is then selected corresponding data to be operated.

Increase conflict avoidance logic in the Read-write Catrol logic, by detect a flag data storage location 2 Simultaneously notice to the reading of the Bank in the storage array or write-access and refreshes the conflict between accessing to bit flag information, Increase by two pin notice detections i.e. in the Read-write Catrol logic to the reading of given Bank or write-access and refreshing Conflict between access.So that the refresh control logic under such control logic, can avoid to the greatest extent because Reading or write-access to given Bank and the conflict refreshed between access and cause the bandwidth of DRAM memory refress to account for With, loss of the read/write conflict to bandwidth, and may be implemented in the case of the DRAM using multi-stage pipeline to data storage with Machine access.

Conflict avoidance logic detection described in the utility model implementation simultaneously notifies reading or write-in to given Bank to visit Ask and refresh the conflict between access.If detecting and notifying to conflict, refresh during the visit current, reading or In the case of write-access causes conflict, reading or write-access are re-initiated by the Read-write Catrol logic, and current During reading or write-access, in the case of refreshing access causes conflict, delay, which refreshes, to be accessed.The delay for refreshing access can be with It is completed by the refresh control logic, the refresh control logic is prolonged using specific known to those skilled in the art Slow circuit is alternative, refreshes and can be a continual process now.The conflict avoidance logic can be by for than Compared with the known comparison circuit of access address, so that the DRAM memory gets rid of the Memory Controller of the prior art, thus So that circuit structure is more simpler.According to the utility model, the conflict avoidance logic embedded loops redundancy check (CRC) is patrolled Collect circuit.Due to the ever-increasing high-speed interface between the Read-write Catrol logic and the storage array, with these interfaces The error of transmission for more and more transmitting data may occur for communication.In order to detect these mistakes, in the Read-write Catrol It may include CRC (or parity bits/verification and) in data transmission between logic and the storage array.It is practical according to this Novel, the conflict avoidance logic can use the presence of this CRC, go detection identification error signal.

Optimize the data access process of DRAM on the basis of DRAM memory architecture described above.Refresh to simplify The refreshing of control logic, three data transmission packets carries out simultaneously, and mutually indepedent, 256 parts of refresh cycle average mark, can obtain It requires to refresh between primary maximum duration to three data transmission packets and is divided into (41 microsecond ÷, 2.0 nanosecond ÷ 256) 80 refreshings In the period, the refresh control logic respectively refreshes once 16 Bank in each data transmission packet within the refresh cycle.? The time of the refresh cycle is divided into three parts, in conjunction with the refreshing timing of Fig. 4 by preferred embodiment in the utility model The access method flow diagram of figure and Fig. 5:

First part is called refresh time, does and refreshes in first part, but when there is read-write operation, refreshing can be by Disconnected, the priority that the Read-write Catrol logic is arranged is higher than the refresh control logic, and the refresh control logic automatically selects Do not refreshed by the Bank that Read-write Catrol logic buffers, is preferentially written and read.In addition, the Read-write Catrol logic is simultaneously Obtain the Bank that uses needed for current read-write request and next read-write requests respectively in read-write requests list；The refresh control Logic selection is not refreshed by the Bank that current read-write request and next read-write requests use.

In the utility model, to realize that the priority of the Read-write Catrol logic is higher than the utility model of refresh control logic Purpose, as shown in the refreshing timing of Fig. 4, the processing priority of normal read-write requests is set as high in X1, and the priority of refreshing is set To be low, i.e., if the certain Bank of read-write operation, the refresh delay meter that will use in the refresh control logic within the X1 stage The time of rolling counters forward refresh operation delay, then refresh operation can only just operate those of other Bank.Because the DRAM flows Waterline length is 2, so if the uppermost request (current read-write request) of current read-write request list is interrupted when refreshing, Back to back second request (next read-write requests) inner Bank for needing to read and write is also to need to interrupt to refresh.Based on such Restrictive condition, refresh control logic can automatically select the Bank that will not be clashed according to read-write requests and refresh to do, to keep away Exempt to same Bank while carrying out the bandwidth of refreshing and read-write operation occupancy DRAM memory interface.And it can between different bank To carry out refreshing and read-write operation simultaneously, the pipeline organization that the utility model is implemented at most allows 4 Bank to refresh.

Second part is called delay refresh time, patrols in the priority of second part Read-write Catrol logic lower than refresh control Volume, the refresh control logic is forced to carry out refresh operation by judgement to the Bank not refreshed detected, described at this time Refresh delay counter counts zero；Start to be also preferentially to be written and read, but second part remaining time is complete due to second part Portion is used to complete refresh operation, no longer response read-write requests, and the Read-write Catrol logic is arranged and enters wait state.

If be written and read to same Bank always, refresh control logic is limited to the brush of these Bank Newly, therefore there need to be second part and set high for the processing priority for refreshing access, but still have by judgement discovery second part Bank is not refreshed, then must be refreshed within this period to them, at this time if receiving the Read-write Catrol There is conflict phenomenon in the read-write requests of logic, then the Read-write Catrol logic enters wait state.

Further, the Read-write Catrol logic just select any one read operation logic or write operation logic therein into Enter wait state.That is, being without other selections when reading the Read-write Catrol logic where the last one data , if at this moment write operation also cannot just reselect the data again, that just can only take the mode of ping-pong operation refreshing One of read operation and write operation operation is allowed to alternatively enter wait state under timing, and it is another then by the corresponding number of selection According to being operated.In this case, the operation of the refresh control logic need to occupy the interface of certain DRAM memory Bandwidth.

Part III is called access time, only does read-write operation in the part-time, promotes the DRAM to reach The purpose of the data access bandwidth of memory arbitrarily selects in the storage array first in the minimum unit BufUnit The one 64B memory space not used by reading logic is as initial address, and the Read-write Catrol logic is from the initial address by suitable Data are written in sequence；The initial address is transferred to the Read-write Catrol logic；Since the initial address is in order, selection The 64B storage unit for being stored with valid data not used by the Read-write Catrol logic carries out reading data.

Further, judge whether the initial address is used by the Read-write Catrol logic, do not sent out if then selecting for a post meaning The address of conflict is given birth to write data；Otherwise data are sequentially read out since the initial address, until reading all data.

In the present embodiment, a kind of more flexible storage mode is taken, it is worth mentioning at this point that, it needs to set one in advance A data are written to the particular order in memory and record, this particular order will be in company with the actually active data of mark The location information of transmission packet is sent to the read operation logic.Then it by the write operation logic, is stored from each 64B empty It is interior it is any select an idle data transmission packet as originating write address and start to write data, and the read operation logic can be with A data biography is randomly chosen according to the position for transmitting the mark actually active data transmission packet come in the storage array Defeated packet after the data in all data transmission packets comprising valid data are all read out, then presses original spy to read data The fixed access control requirement for meeting IC peripheral circuit to DRAM memory that sequentially combines.

For convenience of description, it is divided into various units when description apparatus above with function to describe respectively.Certainly, implementing this The function of each unit can be realized in the same or multiple software and or hardware when application.Pass through above embodiment Description it is found that those skilled in the art can be understood that the application can add required common hardware flat by software The mode of platform is realized.Based on this understanding, the technical solution of the application substantially in other words contributes to the prior art Part can be embodied in the form of software products, which can store in storage medium, such as ROM/RAM, magnetic disk, CD etc., including some instructions are used so that a computer equipment (can be personal computer, service Device or the network equipment etc.) execute method described in certain parts of each embodiment of the application or embodiment.

Device embodiments described above are only schematical, wherein the unit as illustrated by the separation member It may or may not be physically separated, component shown as a unit may or may not be physics list Member, it can it is in one place, or may be distributed over multiple network units.It can be selected according to the actual needs In some or all of the modules realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation Property labour in the case where, it can understand and implement.

Claims (5)

1. a kind of DRAM memory based on 3D encapsulation, which is characterized in that the DRAM memory is integrated with Read-write Catrol logic, brush New control logic and storage array, Read-write Catrol logic, refresh control logic and storage array layer stack are in DRAM memory On silicon substrate；Wherein, entire DRAM memory space is divided into solely by storage array by doped structure wordline and bit line contact hole Vertical bank；Refresh control logic, for controlling the delay and interruption of bank refresh operation；Read-write Catrol logic is used for basis The refreshing result of refresh control logic is written and read.

2. DRAM memory according to claim 1, which is characterized in that doped structure wordline surface applies covering photoresist.

3. DRAM memory according to claim 1, which is characterized in that the storage array has a memory space, first The minimum unit for defining data storage cell is 192B, as a BufUnit；The memory space of 6MB is divided into 24576 most Junior unit BufUnit, minimum unit BufUnit contain 3 64B；

Wherein, the memory space is split into 3 independent memory spaces, is defined as 3 data transmission packets, correspondingly, each It actually include 16 Bank in data transmission packet, specified memory space is divided into 48 Bank.

4. DRAM memory according to claim 1, which is characterized in that the Read-write Catrol is logically divided into read operation logic sum Write operation logic works alternatively under the control action of the refresh control logic.

5. DRAM memory according to claim 4, which is characterized in that further include conflict avoidance in the Read-write Catrol logic Logic, for detecting and notifying to the reading of the Bank in the storage array or write-access and refresh rushing between access It is prominent, and use embedded cyclic redundancy check logic debugging.