CN208190997U - A kind of PCB construction optimizing signal wire reference layer - Google Patents
A kind of PCB construction optimizing signal wire reference layer Download PDFInfo
- Publication number
- CN208190997U CN208190997U CN201820458049.5U CN201820458049U CN208190997U CN 208190997 U CN208190997 U CN 208190997U CN 201820458049 U CN201820458049 U CN 201820458049U CN 208190997 U CN208190997 U CN 208190997U
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- layer
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- signals layer
- reference line
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Abstract
The utility model relates to a kind of PCB constructions for optimizing signal wire reference layer, including signals layer, signals layer adjacent layer and several signals layer non-adjacent layers, isolation disk area has been emptied on signals layer adjacent layer and signals layer non-adjacent layers, it further include the vertical perforative signal via out of isolation disk area, signals layer includes the transmission line being connected in signal via by via pad；Reference line extending towards signal via direction and identical with transmission line wiring path is connected on signals layer adjacent layer, there are gap between reference line and signal via outer wall, the projection of reference line is fallen in the isolation disk area of signals layer adjacent layer.Reference line in the utility model is playing the role of also acting as isolation interference except reference planes offer signal reflux.The signal wire above by separator is also reduced while having no need to change separator size becomes the probability of interference source, but also the signal wire by isolation disk area is not easily susceptible to interfere.
Description
Technical field
The utility model relates to PCB technical fields, and in particular to a kind of PCB construction based on via hole reference layer.
Background technique
The creator of printed circuit board is that Austrian's Borrow's Ace strangles (Paul Eisler), and 1936, he existed first
Printed circuit board is used in radio.From mid-term the 1950s, printed wiring board just starts to be widely used.?
Before PCB occurs, the interconnection between electronic component is all that electric wire is relied on to be directly connected to complete.And now electric wire is used only in
Laboratory, which is done experiment, applies and exists；Printed circuit board occupies the status absolutely controlled certainly in the electronics industry.
Via hole is also referred to as plated through-hole (PTH), in dual platen or multi-layer board, for the printed conductor being connected between each layer,
A upper common aperture, i.e. via hole are bored by the intersection for the conducting wire that each layer needs to be connected to.In technique, used on the hole wall cylindrical surface of via hole
The method of chemical deposition plates one layer of metal, the copper foil for needing to be connected to be connected to intermediate each layer, and the upper and lower surface of via hole is done
At circular pad shape, the parameter of via hole mainly porose outer diameter and bore size.The impedance of PTH would generally be than transmission line
Impedance is much lower, reaches to increase the impedance of PTH and matches with transmission line impedance, our common practices can be by PTH
Around metal flat empty to form separator, empty that area is bigger, the impedance of PTH is higher.But pass through isolation disk area
For signal wire due to not having metal flat reference, it is higher to will lead to away line impedence, seriously affects signal quality.Complete metal flat
Other than signal reflux is provided as a reference plane, the effect of isolation interference is also acted as, and excessive etched-off area can make
Signal wire by anti-pad becomes interference source, can also to be more vulnerable to interfere by the signal wire of anti-pad.
Utility model content
Technical problem to be solved by the utility model is: proposing how one kind keeps also reducing warp while separator size
The problem of signal line impedance mutation increases with interference when crossing separator.
The technical solution that the utility model proposes to solve above-mentioned technical problem is: a kind of optimization signal wire reference layer
PCB construction, including signals layer, signals layer adjacent layer and several signals layer non-adjacent layers, the signals layer adjacent layer and signals layer
Isolation disk area has been emptied on non-adjacent layers, further includes the vertical perforative signal via out of described isolation disk area, it is described
Signals layer includes the transmission line being connected in the signal via by via pad；
Be connected on the signals layer adjacent layer towards the signal via direction extend and with the transmission line cabling
The identical reference line in path, there are gap between the reference line and the signal via outer wall, the projection of the reference line is fallen
Enter in the isolation disk area of the signals layer adjacent layer.
Further, the gap width between the front end of the reference line and the signal via outer wall is 3mil.
Further, the reference line is between the signals layer and signals layer adjacent layer, the tail end of the reference line
It is connected by buried type via hole.
The beneficial effects of the utility model are:
Reference line in the utility model is playing the role of that it is dry to also act as isolation except reference planes offer signal reflux
The effect disturbed.The signal wire above by separator is also reduced while having no need to change separator size becomes interference source
Probability, but also by isolation disk area signal wire be not easily susceptible to interfere.
Detailed description of the invention
A kind of PCB construction of optimization signal wire reference layer of the utility model is described further with reference to the accompanying drawing.
Fig. 1 is the PCB construction cut-away view for optimizing signal wire reference layer in the utility model；
Fig. 2 is the structure schematic top plan view of transmission line；
Fig. 3 is the structure schematic top plan view of reference line.
Specific embodiment
Embodiment
According to Fig. 1 and Fig. 2, the PCB construction of the optimization signal wire reference layer in the utility model, including signals layer 1,
Signals layer adjacent layer 2 and several signals layer non-adjacent layers 3 are emptied on the signals layer adjacent layer 2 and signals layer non-adjacent layers 3
There is isolation disk area 4, further include the vertical perforative signal via 5 out of described isolation disk area 4, the signals layer 1 includes logical
Cross the transmission line 7 that via pad 6 is connected in the signal via 5.
It is connected with extending towards 5 direction of signal via on the signals layer adjacent layer 2 and is walked with the transmission line 7
The identical reference line 8 of thread path, there are gap between 5 outer wall of the reference line 8 and the signal via, the reference line 8
Projection is fallen in the isolation disk area 4 of the signals layer adjacent layer 2.
Can be used as preferably: the gap width between 5 outer wall of front end and the signal via of the reference line 8 is
3mil。
Can be used as preferably: the reference line 8 is between the signals layer 1 and signals layer adjacent layer 2, the ginseng
The tail end for examining line 8 is connected by buried type via hole 9.
The utility model is not limited to the above embodiment, the technical solution of above-mentioned each embodiment of the utility model that
This can form new technical solution with combined crosswise, and in addition all technical solutions formed using equivalent replacement, are all fallen within practical
In the protection scope of novel requirement.
Claims (3)
1. a kind of PCB construction for optimizing signal wire reference layer, including signals layer, signals layer adjacent layer and several signals layers are non-adjacent
Layer, it is characterised in that: emptied isolation disk area on the signals layer adjacent layer and signals layer non-adjacent layers, further included from institute
Vertical perforative signal via in isolation disk area is stated, the signals layer includes being connected to the signal via by via pad
On transmission line；
Be connected on the signals layer adjacent layer towards the signal via direction extend and with the transmission line wiring path
Identical reference line, there are gap between the reference line and the signal via outer wall, the projection of the reference line is fallen within
In the isolation disk area of the signals layer adjacent layer.
2. optimizing the PCB construction of signal wire reference layer according to claim 1, it is characterised in that: the front end of the reference line
Gap width between the signal via outer wall is 3mil.
3. optimizing the PCB construction of signal wire reference layer according to claim 2, it is characterised in that: the reference line is located at institute
It states between signals layer and signals layer adjacent layer, the tail end of the reference line is connected by buried type via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820458049.5U CN208190997U (en) | 2018-04-03 | 2018-04-03 | A kind of PCB construction optimizing signal wire reference layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820458049.5U CN208190997U (en) | 2018-04-03 | 2018-04-03 | A kind of PCB construction optimizing signal wire reference layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208190997U true CN208190997U (en) | 2018-12-04 |
Family
ID=64435877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820458049.5U Expired - Fee Related CN208190997U (en) | 2018-04-03 | 2018-04-03 | A kind of PCB construction optimizing signal wire reference layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208190997U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111970823A (en) * | 2020-07-17 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Circuit board and server |
-
2018
- 2018-04-03 CN CN201820458049.5U patent/CN208190997U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111970823A (en) * | 2020-07-17 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Circuit board and server |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181204 Termination date: 20200403 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |