CN208174654U - Pulsewidth limitation protection circuit - Google Patents
Pulsewidth limitation protection circuit Download PDFInfo
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- CN208174654U CN208174654U CN201820698963.7U CN201820698963U CN208174654U CN 208174654 U CN208174654 U CN 208174654U CN 201820698963 U CN201820698963 U CN 201820698963U CN 208174654 U CN208174654 U CN 208174654U
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- triode
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- optocoupler
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Abstract
The utility model relates to a kind of pulsewidths to limit protection circuit; it is arranged between master chip MCU and switching circuit, including optocoupler U1, triode VT1, resistance R2, resistance R3, nor gate U2, resistance R4, resistance R5, diode D1, capacitor C1, resistance R5, nor gate U3, resistance R6, resistance R7, triode VT2 and diode D2.The utility model by between master chip MCU and switching circuit be arranged pulsewidth limit protection circuit, increase anti-interference ability, in control circuit exception, can effective protection control circuit and user equipment, ensure that safety.
Description
Technical field：
The utility model relates to IGBT drive circuit more particularly to a kind of pulsewidth limitation protection circuits.
Background technique：
Switch element in current switch circuit has chip to drive by light-coupled isolation mostly, in the application of high-voltage great-current
Often there are many disturbing factors in occasion, influence the normal transmission of signal, sometimes due to control circuit failure itself causes to drive
Signal is effective for a long time, and the switch element in such switching circuit is connected for a long time, causes fault, burns circuit, even
Burning apparatus.
Utility model content：
The purpose of this utility model is in view of the drawbacks of the prior art, to provide a kind of pulsewidth limitation protection circuit, can limit
Pulsewidth processed, protective switch circuit and element.
The utility model is achieved by the following technical solution：A kind of pulsewidth limitation protection circuit, is arranged in master chip
Between MCU and switching circuit, including optocoupler U1, triode VT1, resistance R2, resistance R3, nor gate U2, resistance R4, resistance R5,
Diode D1, capacitor C1, resistance R5, nor gate U3, resistance R6, resistance R7, triode VT2 and diode D2, the optocoupler U1
Input terminal connect with master chip MCU, one end of the output of optocoupler U1 is connected with the collector of triode VT1, optocoupler U1 output
The other end be connected with one end of resistance R2, the other end of resistance R2 is connected with the base stage of triode VT1, the hair of triode VT1
Emitter-base bandgap grading is connected with resistance R3, the input terminal of nor gate U2, resistance R5, diode D1, the other end and resistance R4, capacitor of resistance R3
C1, which is connected, to be grounded, and another input terminal of the other end AND OR NOT gate U2 of resistance R4 is connected, the other end and diode D1 of capacitor C1,
Resistance R5, the input terminal of nor gate U3 are connected, and another input terminal of the output end AND OR NOT gate U3 of nor gate U2 is connected, nor gate
The output end of U3 is connected with resistance R6, and the other end of resistance R6 is connected with the base stage of triode VT2, the emitter of triode VT2
It is connected with resistance R7, the other end of resistance R7 is connected with the anode of diode D2, and the cathode of diode D2 is connected with switching circuit.
Preferably, the triode is NPN triode.
Preferably, being connected with resistance R1 between the master chip MCU and optocoupler U1.
The utility model has the beneficial effects that：The utility model is by being arranged arteries and veins between master chip MCU and switching circuit
Tolerance system protection circuit, increases anti-interference ability, in control circuit exception, can effective protection control circuit and user set
It is standby, it ensure that safety.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model pulsewidth limitation protection circuit.
Specific embodiment：
The preferred embodiment of the utility model is described in detail with reference to the accompanying drawing, so that the advantages of the utility model
It can be easier to be understood by those skilled in the art with feature, to make apparent specific boundary to the protection scope of the utility model
It is fixed.
As shown in Figure 1, a kind of pulsewidth limitation protection circuit, is arranged between master chip MCU and switching circuit, including optocoupler
U1, NPN triode VT1, resistance R2, resistance R3, nor gate U2, resistance R4, resistance R5, diode D1, capacitor C1, resistance R5,
Nor gate U3, resistance R6, resistance R7, the input terminal of NPN triode VT2 and diode D2, the optocoupler U1 and master chip MCU are logical
Resistance R1 connection is crossed, one end of the output of optocoupler U1 is connected with the collector of NPN triode VT1, the other end of optocoupler U1 output
It is connected with one end of resistance R2, the other end of resistance R2 is connected with the base stage of NPN triode VT1, the transmitting of NPN triode VT1
Pole is connected with resistance R3, the input terminal of nor gate U2, resistance R5, diode D1, the other end and resistance R4, capacitor C1 of resistance R3
Be connected ground connection, and another input terminal of the other end AND OR NOT gate U2 of resistance R4 is connected, the other end and diode D1, electricity of capacitor C1
Resistance R5, the input terminal of nor gate U3 are connected, and another input terminal of the output end AND OR NOT gate U3 of nor gate U2 is connected, nor gate U3
Output end be connected with resistance R6, the other end of resistance R6 is connected with the base stage of NPN triode VT2, the hair of NPN triode VT2
Emitter-base bandgap grading is connected with resistance R7, and the other end of resistance R7 is connected with the anode of diode D2, the cathode and switching circuit of diode D2
It is connected.
When master chip MCU does not send pulse, optocoupler U1 does not work, and NPN triode VT1 is not turned on, the input of nor gate U2
Be it is low, export as height, the input of nor gate U3 be it is one high and one low, export to be low, NPN triode VT2 is not turned on, and is exported and is
It is low；
When master chip MCU sends pulse, optocoupler U1 work, NPN triode VT1 conducting, the input of nor gate U2 is one
High one is low, exports to be low, input one end of nor gate U3 be it is low, from low to high, output is from high to low for the input other end；
When the pulse that master chip MCU is sent is less than the limits value of pulsewidth limitation protection circuit, what master chip MCU was sent
Pulse can export completely, conversely, the limits value of output pulse width limitation protection circuit, long if master chip MCU cisco unity malfunction
Time allows optocoupler U1 to be connected, and pulsewidth limitation protection circuit no longer exports after export-restriction width pulse.
Compared with prior art, the utility model limits guarantor by the way that pulsewidth is arranged between master chip MCU and switching circuit
Protection circuit increases anti-interference ability, in control circuit exception, can effective protection control circuit and user equipment, guarantee
Safety.
Above-described embodiments merely represent several embodiments of the utility model, the description thereof is more specific and detailed,
But it cannot be understood as the limitations to utility model patent range.It should be pointed out that for the common skill of this field
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
The protection scope of the utility model.
Claims (3)
1. a kind of pulsewidth limitation protection circuit, is arranged between master chip MCU and switching circuit, it is characterised in that：Including optocoupler
U1, triode VT1, resistance R2, resistance R3, nor gate U2, resistance R4, resistance R5, diode D1, capacitor C1, resistance R5 or non-
Door U3, resistance R6, resistance R7, triode VT2 and diode D2, the input terminal of the optocoupler U1 are connect with master chip MCU, optocoupler
One end of the output of U1 is connected with the collector of triode VT1, and the other end of optocoupler U1 output is connected with one end of resistance R2, electricity
The other end of resistance R2 is connected with the base stage of triode VT1, the emitter of triode VT1 and resistance R3, nor gate U2 input terminal,
Resistance R5, diode D1 are connected, and the other end of resistance R3 is connected ground connection with resistance R4, capacitor C1, the other end of resistance R4 and or
Another input terminal of NOT gate U2 is connected, and the other end of capacitor C1 is connected with the input terminal of diode D1, resistance R5, nor gate U3,
Another input terminal of the output end AND OR NOT gate U3 of nor gate U2 is connected, and the output end of nor gate U3 is connected with resistance R6, resistance
The other end of R6 is connected with the base stage of triode VT2, and the emitter of triode VT2 is connected with resistance R7, the other end of resistance R7
It is connected with the anode of diode D2, the cathode of diode D2 is connected with switching circuit.
2. pulsewidth limitation protection circuit according to claim 1, it is characterised in that：The triode is NPN triode.
3. pulsewidth limitation protection circuit according to claim 1, it is characterised in that：The master chip MCU and optocoupler U1 it
Between be connected with resistance R1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820698963.7U CN208174654U (en) | 2018-05-10 | 2018-05-10 | Pulsewidth limitation protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820698963.7U CN208174654U (en) | 2018-05-10 | 2018-05-10 | Pulsewidth limitation protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208174654U true CN208174654U (en) | 2018-11-30 |
Family
ID=64366040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820698963.7U Active CN208174654U (en) | 2018-05-10 | 2018-05-10 | Pulsewidth limitation protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208174654U (en) |
-
2018
- 2018-05-10 CN CN201820698963.7U patent/CN208174654U/en active Active
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| GR01 | Patent grant |