CN208142187U - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
- Publication number
- CN208142187U CN208142187U CN201820601381.2U CN201820601381U CN208142187U CN 208142187 U CN208142187 U CN 208142187U CN 201820601381 U CN201820601381 U CN 201820601381U CN 208142187 U CN208142187 U CN 208142187U
- Authority
- CN
- China
- Prior art keywords
- shallow trench
- active area
- silicon oxide
- semiconductor structure
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000013078 crystal Substances 0.000 claims abstract 2
- 239000000463 material Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
The utility model provides a semiconductor structure, semiconductor structure includes: a semiconductor substrate; an active region located within the semiconductor substrate; the shallow trench is positioned in the semiconductor substrate and positioned between the active regions; and the silicon oxide layer is positioned in the shallow trench and at least covers the bottom of the shallow trench and the side wall of the active region. The utility model discloses a semiconductor structure forms the silicon oxide layer through the etching in the semiconductor substrate in the shallow trench that the active area was kept apart out, when can effectively restoreing the crystal lattice damage that exists in the active area, and does not lead to the fact any consumption to the active area to furthest has remain the active area that is used for forming semiconductor device, has effectively improved the availability factor of semiconductor substrate, is showing and has practiced thrift the cost.
Description
Technical field
The utility model relates to semiconductor process technique fields, more particularly to a kind of semiconductor structure.
Background technique
In existing semiconductor technology, semiconductor devices is prepared on semiconductor substrate (for example wafer) before generally
It needs to carry out dry etching to the semiconductor substrate, forms shallow trench in the semiconductor substrate to serve as a contrast in the semiconductor
Several active areas are isolated in bottom, then fill insulant layer forms fleet plough groove isolation structure in the shallow trench again；
Various required semiconductor devices are then prepared on the active area.Then, dry etch process etching semiconductor is being used
When substrate forms active area, due to the charged particle or group in the etching gas of dry etching containing high-energy, the electrification
While particle or the group bombardment semiconductor substrate form the shallow trench, meeting shape in the finally formed active area
At lattice damage.However, since the semiconductor devices being ultimately to be formed almost is respectively positioned in the active area and the active area
On, if the lattice damage formed in the active area cannot remove in time, the lattice damage being present in the active area is inevitable
Adverse effect can be caused to the performance of semiconductor devices；Moreover, with the increasingly reduction of semiconductor device design size, active area
Interior existing lattice damage is more significant to the adverse effect of semiconductor devices.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor structures, use
It can be active when solving to form active area using dry etch process etching shallow trench in semiconductor substrate in the prior art
The problem of forming lattice damage in area, and then adverse effect caused to the performance of the semiconductor devices formed on the active area.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor structure, the semiconductor
Structure：
Semiconductor substrate；
Active area is located in the semiconductor substrate；
Shallow trench is located in the semiconductor substrate, and between the active area；And
Silicon oxide layer is located in the shallow trench, and be at least covered in the shallow trench bottom and the active area
On side wall.
As a kind of preferred embodiment of the utility model, the thickness of the silicon oxide layer is less than closest two active areas
The half of spacing.
As a kind of preferred embodiment of the utility model, the silicon oxide layer is also covered in the upper surface of the active area.
As a kind of preferred embodiment of the utility model, the thickness of the silicon oxide layer is less than or equal to 200 angstroms.
As a kind of preferred embodiment of the utility model, the semiconductor structure further includes material layer, described siliceous
Material layer is between the silicon oxide layer and the active area and between the silicon oxide layer and the semiconductor substrate.
As a kind of preferred embodiment of the utility model, the silicon oxide layer is by material layer thermal oxidation institute
It is formed.
As a kind of preferred embodiment of the utility model, the material layer includes silicon nitride layer or polysilicon layer.
As a kind of preferred embodiment of the utility model, the shallow trench includes the first shallow trench and the second shallow trench,
In, the width of first shallow trench is greater than the width of second shallow trench, and the depth of first shallow trench is greater than institute
State the depth of the second shallow trench.
As a kind of preferred embodiment of the utility model, the semiconductor structure further includes fleet plough groove isolation structure, described
Fleet plough groove isolation structure is located at the surface of the silicon oxide layer, and fills up the shallow trench.
As a kind of preferred embodiment of the utility model, the semiconductor substrate is monocrystalline substrate.
As described above, the semiconductor structure of the utility model, has the advantages that：The semiconductor junction of the utility model
Structure forms silicon oxide layer by etching to be formed in the shallow trench for isolating active area in semiconductor substrate, can effectively repair
In active area while existing lattice damage, any consumption is not caused to active area, to remain use to the maximum extent
In the active area for forming semiconductor devices, the service efficiency of semiconductor substrate is effectively increased, cost has significantly been saved.
Detailed description of the invention
Fig. 1 is shown as the overlooking structure diagram of the semiconductor structure provided in one example of the utility model.
Fig. 2 is shown as the cross section structure schematic diagram in the direction AA ' along Fig. 1.
Fig. 3 is shown as the overlooking structure diagram of the semiconductor structure provided in another example of the utility model.
Fig. 4 is shown as the cross section structure schematic diagram in the direction AA ' along Fig. 3.
Component label instructions
10 semiconductor substrates
11 shallow trench
111 first shallow trench
112 second shallow trench
12 active areas
13 material layers
14 silicon oxide layers
15 fleet plough groove isolation structures
Specific embodiment
Illustrate the embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this
Content disclosed by specification understands other advantages and effect of the utility model easily.The utility model can also be by another
Outer different specific embodiment is embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
It please refers to Fig.1 to Fig.4.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in schema
Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
Fig. 1 and Fig. 2 is please referred to, the utility model provides a kind of semiconductor structure, and the semiconductor structure includes：Semiconductor
Substrate 10；Active area 12, the active area 12 are located in the semiconductor substrate 10；Shallow trench 11, the shallow trench 11 are located at
In the semiconductor substrate 10, and between the active area 12, specifically, the shallow trench 11 is in the semiconductor substrate
Several active areas 12 are isolated in 10；And silicon oxide layer 14, the silicon oxide layer 14 are located in the shallow trench 11,
And it is at least covered on the bottom of the shallow trench 11 and the side wall of the active area 12.
As an example, the semiconductor substrate 10 can be but be not limited only to silicon substrate, it is preferable that in the present embodiment, institute
Stating semiconductor substrate 10 can be Silicon Wafer.
As an example, the shallow trench 11 can in the shape of the active area 12 isolated in the semiconductor substrate 10
Ellipse is thought, certainly, in other examples, needed for can also being according to actual needs shaped to the active area 12
Shape.
As an example, the shallow trench 11 includes the first shallow trench 111 and the second shallow trench 112, wherein described first is shallow
The width of groove 111 is greater than the width of second shallow trench 112, and the depth of first shallow trench 111 is greater than described the
The depth of two shallow trench 112.Since the width of first shallow trench 111 is greater than the width of second shallow trench 112, in phase
The depth of first shallow trench 111 can be made to be greater than second shallow trench 112 under the conditions of same dry etch process
Depth.The direction AA ' shown in Fig. 1, first shallow trench 111, the active area 12 and second shallow trench 112 according to
It is secondary to be arranged alternately.
As an example, the silicon oxide layer 14 can be by using but being not limited only to low-pressure chemical vapor deposition (LPCVD) work
13 heat of the material layer that skill deposition is formed on the bottom of the shallow trench 11 and the side wall of the active area 12
It aoxidizes and is formed, will not have any consumption to the active area 12 when ensuring to be formed the silicon oxide layer 14.Specifically, can
To carry out thermal oxidation to the material layer 13 using dry-oxygen oxidation method, can also be contained using wet-oxygen oxidation method to described
Silicon material layer 13 is heat-treated, and vapor oxidation method can also be used to be heat-treated to obtain the material layer 13
State silicon oxide layer 14.More specifically, the structure that surface can be formed with to the material layer 13 is placed in annealing device
It is heat-treated in (for example, tube furnace, annealing furnace etc.), the temperature of heat treatment is between 900 DEG C~1200 DEG C.Heat treatment when
Between set according to actual needs, it is preferable that during heat treatment, the material layer 13 is thermally oxidized as the oxygen
SiClx layer 14, i.e., in the step, the material layer 13 is converted into the silicon oxide layer 14, and the active area 12 does not have
Any loss.
As an example, sinking the silicon oxide layer 14 is also covered in the upper surface of the active area 12.
As an example, the thickness of the silicon oxide layer 14 can be set according to actual needs, it is preferable that the present embodiment
In, the thickness of the silicon oxide layer 14 should be less than the half of closest two 12 spacing of active area, to ensure the silica
Adjacent two active area 12 will not be connected by layer 14.
As an example, the lattice structure for forming the material layer 13 of the silicon oxide layer 14 include polycrystalline structure and
One of non crystalline structure.
In one example, the material layer 13 may include polysilicon layer；The thickness of the polysilicon layer can be small
In being equal to 150 angstroms, i.e., the thickness of the described polysilicon layer is greater than 0 angstrom and is less than or equal to 150 angstroms；Certainly, in other examples, described
The thickness of polysilicon layer can be set according to actual needs, but be necessary to ensure that the material layer 13 will not be by adjacent institute
Active area 12 is stated to be connected.
In another example, the material layer 13 for forming the silicon oxide layer 14 can also include silicon nitride layer,
The thickness of the silicon nitride layer is less than or equal to 200 angstroms, i.e., the thickness of the described silicon nitride layer is greater than 0 angstrom and is less than or equal to 200 angstroms；When
So, in other examples, the thickness of the silicon nitride layer can be set according to actual needs, but be necessary to ensure that described siliceous
The adjacent active area 12 will not be connected by material layer 13.
In one example, the silicon oxide layer 14 can be by obtaining 13 complete oxidation of material layer, i.e. institute
The thickness for stating silicon oxide layer 14 can be equal to the thickness of the silicon oxide-containing layer 13, also that is, the inner surface of the silicon oxide layer 14
On the side wall for adhering on the active area 12.
In another example, the silicon oxide layer 14 can also be obtained by 13 partial oxidation of material layer, i.e.,
The thickness of the silicon oxide layer 14 be less than the material layer 13 thickness, at this point, the silicon oxide layer 14 with it is described active
There is also have the material floor 13, i.e., non-oxygen between area 12 and between the silicon oxide layer 14 and the semiconductor substrate 10
The material layer 13 changed is between the silicon oxide layer 14 and the active area 12 and the silicon oxide layer 14 and institute
It states between semiconductor substrate 10.
As an example, the semiconductor structure further includes fleet plough groove isolation structure 15, the fleet plough groove isolation structure 15
In the surface of the silicon oxide layer 14, and the shallow trench 11 is filled up, each active area 12 is isolated.
In conclusion the utility model provides a kind of semiconductor structure, the semiconductor structure includes：Semiconductor substrate；
Active area is located in the semiconductor substrate；Shallow trench is located in the semiconductor substrate, and between the active area；
And silicon oxide layer, it is located in the shallow trench, and be at least covered in the bottom of the shallow trench and the side wall of the active area
On.The semiconductor structure of the utility model is formed by etching to be formed in the shallow trench for isolating active area in semiconductor substrate
Silicon oxide layer does not cause any consumption to active area while effectively can repair existing lattice damage in active area,
To remain the active area for being used to form semiconductor devices to the maximum extent, the use effect of semiconductor substrate is effectively increased
Rate has significantly saved cost.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (10)
1. a kind of semiconductor structure, which is characterized in that the semiconductor structure includes：
Semiconductor substrate；
Active area is located in the semiconductor substrate；
Shallow trench is located in the semiconductor substrate, and between the active area；And
Silicon oxide layer is located in the shallow trench, and is at least covered in the bottom of the shallow trench and the side wall of the active area
On.
2. semiconductor structure according to claim 1, it is characterised in that：The thickness of the silicon oxide layer is less than closest two
The half of the active area spacing.
3. semiconductor structure according to claim 1, it is characterised in that：The silicon oxide layer is also covered in the active area
Upper surface.
4. semiconductor structure according to claim 1, it is characterised in that：The thickness of the silicon oxide layer is less than or equal to 200
Angstrom.
5. semiconductor structure according to claim 1, it is characterised in that：The semiconductor structure further includes material
Layer, the material layer is between the silicon oxide layer and the active area and the silicon oxide layer is served as a contrast with the semiconductor
Between bottom.
6. semiconductor structure according to claim 5, it is characterised in that：The silicon oxide layer is by the material layer warm
Oxidation processes are formed.
7. semiconductor structure according to claim 5, it is characterised in that：The material layer includes silicon nitride layer or more
Crystal silicon layer.
8. semiconductor structure according to claim 1, it is characterised in that：The shallow trench includes the first shallow trench and second
Shallow trench, wherein the width of first shallow trench is greater than the width of second shallow trench, and the depth of first shallow trench
Degree is greater than the depth of second shallow trench.
9. semiconductor structure according to claim 1, it is characterised in that：The semiconductor structure further includes shallow trench isolation
Structure, the fleet plough groove isolation structure are located at the surface of the silicon oxide layer, and fill up the shallow trench.
10. semiconductor structure according to claim 1, it is characterised in that：The semiconductor substrate is monocrystalline substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820601381.2U CN208142187U (en) | 2018-04-25 | 2018-04-25 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820601381.2U CN208142187U (en) | 2018-04-25 | 2018-04-25 | Semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208142187U true CN208142187U (en) | 2018-11-23 |
Family
ID=64311103
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820601381.2U Expired - Fee Related CN208142187U (en) | 2018-04-25 | 2018-04-25 | Semiconductor structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN208142187U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11676810B2 (en) | 2020-07-02 | 2023-06-13 | Changxin Memory Technologies, Inc. | Semiconductor structure processing method and forming method |
| US11978636B2 (en) | 2020-07-02 | 2024-05-07 | Changxin Memory Technologies, Inc. | Methods for processing semiconductor structures and methods for forming semiconductor structures |
-
2018
- 2018-04-25 CN CN201820601381.2U patent/CN208142187U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11676810B2 (en) | 2020-07-02 | 2023-06-13 | Changxin Memory Technologies, Inc. | Semiconductor structure processing method and forming method |
| US11978636B2 (en) | 2020-07-02 | 2024-05-07 | Changxin Memory Technologies, Inc. | Methods for processing semiconductor structures and methods for forming semiconductor structures |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181123 Termination date: 20190425 |
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| CF01 | Termination of patent right due to non-payment of annual fee |