CN208127143U - The embedded type encapsulating structure of rectilinear chip and horizontal chip - Google Patents
The embedded type encapsulating structure of rectilinear chip and horizontal chip Download PDFInfo
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- CN208127143U CN208127143U CN201820221036.6U CN201820221036U CN208127143U CN 208127143 U CN208127143 U CN 208127143U CN 201820221036 U CN201820221036 U CN 201820221036U CN 208127143 U CN208127143 U CN 208127143U
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- blind hole
- chip
- substrate
- face
- rectilinear
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Abstract
The utility model provides the embedded type encapsulating structure of a kind of rectilinear chip and horizontal chip, it includes：One substrate, it has one first face and one second opposite face, a first circuit layer, drilling via formations at least one first blind hole or at least one second blind hole on first face are equipped on second face, and each blind hole is each passed through the substrate thickness and is connected to the first circuit layer；An at least chip, it includes rectilinear chip or horizontal chips；Wherein each chip, which is respectively embedded into, is located in corresponding each first blind hole, and makes each brilliant pad set on second surface that conduction material can be relied on to be linked to the first circuit layer of the substrate；Set a second circuit layer again later, at least one brilliant pad for making to be located on the first surface of the rectilinear chip can be by the second circuit layer with electrical connection to the first circuit layer；An embedded type encapsulating structure is so completed, the advantages of thickness is greatly decreased, processing procedure relative simplicity, conductive reliability are promoted is reached.
Description
Technical field
It is espespecially a kind of to be embedded in rectilinear chip or horizontal chip the utility model relates to a kind of encapsulating structure of chip
And it welds knot and is located at the embedded type encapsulating structure that encapsulating structure thickness is effectively reduced in the blind hole of a substrate.
Background technique
In chip package structure technical field, current existing a variety of background techniques are such as：US8,211,722, US6,
914,268、US8,049,230、US7,985,979、US7,939,832、US7,713,353、US7,642,121、US7,462,
861、US7,393,411、US7,335,519、US7,294,866、 US7,087,526、US5,557,115、US6,514,782、
US6,497,944, US6,791,119, US2011/0014734, US2002/0163302, US2004/0113156 etc..It is existing
On the whole wafer package technology is in the way of surface adhering technical (SMT) or other electrical connections such as wire bond (wire
Bond) technology, which welds a chip, ties and is fixed on a substrate (core board or support plate substrate, such as printed circuit
Plate) on surface on the contact of each default route to complete for example common crystal covering type (flip-chip) encapsulation of a chip package structure
It structure but does not limit；In application, the chip package structure again tie and be fixed on a mainboard (such as printed circuit board) surface by corresponding weldering
Predeterminated position on, so complete the subsequent installation processing procedure of the chip package structure.
For the setting kenel for separately padding (such as pole P/N) with crystalline substance each on chip, chip can be divided into rectilinear chip and horizontal
Chip, a rectilinear chip have at least two brilliant pads (such as pole P/N) and are separately located at first surfaces of the chip and opposite
It such as power supply (power) chip, light emitting diode (LED) chip (such as red LED) but is not limited on second surface；One horizontal
Chip has at least two brilliant pads and with being located on a surface of the chip such as the second surface of the utility model meaning but do not limit.
In addition, will be usually located on wherein a surface (such as first surface) for the flip-chip type package structure of a rectilinear chip
Each brilliant pad be first electrically connected to and be located at each brilliant pad on wherein another surface (such as second surface) and be located on same plane,
Surface adhering technical (SMT) is recycled to carry out subsequent flip-chip type package operation；And with default route each on substrate surface
Connecting point position difference, an encapsulating structure further again can be divided into fan inner mold (Fan-In) or fan-out-type (Fan-Out) encapsulation
Structure.
In existing chip package structure, since chip is weldering knot and is fixed on the surface of substrate, therefore a wafer package
The thickness of structure basically comprises the thickness of chip and the thickness of substrate, and the thickness of rectilinear chip package structure is generally again
Greater than the thickness of horizontal chip package structure, because the thickness of chip package structure is difficult to be effectively reduced, it has been unable to satisfy at present
Gently, thin, short and small requirement.
Utility model content
From the foregoing, it will be observed that for a chip package structure, how to effectively reduce package thickness or simplify encapsulating structure or its
Processing procedure, and can be suitably used for rectilinear chip or horizontal chip again, still there are improved needs, the utility model is directed to above-mentioned
It needs and proposes solution.
To achieve the above object, the technical solution adopted in the utility model is：
A kind of embedded type encapsulating structure of rectilinear chip, it is characterized in that comprising：
One substrate has one first face and one second opposite face, wherein being equipped with one first circuit on second face
Layer, drilling via formations at least one first blind hole and at least one second blind hole on the first face of the substrate, wherein each first blind hole and
Each second blind hole passes through the substrate thickness by first face respectively and is connected to the first circuit layer；
At least one rectilinear chip, each rectilinear chip have at least two brilliant pads, and wherein at least one brilliant pad is located at each vertical
On one first surface of formula chip, and other at least one brilliant pads are located on opposite second surface, and each rectilinear chip is embedded in
In corresponding each first blind hole, and each brilliant pad for making to set on a second surface can be by conduction material with electrical connection to the substrate
First circuit layer；
One insulating layer is covered on the first face of the substrate, and a drilling via formations at least third is blind on which insulating layer
Hole and at least one the 4th blind hole；Wherein each third blind hole is connected to the first table of the rectilinear chip across the thickness of insulating layer
Face；Wherein each 4th blind hole is through the thickness of insulating layer and correspondence is connected to each second blind hole set on the substrate, makes each the
Four blind holes can form about the one integral type blind hole being connected to corresponding each second blind hole；
One the second circuit layer is molded on the surface of the insulating layer and each third blind hole, each using electroplating technology
On the inner wall of 4th blind hole and each second blind hole, making to be located at each brilliant pad on the first surface of the rectilinear chip can be by being somebody's turn to do
The second circuit layer with electrical connection is to the first circuit layer.
The embedded type encapsulating structure of the rectilinear chip, wherein：The insulating layer further fills up each rectilinear chip
It is embedded in gap left in each first blind hole.
The embedded type encapsulating structure of the rectilinear chip, wherein：It also include an outer jacket, which is covered in this
In the second circuit layer and fill up each third blind hole, each 4th blind hole and each second blind hole.
The embedded type encapsulating structure of the rectilinear chip, wherein：The depth of first blind hole of the substrate is hung down equal to this
The thickness of straight chip.
A kind of embedded type encapsulating structure of horizontal chip, it is characterized in that comprising：
One substrate has one first face and one second opposite face, and a first circuit layer is equipped on second face,
Drilling via formations at least one first blind hole on first face of the substrate, wherein each first blind hole passes through the substrate by first face respectively
Thickness and be connected to the first circuit layer；
An at least horizontal chip has at least two brilliant pads, which is separately located at the horizontal chip
On one second surface, wherein each horizontal chip is embedded in corresponding each first blind hole, and make to set on a second surface
Each brilliant pad can dividually be electrically connected to the first circuit layer of the substrate by conduction material respectively；
One insulating layer, is covered on the first face of the substrate and fills up each horizontal chip and be embedded in each first blind hole
Left gap.
The utility model major advantage is：The embedded type encapsulating structure for so completing a horizontal chip, so that thickness
It is greatly decreased, processing procedure relative simplicity and the conductive reliability of acquisition are promoted.
Detailed description of the invention
Fig. 1 is schematic cross-sectional view in the processing procedure of one embodiment of embedded type encapsulating structure of the rectilinear chip of the utility model.
Fig. 2 is the schematic cross-sectional view of embedded type encapsulating structure shown in Fig. 1.
Fig. 3 to Fig. 7 is the manufacturing process schematic diagram of embedded type encapsulating structure shown in Fig. 2 respectively.
Fig. 8 is schematic cross-sectional view in the processing procedure of one embodiment of embedded type encapsulating structure of the utility model horizontal chip.
Fig. 9 is the schematic cross-sectional view of embedded type encapsulating structure shown in Fig. 8.
Figure 10 to Figure 12 is the manufacturing process schematic diagram of embedded type encapsulating structure shown in Fig. 9 respectively.
Description of symbols：1- encapsulating structure；1a- encapsulating structure；2- sheet parent；2a- sheet parent；10- substrate；
The first face 11-；The second face 12-；13- first circuit layer；13a- copper foil layer；The first blind hole of 14-；The second blind hole of 15-；20- is vertical
Formula chip；20a- horizontal chip；21- crystalline substance pad；21a- crystalline substance pad；21b- crystalline substance pad；22- first surface；23- second surface；30-
Insulating layer；30a- insulating layer；31- third blind hole；The 4th blind hole of 32-；40- the second circuit layer；50- outer jacket.
Specific embodiment
To keep the utility model definitely full and accurate, hereby enumerates preferred embodiment and cooperate following schemes, it will be originally practical new
The structure and its technical characteristic of type are described in detail as after, wherein each illustrate only to the structural relation for illustrating the utility model and related function
Can, therefore each portion's size or shape or size are not according to actual ratio setting and non-to limit the utility model：
Referring to figs. 1 to Fig. 7, a kind of embedded type encapsulating structure 1 of rectilinear chip of the present embodiment system, it includes：One substrate
10, at least one rectilinear chip 20, an insulating layer 30, a second circuit layer 40 or an outer jacket 50, the wherein encapsulating structure 1
A sheet parent 2 with multiple encapsulating structures 1 (daughter) is completed (such as using the substrate 10 of a tool larger area to synchronize
Shown in Fig. 1), then be cut to multiple encapsulating structures 1 (daughter) to the sheet parent 2, but non-practical to limit
It is novel.
The substrate 10 has one first face 11 and one second opposite face 12, and wherein molding is equipped with one the on second face 12
One circuit layer 13.The present embodiment ties up to drilling via formations at least one first blind hole 14 and at least 1 on the first face 11 of the substrate 10
Two blind holes 15, the present embodiment system as shown in Figures 1 to 7 illustrate but unlimited by taking one first blind hole 14 and one second blind hole 15 as an example
System.Each first blind hole 14 and each second blind hole 15 pass through 10 thickness of substrate by first face 11 respectively and are connected to first electricity
The inner face of road floor 13, wherein the depth design of each first blind hole 14 is at the thickness for being approximately equal to the rectilinear chip 20.Further, since
Each first blind hole 14 and each second blind hole 15 pass through 10 thickness of substrate and are connected to the inner face of the first circuit layer 13, but machine
Tool drilling technique be not easy accurate control blind hole depth and thus be easy to injure the first circuit layer 13, therefore the present embodiment is to utilize
Laser drill technology is come to make each blind hole 14,15 be best.
Existing double-layer circuit board further can be used in the substrate 10, i.e., the substrate 10 is on the first face 11 and the second face 12
It is respectively provided with a copper foil layer 13a, wherein the copper foil layer 13a being located on the second face 12 to form the first circuit layer 13 to make,
The copper foil layer 13a being wherein located on first face 11 can have relatively thin thickness, for that Laser drill technology can be utilized directly to pass through
Wear the relatively thin copper foil layer 13a and each first blind hole 14 of drilling via formations and each second blind hole 15.
Each rectilinear chip 20 has at least two brilliant pads 21 such as brilliant pad 21a, 21b comprising positive and negative electrode but does not limit,
In at least two brilliant pad 21 be separately located on the first surface 22 and opposite second surface 23 of each chip 20, such as at least one is brilliant
Pad 21a is located on a first surface 22 of each chip 20, and remaining at least one brilliant pad 21b is located at one second table of each chip 20
It on face 23 but does not limit, that is, forms the brilliant pad-type state for being generally generally called rectilinear chip；Each rectilinear chip 20 is embedded in the substrate
In 10 corresponding each first blind hole 14, since the depth system of each first blind hole 14 is designed to be approximately equal to the rectilinear chip
20 thickness, thus at least one brilliant pad 21a being located on the first surface 22 of each rectilinear chip 20 can be exposed at just this first
At the aperture of blind hole 14.At least one brilliant pad 21b on the second surface 22 of the rectilinear chip 20 relies on conduction material 24 such as tin ball
Or elargol etc. but do not limit, the inner face of with electrical connection to the first circuit layer 13 of the substrate 10 and form on state.
The insulating layer 30 is covered on the first face 11 of the substrate 10, and it is each vertical so that the insulating layer 30 is further filled up
The gap left when being embedded in each first blind hole 14 of formula chip 20 is as shown in figure 5, so that each rectilinear chip 20 can be securely
Positioning, and can avoid unfilled and have the problem of being easy to happen thermal expansion in the presence of bubble in use and bursting.In the insulation
Recycle Laser drill technology to form an at least third blind hole 31 and at least one the 4th blind hole 32 on layer 30.Each third blind hole 31
At least one brilliant pad 21a being connected on the first surface 21 of the rectilinear chip 20 across 30 thickness of insulating layer, but each the
Three blind holes 31 preferably can be effectively controlled to injure the rectilinear chip 20 in Laser drill.In addition, each 4th blind hole 32
Further it can run through and correspond to each second blind hole 15 for being connected to and being located on the substrate 10 simultaneously when Laser drill forms, make
Each 4th blind hole 32 can form about the one integral type blind hole 32,15 being connected to corresponding each second blind hole 15.Due to each
The drilling depth of first, second and third blind hole 14,15,31 accurate must control, therefore the utility model using Laser drill technology to be made
It is best for making each blind hole 14,15.Furthermore by each 4th blind hole 32 and the formed integral type blind hole of corresponding each second blind hole 15
32,15 total depth is relatively deep, is probably difficult to just mold the integral type blind hole 32,15 by a Laser drill operation, because
This utility model is first forming each second blind hole 15 by secondary Laser drill operation, then at each 4th blind hole 32 of molding
Run through and be connected to corresponding each second blind hole 15 simultaneously, so that each 4th blind hole 32 is formed with each corresponding second blind hole 15
The integral type blind hole 32,15 of about one connection, can so promote the efficiency of bore operation.
The second circuit layer 40 is molded on the surface of the insulating layer 30 using electroplating technology and each third blind hole 31, each
4th blind hole 32 makes to be located on the first surface 22 of each rectilinear chip 20 on the inner wall of each corresponding second blind hole 15
At least one brilliant pad 21a can so make the rectilinear crystalline substance by 40 with electrical connection of the second circuit layer to the first circuit layer 13
Piece 20, which sets up each at least one brilliant pad 21a, 21b on the first and second surface 22,23 vertically separately, can be electrically connected to this
First circuit layer 13 is simultaneously respectively formed a solder joint, therefore when the encapsulating structure 1 of the utility model is as shown in the direction arrow A in Fig. 2
It to be mounted on an external mainboard such as printed circuit board (not shown), each weldering being respectively formed in the first circuit layer 13 downwards
Point be able to maintain it is smooth, be conducive to carry out subsequent installation processing procedure such as surface mount technology (Surface Mount Technology,
SMT)。
In addition, the embedded type encapsulating structure 1 of the present embodiment can further set an outer jacket 50, which is smooth
Ground is covered in the second circuit layer 40 and fills up each third blind hole 31, each 4th blind hole 32 and the second blind hole 15 being respectively connected to,
To protect the second circuit layer 40 and be formed by encapsulating structure 1.
The manufacturing method of the embedded type encapsulating structure 1 of the rectilinear chip 20 of the present embodiment, comprises the steps of：
Step S1：With reference to Fig. 3, a substrate 10 is provided, there is one first face 11 and one second opposite face 12, at this
Second face 12 be equipped with a first circuit layer 13, on the first face 11 of the substrate 10 drilling via formations at least one first blind hole 14 and
At least one second blind hole 15, wherein each first blind hole 14 and each second blind hole 15 pass through the substrate 10 by first face 11 respectively
Thickness and the inner face for being connected to the first circuit layer 13.
Step S2：With reference to Fig. 4, at least one rectilinear chip 20 is provided, each rectilinear chip 20 is equipped at least two brilliant pads 21,
Wherein at least one brilliant pad 21a is located on a first surface 22 of the chip 20, and wherein at least one brilliant pad 21b is located at the chip 20
On an opposite second surface 23.
Step S3：With reference to Fig. 4, each rectilinear chip 20 is respectively corresponded to each first blind hole 14 for being embedded in the substrate 10
It is interior, and enable at least one brilliant pad 21b set on the second surface 22 of each rectilinear chip 20 by conduction material 24 electrically to connect
It ties to the first circuit layer 13 of the substrate 10.
Step S4：With reference to Fig. 5, cover an insulating layer 30 on the first face 11 of the substrate 10, wherein the insulating layer 30 into
One step fills up each rectilinear chip 20 and is embedded in gap left in each first blind hole 14.
Step S5：With reference to Fig. 6, a drilling via formations at least third blind hole 31 and at least one the 4th blind hole on the insulating layer 30
32, wherein each third blind hole 31 is each passed through 30 thickness of insulating layer and is connected to the first of corresponding each rectilinear chip 20
Each brilliant pad 21a set by surface 21, wherein each 4th blind hole 32 further can run through the insulation when Laser drill forms simultaneously
Layer 30 thickness and correspondence be connected to each second blind hole 15 being located on the substrate 10, enable each 4th blind hole 32 with it is corresponding
Each second blind hole 15 forms the integral type blind hole 32,15 of about one connection.
Step S6：With reference to Fig. 7, on the surface of the insulating layer 30 and each third blind hole 31, each 4th blind hole 32 and each the
One the second circuit layer 40 of production molding, makes to be located on the first surface 22 of each rectilinear chip 20 on the inner wall of two blind holes 15
Each brilliant pad 21a can be by first circuit in 40 with electrical connection of the second circuit layer to the second face 12 for being located at the substrate 10
Layer 13 so completes an encapsulating structure 1.
In addition, further may include a step S7：The outer jacket 50 is covered entirely if an outer jacket 50 with reference to Fig. 2
Be located in the second circuit layer 40 and fill up each third blind hole 31, each 4th blind hole 32 and each second blind hole 15 with protect this second
Circuit layer 40.
Referring again to Fig. 8 to Figure 12, a kind of embedded type encapsulating structure 1a of horizontal chip of the present embodiment system is mainly wrapped
Contain：One substrate 10, at least a horizontal chip 20a and an insulating layer 30a, wherein encapsulating structure 1a utilizes a larger face of tool
Long-pending substrate 10 with synchronize complete one with multiple encapsulating structures 1 (daughter) sheet parent 2a (as shown in Figure 8), then
Sheet parent 2a is carried out being cut to multiple encapsulating structure 1a (daughter) but is not limited.
The substrate 10 has one first face 11 and one second opposite face 12, and wherein molding is equipped with one the on second face 12
One circuit layer 13.The present embodiment is blind to form at least one first on the first face 11 of the substrate 10 using Laser drill technology
Hole 14, the present embodiment system as shown in Fig. 8 to Figure 12 illustrate by taking one first blind hole 14 as an example but do not limit.Each first blind hole 14 is distinguished
The inner face of the first circuit layer 13 is connected to across 10 thickness of substrate by first face 11, wherein the depth of each first blind hole 14
Degree is designed to be approximately equal to the thickness of the horizontal chip 20.
Each horizontal chip 20a has at least two brilliant pads 21 such as brilliant pad 21a, 21b comprising positive and negative electrode but does not limit, and
It is separately located on the second surface 23 of each horizontal chip 20；Each horizontal chip 20a is embedded in the corresponding of the substrate 10
In each first blind hole 14, wherein the depth system of each first blind hole 14 is designed to be approximately equal to the thickness of each horizontal chip 20a.Respectively
At least two set brilliant pads 21 (21a, 21b) rely on conduction material 24 such as tin ball respectively on the second surface 23 of horizontal chip 20a
Or elargol but do not limit, it forms positive and negative anodes to be separately electrically connected to the first circuit layer 13 of the substrate 10 and shape is separately connected
State.
The manufacturing method of the embedded type encapsulating structure 1a of the horizontal chip 20a of the present embodiment, comprises the steps of：
Step S1：With reference to Figure 10, a substrate 10 is provided, there is one first face 11 and one second opposite face 12, wherein
Second face 12 is equipped with a first circuit layer 13 (but including at least two points of circuits opened), and in the first face 11 of the substrate 10
Upper drilling via formations at least one first blind hole 14, wherein each first blind hole 14 be each passed through 10 thickness of substrate and be connected to this
One circuit layer 13.
Step S2：With reference to Figure 11, at least horizontal chip a 20a, each horizontal chip 20a is provided and is equipped at least two brilliant pads
It 21 and is dividually located on the second surface 12 of horizontal chip 20a.
Step S3：With reference to Figure 11, each horizontal chip 20a is respectively embedded into corresponding each first blind hole 14, and
Make to be located at each brilliant pad 21 on second surface 12 respectively by conduction material with dividually electrical connection (weldering knot) to the substrate 10
In first circuit layer 13 at least two points of circuits opened.
Step S4：Insulating layer 30a is covered on the first face 11 of the substrate 10 if an insulating layer 30a with reference to Figure 12
And fill up each horizontal chip 20a and be embedded in gap left in each first blind hole 14, and complete a horizontal chip 20a's
Embedded type encapsulating structure 1a.
The rectilinear chip 20 of the utility model or embedded type encapsulating structure 1, the 1a of horizontal chip 20a, with this field
Background technique compare, at least following advantages：
(1) each rectilinear chip 20 or horizontal chip 20a are embedded in corresponding each first blind hole 14 of the substrate 10
It is interior, and the depth of each first blind hole 14 is designed to be approximately equal to the thickness of the rectilinear chip 20 or horizontal chip 20a, therefore really
It can be reduced the thickness of the encapsulating structure 1,1a in fact.
(2) the rectilinear chip 20 of the utility model is built-in in substrate 10 (printed circuit board), and blind by each 4th
Hole 32 and corresponding each second blind hole 15 are formed by integral type blind hole 32,15 and are molded over around the rectilinear chip 20
On external substrate 10, therefore 1 system of encapsulating structure of the utility model forms a rectilinear chip 20 and is embedded in (the printing electricity of substrate 10
Road plate) in fan-out-type (FOiP, Fan-Out in PCB) encapsulating structure kenel, so reach thickness be greatly decreased, processing procedure phase
To simplified advantage, this is that the prior art can not be reached.
(3) each blind hole 14, each second blind hole 15, third blind hole 31, each 4th blind hole 32, Yi Jiyou of the utility model
Each 4th blind hole 32 is formed by integral type blind hole 32,15 with corresponding each second blind hole 15, all utilizes Laser drill technology
It is formed, therefore can simplify the processing procedure of each blind hole in the encapsulating structure 1.
(4) the second circuit layer 40 is formed on the surface for being located at the insulating layer 30 and the third blind hole using electroplating technology
31, on the inner wall of each 4th blind hole 32 and corresponding each second blind hole 15, therefore conductive reliability can effectively be promoted.
It is described above to be merely exemplary for the utility model, and not restrictive, those of ordinary skill in the art
Understand, without departing from the spirit and scope defined by the claims, can many modifications may be made, variation or it is equivalent, but
It falls within the protection scope of the utility model.
Claims (5)
1. a kind of embedded type encapsulating structure of rectilinear chip, it is characterized in that comprising：
One substrate has one first face and one second opposite face, wherein a first circuit layer is equipped on second face,
Drilling via formations at least one first blind hole and at least one second blind hole on first face of the substrate, wherein each first blind hole and each second
Blind hole passes through the substrate thickness by first face respectively and is connected to the first circuit layer；
At least one rectilinear chip, each rectilinear chip have at least two brilliant pads, and wherein at least one brilliant pad is located at each rectilinear crystalline substance
On one first surface of piece, and other at least one brilliant pads are located on opposite second surface, each rectilinear chip be embedded in pair
In each first blind hole answered, and making to set each brilliant pad on a second surface can rely on conduction material with electrical connection to the of the substrate
One circuit layer；
One insulating layer is covered on the first face of the substrate, and on which insulating layer a drilling via formations at least third blind hole and
At least one the 4th blind hole；Wherein each third blind hole is connected to the first surface of the rectilinear chip across the thickness of insulating layer；
Wherein each 4th blind hole is through the thickness of insulating layer and correspondence is connected to each second blind hole set on the substrate, makes each 4th blind
Hole can form about the one integral type blind hole being connected to corresponding each second blind hole；
One the second circuit layer, is molded on the surface of the insulating layer and each third blind hole, each 4th using electroplating technology
On the inner wall of blind hole and each second blind hole, make to be located at each brilliant pad on the first surface of the rectilinear chip can rely on this second
Circuit layer with electrical connection is to the first circuit layer.
2. the embedded type encapsulating structure of rectilinear chip as described in claim 1, it is characterised in that：The insulating layer is further filled out
Full each rectilinear chip is embedded in gap left in each first blind hole.
3. the embedded type encapsulating structure of rectilinear chip as described in claim 1, it is characterised in that：It also include an outer jacket,
The outer jacket is covered in the second circuit layer and fills up each third blind hole, each 4th blind hole and each second blind hole.
4. the embedded type encapsulating structure of rectilinear chip as described in claim 1, it is characterised in that：First blind hole of the substrate
Depth be equal to the rectilinear chip thickness.
5. a kind of embedded type encapsulating structure of horizontal chip, it is characterized in that comprising：
One substrate has one first face and one second opposite face, a first circuit layer is equipped on second face, in the base
Drilling via formations at least one first blind hole on first face of plate, wherein each first blind hole passes through the substrate thickness by first face respectively
And it is connected to the first circuit layer；
An at least horizontal chip has at least two brilliant pads, which is separately located at the one the of the horizontal chip
On two surfaces, wherein each horizontal chip is embedded in corresponding each first blind hole, and make to set each crystalline substance on a second surface
Pad can dividually be electrically connected to the first circuit layer of the substrate by conduction material respectively；
One insulating layer is covered on the first face of the substrate and fills up each horizontal chip and be embedded in each first blind hole and stayed
Under gap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820221036.6U CN208127143U (en) | 2018-02-07 | 2018-02-07 | The embedded type encapsulating structure of rectilinear chip and horizontal chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820221036.6U CN208127143U (en) | 2018-02-07 | 2018-02-07 | The embedded type encapsulating structure of rectilinear chip and horizontal chip |
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| Publication Number | Publication Date |
|---|---|
| CN208127143U true CN208127143U (en) | 2018-11-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201820221036.6U Withdrawn - After Issue CN208127143U (en) | 2018-02-07 | 2018-02-07 | The embedded type encapsulating structure of rectilinear chip and horizontal chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120353A (en) * | 2018-02-07 | 2019-08-13 | 茂邦电子有限公司 | The embedded type encapsulating structure and its manufacturing method of rectilinear chip and horizontal chip |
-
2018
- 2018-02-07 CN CN201820221036.6U patent/CN208127143U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120353A (en) * | 2018-02-07 | 2019-08-13 | 茂邦电子有限公司 | The embedded type encapsulating structure and its manufacturing method of rectilinear chip and horizontal chip |
| CN110120353B (en) * | 2018-02-07 | 2023-07-18 | 讯忆科技股份有限公司 | Embedded packaging structure of vertical wafer and horizontal wafer and manufacturing method thereof |
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