CN208111453U - A kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer - Google Patents
A kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer Download PDFInfo
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- CN208111453U CN208111453U CN201820607103.8U CN201820607103U CN208111453U CN 208111453 U CN208111453 U CN 208111453U CN 201820607103 U CN201820607103 U CN 201820607103U CN 208111453 U CN208111453 U CN 208111453U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The utility model provides a kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, belongs to technical field of solar.It solves the problems, such as that existing polysilicon chip performance is not sufficiently stable.This boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer; including wafer bulk; wafer bulk successively includes polyvinyl fluoride composite membrane, N-type silicon chip, P-type wafer and toughened glass layer from lower to upper; P-type wafer has been co-doped with boron gallium; and the side of P-type wafer is connected with first electrode, the side of N-type silicon chip is connected with second electrode, and the outer periphery of wafer bulk is provided with protecting border; first electrode and second electrode are vertically interspersed on protecting border, and first electrode is located at the surface of second electrode.Protecting border set by it can protect wafer bulk, avoid damage of being collided with, while can carry out auxiliary positioning to first electrode and second electrode, so that wiring is more convenient, when installation is time saving and energy saving.
Description
Technical field
The utility model belongs to technical field of solar, is related to a kind of solar energy polycrystalline silicon sheet, and especially a kind of boron gallium is total
Mix p-type high-efficiency polycrystalline silicon wafer.
Background technique
Currently, the silicon wafer of production polysilicon solar cell is made by polycrystal silicon ingot is processed, in order to meet cell piece
The requirement on electric performance of processing, polycrystal silicon ingot must adjust the concentration of dopant in crystal growing process.Existing dopant master
To include boron, phosphorus and gallium, but use single boron or gallium mostly, and structure is also not ideal enough, in performance or there is
It is insufficient.
Summary of the invention
The purpose of this utility model is the presence of the above problem in view of the prior art, and it is high to propose a kind of boron and gallium co-doped p-type
Polysilicon chip is imitated, the technical problem to be solved is that the performances for how guaranteeing solar energy polycrystalline silicon sheet for it.
The purpose of this utility model can be realized by the following technical scheme：A kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer,
Including wafer bulk, which is characterized in that the wafer bulk is plate-like, and from lower to upper successively includes polyvinyl fluoride composite membrane, N
Type silicon wafer, P-type wafer and toughened glass layer, the toughened glass layer are connected on the top surface of P-type wafer by EVA colloidal sol, institute
It states polyvinyl fluoride composite membrane to be connected on the bottom surface of N-type silicon chip by EVA colloidal sol, the P-type wafer has been co-doped with boron gallium, and p-type
The side of silicon wafer is connected with first electrode, and the side of the N-type silicon chip is connected with second electrode, the outer periphery of the wafer bulk
It is provided with protecting border, the first electrode and second electrode are vertically interspersed on protecting border, and the first electrode position
In the surface of second electrode.
Sunlight is radiated at P-type wafer surface, forms electrons and holes pair, under the action of P-N junction electric field, hole on surface
N-type silicon chip is flowed to by P-type wafer, electronics flows to P-type wafer by N-type silicon chip, and passes through first electrode and second electrode output electricity
Stream, after this polysilicon chip adulterates boron and gallium element simultaneously in P-type wafer, efficiency is higher；Protecting border, can be to silicon wafer master
Body is protected, and damage of being collided with is avoided, while can carry out auxiliary positioning to first electrode and second electrode, so that wiring is more
Add conveniently, when installation is time saving and energy saving.
In above-mentioned boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, the electron concentration of silicon is 10 in the P-type wafer-18cm3
The order of magnitude.10-18cm3The P-type wafer of the order of magnitude is better than common P after mixed with boron gallium in terms of electrons and holes movement speed
Type silicon and electron concentration is easily achieved no longer needs to that groove or shrinkage pool is arranged on surface using the P-type wafer after this order of magnitude,
Structure is simpler, and efficiency is higher.
In above-mentioned boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, the protecting border is rectangle frame, including frame bar one, frame
Bar two, frame bar three and frame bar four, the left end of the frame bar two are connected in the upper end of frame bar one, and the left end of the frame bar four is connected in
The upper end of the lower end of frame bar two, the frame bar three is detachably connected on the right end of frame bar two, and the lower end of frame bar three detachably connects
The right end in frame bar four is connect, the frame bar three has for interting the first positioning hole of first electrode and for interting second electrode
Second location hole.Connect it is more convenient, simultaneously because the structure of each frame bar and mutual connection type are different, identification
Degree is high, is not easy to obscure.
In above-mentioned boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, the upper end left wall face of the frame bar three, which has, to be used for and frame
The first connection-peg that bar two plugs, the lower end left wall face of the frame bar three have the second grafting for plugging with frame bar four
Head.Inserting mode sound construction, it is easy to operate.
In above-mentioned boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, fastener and frame bar two and frame bar are crossed in the frame bar threeway
Four are detachably connected.Fastener is bolt or positioning pin.
In above-mentioned boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, sea is provided between the wafer bulk and protecting border
Continuous washer, the inner wall of the sponge washer have the locating slot one for being embedded in wafer bulk, the inner wall of the protecting border
With locating slot two, the outside wall surface of the sponge washer, which has, to be outwardly protruded and for being embedded the circular orientation in locating slot two
Portion.Cooperate closely between wafer bulk and sponge washer, sponge washer and protecting border, is not easy to loosen.
In above-mentioned boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, the bottom surface of the polyvinyl fluoride composite membrane is plane, and poly-
The bottom surface surrounding edge of fluoride composite film is resisted against in locating slot one.The bottom surface of polyvinyl fluoride composite membrane, i.e. wafer bulk
There are gaps between bottom surface and the bottom surface of sponge washer and protecting border, prevent plowing from.
In above-mentioned boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, the protecting border is made of aluminum alloy materials, and protects
The quadrangle of frame is made as fillet.Avoid colliding with and caused by damage.
Compared with prior art, the utility model has the following advantages that：
1, this polysilicon chip in P-type wafer simultaneously adulterate boron and gallium element after, and in P-type wafer silicon electron concentration
10-18cm3The order of magnitude, efficiency are higher；
2, this polysilicon chip can not only avoid polysilicon chip impaired by setting protecting border, while can also be to defeated
Electrode out carries out positioning and further protection, furthermore the bottom surface of polysilicon chip by protecting border frame it is high after, without setting again
Protective film is set, cost is lower.
Detailed description of the invention
Fig. 1 is the overlooking structure figure of the utility model.
Fig. 2 is the decomposition texture schematic diagram of the utility model.
Fig. 3 is the cross section structure schematic diagram of the utility model.
Fig. 4 is enlarged drawing at A in Fig. 3.
In figure, 1, wafer bulk；2, protecting border；21, frame bar one；22, frame bar two；23, frame bar three；231, the first positioning
Hole；232, second location hole；233, the first connection-peg；234, the second connection-peg；24, frame bar four；25, locating slot two；3, sponge
Washer；31, locating slot one；4, polyvinyl fluoride composite membrane；5, N-type silicon chip；6, P-type wafer；7, toughened glass layer；8, the first electricity
Pole；9, second electrode.
Specific embodiment
It is specific embodiment of the utility model and in conjunction with attached drawing below, the technical solution of the utility model is made further
Description, but the utility model is not limited to these examples.
- Fig. 4 referring to Fig.1, the present embodiment are a kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, including wafer bulk 1, silicon wafer
Main body 1 is plate-like, and from lower to upper successively include polyvinyl fluoride composite membrane 4, N-type silicon chip 5, P-type wafer 6 and toughened glass layer 7,
Toughened glass layer 7 is connected on the top surface of P-type wafer 6 by EVA colloidal sol, and polyvinyl fluoride composite membrane 4 is connected in by EVA colloidal sol
On the bottom surface of N-type silicon chip 5, P-type wafer 6 has been co-doped with boron gallium, and in P-type wafer 6 silicon electron concentration 10-18cm3The order of magnitude.
The side of P-type wafer 6 is connected with first electrode 8, and the side of N-type silicon chip 5 is connected with second electrode 9, wafer bulk 1
Outer periphery be provided with protecting border 2, first electrode 8 and second electrode 9 are vertically interspersed on protecting border 2, and first electricity
Pole 8 is located at the surface of second electrode 9.Protecting border 2 is rectangle frame, including frame bar 1, frame bar 2 22, frame bar 3 23 and frame
Bar 4 24, the left end of frame bar 2 22 are connected in the upper end of frame bar 1, and the left end of frame bar 4 24 is connected in the lower end of frame bar 2 22,
The upper end of frame bar 3 23 is detachably connected on the right end of frame bar 2 22, and the lower end of frame bar 3 23 is detachably connected on frame bar 4 24
Right end, frame bar 3 23 have for interting the first positioning hole 231 of first electrode 8 and for interting second electrode 9 second
Location hole 232, the upper end left wall face of frame bar 3 23 have the first connection-peg 233 for plugging with frame bar 2 22, frame bar three
23 lower end left wall face has the second connection-peg 234 for plugging with frame bar 4 24.
In addition, frame bar 3 23 is detachably connected by fastener with frame bar 2 22 and frame bar 4 24, fastener is to be interspersed in
The positioning pin or bolt of 3 23 end of frame bar.
Sponge washer 3 is provided between wafer bulk 1 and protecting border 2, the inner wall of sponge washer 3 has for being embedded in
The locating slot 1 of wafer bulk 1, the inner wall of protecting border 2 have locating slot 2 25, and the outside wall surface of sponge washer 3 has outside
It protrudes and is used to be embedded the circular orientation portion in locating slot 2 25, the lateral wall of the top and bottom of sponge washer 3 supports respectively
On the inner wall for leaning against protecting border 2, and the top surface of sponge washer 3 and the top surface of protecting border 2 are flush, sponge washer 3
Bottom surface and the bottom surface of protecting border 2 are flush.The bottom surface of polyvinyl fluoride composite membrane 4 is plane, and the bottom of polyvinyl fluoride composite membrane 4
Face surrounding edge is resisted against in locating slot 1, and protecting border 2 is made of aluminum alloy materials, and the quadrangle of protecting border 2 is made as
Fillet, between the bottom surface of polyvinyl fluoride composite membrane 4, the i.e. bottom surface of wafer bulk 1 and sponge washer 3 and the bottom surface of protecting border 2
There are gaps, prevent plowing from.
The specific embodiments described herein are merely examples of the spirit of the present invention.The utility model institute
Belonging to those skilled in the art can make various modifications or additions to the described embodiments or using similar
Mode substitute, but without departing from the spirit of the present application or beyond the scope of the appended claims.
Claims (8)
1. a kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer, including wafer bulk (1), which is characterized in that the wafer bulk (1)
It is plate-like, and from lower to upper successively include polyvinyl fluoride composite membrane (4), N-type silicon chip (5), P-type wafer (6) and toughened glass layer
(7), the toughened glass layer (7) is connected on the top surface of P-type wafer (6) by EVA colloidal sol, the polyvinyl fluoride composite membrane
(4) it is connected in by EVA colloidal sol on the bottom surface of N-type silicon chip (5), the P-type wafer (6) has been co-doped with boron gallium, and P-type wafer (6)
Side be connected with first electrode (8), the side of the N-type silicon chip (5) is connected with second electrode (9), the wafer bulk (1)
Outer periphery be provided with protecting border (2), the first electrode (8) and second electrode (9) are vertically interspersed in protecting border (2)
On, and the first electrode (8) is located at the surface of second electrode (9).
2. boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer according to claim 1, which is characterized in that in the P-type wafer (6)
The electron concentration of silicon is 10-18cm3The order of magnitude.
3. boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer according to claim 1, which is characterized in that the protecting border (2) is
Rectangle frame, including frame bar one (21), frame bar two (22), frame bar three (23) and frame bar four (24), the left end of the frame bar two (22)
It is connected in the upper end of frame bar one (21), the left end of the frame bar four (24) is connected in the lower end of frame bar two (22), the frame bar three
(23) upper end is detachably connected on the right end of frame bar two (22), and the lower end of frame bar three (23) is detachably connected on frame bar four
(24) right end, the frame bar three (23) have first positioning hole (231) for interting first electrode (8) and for interting the
The second location hole (232) of two electrodes (9).
4. boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer according to claim 3, which is characterized in that the frame bar three (23)
Upper end left wall face has the first connection-peg (233) for plugging with frame bar two (22), and the lower end of the frame bar three (23) is left
Wall surface has the second connection-peg (234) for plugging with frame bar four (24).
5. boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer according to claim 3, which is characterized in that the frame bar three (23) is logical
Fastener is crossed to be detachably connected with frame bar two (22) and frame bar four (24).
6. boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer according to claim 1, which is characterized in that the wafer bulk (1) and
It is provided between protecting border (2) sponge washer (3), the inner wall of the sponge washer (3) has for being embedded in wafer bulk
(1) inner wall of locating slot one (31), the protecting border (2) has locating slot two (25), the outer wall of the sponge washer (3)
Mask is outwardly convex out and for being embedded the circular orientation portion in locating slot two (25).
7. boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer according to claim 6, which is characterized in that the polyvinyl fluoride is compound
The bottom surface of film (4) is plane, and the bottom surface surrounding edge of polyvinyl fluoride composite membrane (4) is resisted against in locating slot one (31).
8. boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer according to claim 7, which is characterized in that the protecting border (2) by
Aluminum alloy materials are made, and the quadrangle of protecting border (2) is made as fillet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820607103.8U CN208111453U (en) | 2018-04-25 | 2018-04-25 | A kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820607103.8U CN208111453U (en) | 2018-04-25 | 2018-04-25 | A kind of boron and gallium co-doped p-type high-efficiency polycrystalline silicon wafer |
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| Publication Number | Publication Date |
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| CN208111453U true CN208111453U (en) | 2018-11-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628711A (en) * | 2020-06-05 | 2020-09-04 | 南京中清华峰智能科技有限公司 | Outer packet mode sealing protection mechanism of photovoltaic power generation solar panel outer edge |
-
2018
- 2018-04-25 CN CN201820607103.8U patent/CN208111453U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111628711A (en) * | 2020-06-05 | 2020-09-04 | 南京中清华峰智能科技有限公司 | Outer packet mode sealing protection mechanism of photovoltaic power generation solar panel outer edge |
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