CN208111431U - A kind of chip-packaging structure - Google Patents

Abstract

The utility model embodiment discloses a kind of chip-packaging structure, including substrate, and the chip positioned at the upper surface of the substrate, the lower surface of the chip is electrically coupled by the upper surface of multiple pins and the substrate, the multiple pin includes the second pin positioned at first pin in the middle position of the chip lower surface and positioned at the chip lower surface edge, the second pin extends at least part of the chip sides, and the gap between the multiple pin can be with cabling.By the way that the side of chip will be extended to close to the pin of chip edge, the connection of chip and substrate edges can be reinforced, to avoid the problem that due to occurring being located at the pin of chip edge and substrate disconnection when substrate is bent.

Description

A kind of chip-packaging structure

Technical field

The utility model relates to chip technology fields, relate more specifically to a kind of chip-packaging structure.

Background technique

In information age today, with the fast development of electronics industry, the products such as computer, mobile phone are become increasingly popular. People are more and more to the functional requirement of electronic product, more and more stronger to performance requirement, and volume requirement is smaller and smaller, weight It is required that more and more lighter.This just promotes electronic product to develop to multi-functional, high-performance and miniaturization, lightness direction.To realize this The characteristic size of one target, IC chip will be smaller and smaller, and complexity is continuously increased, and then, the I/O number of circuit will be more next More, the I/O density of encapsulation will be continuously increased.In order to adapt to this demand for development, some advanced High Density Packaging Technologies It comes into being, welded ball array encapsulation technology is exactly one of them.The chip package element of design of electronic products, through frequently with soldered ball Array package (Ball Grid Array, BGA), as shown in Figure 1, it is made in the upper surface of the substrate 930 of packaging body 900 I/O end and printed wiring board 910 (PCB) mutual connection of the array pin 920 as circuit.The element of BGA package have it is small in size, draw Advantage more than foot can adapt to the demand for development of present chip package.

But in bga structure, pin 920 be it is spherical, substrate 930 and IC chip 910 are electrically coupled, pin 920 and The contact surface very little of substrate 930, chip 910, even a point.It has in transport road and inevitably jolts, make thin The substrate of type bends, and the pin 920 connecting positioned at 930 edge of substrate with substrate 930 may be bent because of substrate 930 The connection of generated power and substrate 930 disconnects, so that solder crack phenomenon occur.The prior art can increase after the completion of piece factory piece The step of adding one of dispensing.And dispensing will increase product cost and time cost.

Therefore, for welded ball array encapsulation technology, reinforced by the way of easy pin positioned at substrate edges with The binding force of substrate is vital.

Utility model content

The problems solved by the utility model are to provide a kind of chip-packaging structure, by will drawing close to chip edge Foot extends to the side of chip, can reinforce the connection of chip and substrate edges, to avoid being located at chip since substrate is bent The pin and substrate at edge disconnect.

According to a kind of chip-packaging structure provided by the embodiment of the utility model, including：Substrate；Chip is located at the base The lower surface of the upper surface of plate, the chip is electrically coupled by the upper surface of multiple pins and the substrate, the multiple pin Including being located at first pin in chip lower surface middle position and being located at the every adjacent two edges edge in the chip lower surface The second pin of intersection, first pin are the ball-like pins of multiple array distributions, and the second pin is by the intersection Place extends to corresponding two sides in the intersection, each adjacent two pin of the multiple pin in the chip lower surface The spacing at edge remains unchanged.Preferably, the chip-packaging structure further includes third pin, positioned at the chip lower surface Edge, the third pin extend at least part of the chip sides.

Preferably, the third pin extends close to the corresponding side surface of the chip lower surface edge.

Preferably, mutually flat close to the extending direction of multiple third pins of the same side in chip lower surface Row.

Preferably, the third pin and the second pin surround first pin.

Preferably, the chip-packaging structure further includes：It is close to be located at the chip sides for 4th pin, the 4th pin The position of the chip lower surface edge, the 4th pin and the second pin surround first pin.

Preferably, the chip-packaging structure further includes：4th pin is located at the chip sides close under the chip The position of marginal surface, the 4th pin, the third pin and the second pin surround first pin.It is preferred that Ground, the third pin are evenly distributed on position of the chip with respect to two edges, and the 4th pin is evenly distributed on described Position of the chip sides close in addition opposite two edges.

Preferably, the third pin and the 4th pin distribute alternately on the chip sides and lower surface side Edge.

Preferably, the 4th pin is QFP pin, and the 4th pin includes grounding pin.

According in the chip-packaging structure of the utility model embodiment, the pin between substrate and chip includes first Pin, third pin and second pin, the first pin are located at the middle position of chip lower surface, and third pin and second are drawn Foot is located at the marginal position of chip lower surface, and third pin and second pin surround the first pin.Due to second pin, Third pin extends to the side of substrate, will not influence chip wiring function, while increasing the contact surface of pin and tin cream, side Tin cream on the contact surface and substrate in face, which is combined closely, can reinforce the binding force of second pin, third pin and substrate, can be with Effective the distance between control base board and chip are avoided being bent the pin for being located at chip edge due to substrate and substrate disconnect, So as to reinforce the binding force of chip and substrate, effectively mitigate soldered elements deviate, fall, missing solder the problems such as, to improve The stability and reliability of integrated chip.

Preferably, at least one side of chip is equipped with the 4th pin of multiple QFP encapsulation, fixed function is played, when substrate is curved Qu Shi, the 4th pin hold on to substrate, guarantee that the first pin, second pin and third pin are contacted with substrates into intimate, no Solder crack is led to the problem of, the gap between chip and substrate is effectively controlled, enhances welding quality.

Detailed description of the invention

By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model , feature and advantage will be apparent from.

Fig. 1 shows the perspective view of the chip-packaging structure of the prior art；

Fig. 2 shows the chip-packaging structure top views of the utility model；

Fig. 3 be according to fig. 2 shown in the position A-A sectional view；

Fig. 4 shows the perspective view that the utility model first embodiment chip-packaging structure omits substrate；

Fig. 5 shows the top view that the utility model first embodiment chip-packaging structure omits substrate；

Fig. 6 shows the top view that the utility model second embodiment chip-packaging structure omits substrate；

Fig. 7 shows the top view that the utility model 3rd embodiment chip-packaging structure omits substrate.

Specific embodiment

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Appended drawing reference indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.In addition, may in figure Certain well known parts are not shown.

Many specific details of the utility model, such as the structure of component, material, size, place are described hereinafter Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

It should be appreciated that being known as being located at another floor, another area when by a floor, a region when describing the structure of component When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also comprising other layers or region between a region.Also, if by part turnover, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

Fig. 2 shows the chip-packaging structure top view of the utility model, Fig. 3 shows the chip-packaging structure of the utility model Sectional view, wherein Fig. 3 be according to fig. 2 shown in the position A-A sectional view.

Referring to figure 2. and Fig. 3, the chip-packaging structure of the utility model includes substrate 100, chip 200 and multiple draws Foot 300.Wherein, chip 200 is located on substrate 100, is electrically coupled by multiple pins 300 with substrate 100.Substrate 100 can be in Cube structure, and substrate 100 can be thin base.

Fig. 4 shows the perspective view that the utility model first embodiment chip-packaging structure omits substrate,

Fig. 5 shows the top view that the utility model first embodiment chip-packaging structure omits substrate.

Referring to figure 4. and Fig. 5, multiple pins 300 of the chip-packaging structure 400 in the utility model first embodiment wrap Include the first pin 310, third pin 330 and second pin 320.First pin 310 is located at 200 lower surface of chip, further Ground, the first pin 310 are located at the middle position of 200 lower surface of chip.First pin 310 can be the spherical of multiple array distributions Pin forms welded ball array encapsulating structure (BGA).First pin 310 can be soldered ball.

Second pin 320 is located in 200 lower surface four edges edge of chip per the position of adjacent two edges intersection, and second Pin 320 coats intersection, and from the intersection at two edges to the side of corresponding two sides in the two of intersection edges To extension pin.Since two sides that second pin 320 intersects to 200 lower surface edge of chip simultaneously extend, so as to Further strengthen the binding force of 200 edge of chip especially chip 200 edges and corners and substrate 100.The quantity example of second pin 320 For example 4.Second pin 320 is for example made or copper nickel plating is made etc. by copper is tin plating.

Third pin 330 is located at the position close to edge of 200 lower surface of chip, and third pin 330 surrounds and is located at The first pin 310 among chip 200.In addition, third pin 330 extends at least part of 200 side of chip, further Ground, each third pin 330 extend respectively to the corresponding side surface close to 200 edge of chip, so that being located at 200 following table of chip Tin cream on the contact surface and substrate of 300 side of multiple pins at face edge is combined closely, so that chip 200 and substrate The binding force of frontside edge enhances.Extending direction close to multiple third pins 330 at same edge can be parallel to each other.Third Pin 330 is for example made or copper nickel plating is made etc. by copper is tin plating.

For example, when chip 200 is cube structure, such as Fig. 4 and Fig. 5, the first pin 310 of chip-packaging structure 400 The array distribution that can be arranged at 3 rows 6；Third pin 330 can surround the first pin 310, in the close phase in 200 lower surface of chip 6 are uniformly distributed to the position of two edges, is uniformly distributed 3 close to the position of in addition opposite two edges；Second pin 320 can be with Be located at 200 lower surface of chip close to 4 angles position.

When substrate 100 be it is slim, be prone to bending, substrate 100 after bending to be located at 100 upper surface of substrate chip The pin of 200 lower surface edges generates power, separates the pin positioned at 200 lower surface edge of chip with substrate 100.Second pin 320 extend to two sides of chip 200, and third pin 330 extends to the side of chip 200, therefore multiple pins 300 are in core The spacing of each adjacent two pin edge of 200 lower surface of piece does not change, and then will not influence chip wiring function, increases simultaneously The contact surface of pin and tin cream, further strengthens the binding force of 200 edge of chip especially chip 200 edges and corners and substrate, It effectively avoids being bent the pin for being located at chip edge due to substrate and substrate disconnects, effectively mitigate soldered elements and deviate, fall, is empty The problems such as weldering, to improve the stability and reliability of integrated chip.

Fig. 6 shows the top view that the utility model second embodiment chip-packaging structure omits substrate.

Fig. 6 is please referred to, multiple pins 300 of the chip-packaging structure 500 in the utility model second embodiment include the One pin 310, second pin 320 and the 4th pin 340.First pin 310, second pin 320 position in above-mentioned implementation It has been described in detail in example, details are not described herein again.

4th pin 340 is located at 200 side of chip close to the position of lower surface edge, and the 4th pin 340 surrounds position The first pin 310 among chip 200.4th pin 340 is QFP (quad flat package) pin, the 4th pin 340 packet Include grounding pin and fixed pin.4th pin, 340 to the first pin 310, second pin 320 and third pin 330 Tin ball bottom is slightly higher, and when chip is welded in substrate, tin ball melts, and chip weight itself pushes down tin ball and is lower, after welding, tin ball At elliptical shape ball, the height of tin ball and 340 height of the 4th pin be with high at this time, as long as with unbroken, the chip that reaches the 4th pin 340 Solder crack would not be generated with substrate to disconnect.And the 4th pin 340 is located at 200 side of chip close to the position of lower surface edge, So that the pin number of 200 lower surface of chip increases.

For example, when chip 200 is cube structure, such as Fig. 6, the first pin 310 of chip-packaging structure 500 can be at The array distribution of 5 rows 6 column；4th pin 340 can surround the first pin 310, in 200 side of chip close to lower surface edge The position of opposite two edges is uniformly distributed 6, is uniformly distributed 5 close to the position of in addition opposite two edges；Second pin 320 can Be located at 200 lower surface of chip close to 4 angles position.

Fig. 7 shows the top view that the utility model 3rd embodiment chip-packaging structure omits substrate.

Fig. 7 is please referred to, multiple pins 300 of the chip-packaging structure 600 in the utility model 3rd embodiment include the One pin 310, second pin 320, third pin 330 and the 4th pin 340.First pin 310, second pin 320, third The position of pin 330 and the 4th pin 340 has been described in detail in the above-described embodiments, and details are not described herein again.

For example, when chip 200 is cube structure, such as Fig. 7, the first pin 310 of chip-packaging structure 600 can be at The array distribution of 6 rows 5 column；4th pin 340 can surround the first pin 310, in 200 side of chip close to lower surface edge The position of opposite two edges is uniformly distributed 6；Third pin 330 can surround the first pin 310, close in addition opposite two edges Position be uniformly distributed 3；Second pin 320 can be located at 200 lower surface of chip close to the position at 4 angles.

In the present embodiment, 330 Relative distribution of the 4th pin 340 and third pin, it should be noted that the 4th pin 340 It with adjacent distributions or can also distribute alternately with third pin 330.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including the element.

It is as described above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe, Also not limiting the utility model is only the specific embodiment.Obviously, as described above, many modification and change can be made Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer With so that skilled artisan be enable to utilize the utility model and repairing on the basis of the utility model well Change use.The utility model is limited only by the claims and their full scope and equivalents.

Claims (10)

1. a kind of chip-packaging structure, including：

Substrate；

Chip, positioned at the upper surface of the substrate, the lower surface of the chip passes through the upper surface of multiple pins and the substrate It is electrically coupled,

The multiple pin includes positioned at first pin in chip lower surface middle position and positioned at the chip following table The second pin of face every adjacent two edges edge intersection, first pin are the ball-like pins of multiple array distributions, feature It is, the second pin extends to corresponding two sides in the intersection by the intersection, and the multiple pin is in institute The spacing for stating each adjacent two pin edge of chip lower surface remains unchanged.

2. chip-packaging structure according to claim 1, which is characterized in that further include：Third pin is located at the chip The edge of lower surface, the third pin extend at least part of the chip sides.

3. chip-packaging structure according to claim 2, which is characterized in that the third pin extends close to the core The corresponding side surface of piece lower surface edge.

4. chip-packaging structure according to claim 2, which is characterized in that close to the same side in chip lower surface The extending direction of multiple third pins is parallel to each other.

5. chip-packaging structure according to claim 2, which is characterized in that the third pin and the second pin are enclosed Around first pin.

6. chip-packaging structure according to claim 1, which is characterized in that further include：

4th pin, positioned at the chip sides close to the position of the chip lower surface edge, the 4th pin and described Second pin surrounds first pin.

7. chip-packaging structure according to claim 2, which is characterized in that further include：

4th pin, positioned at the chip sides close to the position of the chip lower surface edge, the 4th pin, described Three pins and the second pin surround first pin.

8. chip-packaging structure according to claim 7, which is characterized in that the third pin is evenly distributed on the core For piece with respect to the position of two edges, it is close in addition with respect to the position of two edges that the 4th pin is evenly distributed on the chip sides It sets.

9. chip-packaging structure according to claim 7, which is characterized in that the third pin and the 4th pin phase Between be distributed in the chip sides and lower surface edge.

10. chip-packaging structure according to claim 6 or 7, which is characterized in that the 4th pin is QFP pin, institute Stating the 4th pin includes grounding pin.