CN208076706U

CN208076706U - Relatively prime frequency sampling probability measures the circuit of electronic signal phase difference

Info

Publication number: CN208076706U
Application number: CN201820637419.1U
Authority: CN
Inventors: 焦杰; 李卫国; 赵虢睿; 秦志江; 王萍
Original assignee: Jilin Institute Of Radio And Television (scientific And Technological Information Center Jilin Bureau Of Press Publication Radio Film And Television)
Current assignee: Jilin Provincial Radio and Television Research Institute Technology Development Co.; Jilin Radio And Television Research Institute (science And Technology Information Center Of Jilin Radio And Television Bureau)
Priority date: 2018-04-28
Filing date: 2018-04-28
Publication date: 2018-11-09
Anticipated expiration: 2028-04-28

Abstract

Relatively prime frequency sampling probability measures the circuit of electronic signal phase difference, is related to electronic technology and field of broadcast televisions, solves the problems such as circuit is complicated and inaccurate when existing method measures high-frequency signal, including the first signal input part, second signal input terminal, sampling clock input terminal, first sampler, second sampler differs counter, counter of sampling, output register, digital comparator, the positive B of A are instead and logic gate, count upper-limit value input and OUT output ends；The utility model uses the sampled signal relatively prime with frequency input signal, the method for calculating probability that can directly obtain the phase difference of two homogenous frequency signals, and the digitized phase for directly obtaining specified physical unit is poor, has the good linearity and precision.The utility model does not need agc circuit, does not need the complex components such as multiplier, so circuit is very simple, with the relatively low digital circuit of cost or the microcontroller of hardware multiplier can not obtain preferable measurement effect yet.

Description

Relatively prime frequency sampling probability measures the circuit of electronic signal phase difference

Technical field

The utility model is related to electronic technology and field of broadcast televisions, and in particular to a kind of relatively prime frequency sampling probability measurement The device and method of electronic signal phase difference；With this technology, radio signal interferometer can be designed, for measuring broadcast Orientation where the radio emitting sources such as television transmitter.

Background technology

Largely there is illegal black appliances platform in each main cities at home in recent years, pretend to be the legal media of country, mainly from the leave of absence Medicine publicizes.In order to effectively supervise radio and television and radio environment, its black appliances platform unlawful activities is hit, needs to monitor radio and television The legitimacy of program, and measurement and positioning pirate radio.This will use one kind that can measure radio emitting source direction Radio signal interferometer, principle is exactly to calculate the direction where information source by measuring the phase difference of radio signal Angle.

The phase difference main method for measuring radio signal at present is the time difference for measuring two signals at zero crossing, then Become phase difference according to frequency conversion.In actual circuit, because Signal averaging noise or being interfered or circuit distortion Zero passage point moment is caused to be inaccurate.It being limited by circuit count clock frequency, the precision that this method measures high-frequency signal is not high, It is only applicable to low frequency signal measurement.

Also two signal multiplications of analog multiplier pair is used to filter again later, measures DC component and two in product signal At cosine function relationship between a signal, or measurement amplitude after signal is added and subtracted.This type method is needed with agc circuit input Signal becomes the signal of same-amplitude, there is linear bad, precision deficiency, the higher problem of cost.

Utility model content

Circuit when existing method measures high-frequency signal is complicated and phase difference precision is low and surveys in order to solve for the utility model The problems such as cost is larger is measured, the circuit that relatively prime frequency sampling probability measures electronic signal phase difference is provided.

Relatively prime frequency sampling probability measures the circuit of electronic signal phase difference, including the first signal input part, second signal Input terminal, sampling clock input terminal, the first sampler, the second sampler, difference counter, sampling counter, output register, The positive B of digital comparator, A instead with logic gate, count upper-limit value input and OUT output ends；

The ends D of first signal input part and the first sampler electrically connect, second signal input terminal and the second sampler The ends D electrically connect, the ends Q and the positive B of A of the first sampler are instead electrically connected with the positive input terminal of logic gate, the ends Q of the second sampler with The positive B of A are instead electrically connected with the negative input end of logic gate, the positive B of A instead with the output end of logic gate and the synchronous enabled end for differing counter It electrically connects；The output end and the input terminal of output register of the difference counter electrically connect, the output end of output register with OUT output ends electrically connect；

The X input terminals of the count upper-limit value input and digital comparator electrically connect, the output end for counter of sampling It is electrically connected with the Y input terminals of digital comparator；

The output end of the digital comparator simultaneously with the synchronous clear terminal of difference counter, sampling counter synchronize it is clear Zero end and the synchronous enabled end of output register electrically connect；

Input end of clock, the phasemeter of the input end of clock of sampling clock input terminal and the first sampler, the second sampler The input end of clock of number device, the input end of clock of counter of sampling, the input end of clock of output register electrically connect.

The beneficial effects of the utility model：Measuring circuit provided by the utility model can directly be sampled with low frequency signal and be surveyed High-frequency signal is measured, the digitlization difference numerical value of specified physical unit is directly obtained, is well suited for measuring small phase difference, measurement accuracy Height, the linearity is good, strong antijamming capability.Because the utility model does not need agc circuit, the complicated member such as multiplier is not needed yet Part can be obtained preferably so circuit is very simple with the relatively low digital circuit of cost or the not microcontroller of hardware multiplier Measurement effect.

Description of the drawings

Fig. 1 is the circuit logic diagram that relatively prime frequency sampling probability described in the utility model measures electronic signal phase difference.

Specific implementation mode

Specific implementation mode one, embodiment is described with reference to Fig. 1, and relatively prime frequency sampling probability measures electronic signal phase The circuit of difference designs circuit, above U1, U2, U3, U4, U5, U6 and U7 component using the CPLD chips of a piece of model EPM570 All it is the component of CPLD interior designs.The device includes the first signal input part IN1, second signal input terminal IN2, sampling clock Input terminal CP, the first sampler U1, the second sampler U2, difference counter U3, sampling counter U4, output register U5, number Be worth comparator U6, A positive B instead with logic gate U7, count upper-limit value input M1 and OUT output end；

The ends D of the first signal input part IN1 and the first sampler U1 electrically connect, second signal input terminal IN2 and The ends D of two sampler U2 electrically connect, and the positive input terminal of the ends Q of the first sampler U1 with the positive B of A instead with logic gate U7 electrically connects, and Negative input end of the ends Q of two sampler U2 with the positive B of A instead with logic gate U7 electrically connects, the positive B of A instead with the output end of logic gate U7 with The synchronous enabled end of difference counter U3 electrically connects；The input terminal of the output end and output register U5 of the difference counter U3 It electrically connects, output end and the OUT output ends of output register U5 electrically connect；

The X input terminals of the count upper-limit value input M1 and digital comparator U6 electrically connect, sampling counter U4's The Y input terminals of output end and digital comparator U6 electrically connect；

The output end of the digital comparator U6 simultaneously with the synchronous clear terminal of difference counter U3, sampling counter U4 The synchronous enabled end of synchronous clear terminal and output register U5 electrically connect；

The input end of clock of sampling clock input terminal CP and the first sampler U1, the second sampler U2 input end of clock, Differ the input end of clock electricity of the input end of clock of counter U3, the input end of clock of sampling counter U4, output register U5 Connection.

In present embodiment, the first sampler U1 and the second sampler U2 are d type flip flop；Differ counter U3 and The counter U4 that samples is synchronous binary counter；Output register U5 is data latches.

Claims

1. relatively prime frequency sampling probability measures the circuit of electronic signal phase difference, including the first signal input part (IN1), the second letter Number input terminal (IN2), sampling clock input terminal (CP), the first sampler (U1), the second sampler (U2), difference counter (U3), sampling counter (U4), output register (U5), digital comparator (U6), the positive B of A instead with logic gate (U7), count upper-limit Value input (M1) and OUT terminal；

First signal input part (IN1) and the ends D of the first sampler (U1) electrically connect, second signal input terminal (IN2) with The ends D of second sampler (U2) electrically connect, and the ends Q of the first sampler (U1) and the positive B of A are electric instead with the positive input terminal of logic gate (U7) Connection, the negative input end of the ends Q of the second sampler (U2) with the positive B of A instead with logic gate (U7) electrically connect, and the positive B of A are instead and logic gate (U7) output end is electrically connected with the synchronous enabled end for differing counter (U3)；It is described difference counter (U3) output end with it is defeated The input terminal for going out register (U5) electrically connects, and output end and the OUT output ends of output register (U5) electrically connect；

The count upper-limit value input (M1) and the X input terminals of digital comparator (U6) electrically connect, sampling counter (U4) The Y input terminals of output end and digital comparator (U6) electrically connect；

The output end of the digital comparator (U6) simultaneously with the synchronous clear terminal of difference counter (U3), sampling counter (U4) Synchronization clear terminal and the synchronous enabled end of output register (U5) electrically connect；

Sampling clock input terminal (CP) is inputted with the input end of clock of the first sampler (U1), the clock of the second sampler (U2) End, the input end of clock of difference counter (U3), the input end of clock of counter (U4) of sampling, the clock of output register (U5) Input terminal electrically connects.

2. relatively prime frequency sampling probability according to claim 1 measures the circuit of electronic signal phase difference, it is characterised in that； First sampler (U1) and the second sampler (U2) are d type flip flop；Differ counter (U3) and sampling counter (U4) It is synchronous binary counter；Output register (U5) is data latches.