CN208076611U - Random frequency modulation sampling probability measures the circuit of electronic signal phase difference - Google Patents
Random frequency modulation sampling probability measures the circuit of electronic signal phase difference Download PDFInfo
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- CN208076611U CN208076611U CN201820637431.2U CN201820637431U CN208076611U CN 208076611 U CN208076611 U CN 208076611U CN 201820637431 U CN201820637431 U CN 201820637431U CN 208076611 U CN208076611 U CN 208076611U
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Abstract
Random frequency modulation sampling probability measures the circuit of electronic signal phase difference, it is related to electronic technology and field of broadcast televisions, solve the problems such as circuit is complicated and inaccurate when existing method measures high-frequency signal, including the first signal input part, second signal input terminal, input end of clock, first sampler, second sampler differs counter, counter of sampling, output register, digital comparator, the positive B of A instead and logic gate, count upper-limit value input, frequency counter, randomizer divides digital comparator, divides d type flip flop and OUT output ends；The utility model can directly measure high-frequency signal, directly obtain the digitlization difference numerical value of specified physical unit, be well suited for measuring small phase difference, high certainty of measurement, the linearity is good, strong antijamming capability.The utility model does not need agc circuit, does not need the complex components such as multiplier yet, so circuit is very simple, with the relatively low digital circuit of cost or the microcontroller of hardware multiplier can not obtain preferable measurement effect.
Description
Technical field
The utility model is related to electronic technology and field of broadcast televisions can design radio signal with this technology
Interferometer, for orientation where measuring the radio emitting sources such as TV and radio emission machine.
Background technology
Largely there is illegal black appliances platform in each main cities at home in recent years, pretend to be the legal media of country, mainly from the leave of absence
Medicine publicizes.In order to effectively supervise radio and television and radio environment, its black appliances platform unlawful activities is hit, needs to monitor radio and television
The legitimacy of program, and measurement and positioning pirate radio.This will use one kind that can measure radio emitting source direction
Radio signal interferometer, principle is exactly to calculate the direction where information source by measuring the phase difference of radio signal
Angle.
The phase difference main method for measuring radio signal at present is the time difference for measuring two signals at zero crossing, then
Become phase difference according to frequency conversion.In actual circuit, because Signal averaging noise or being interfered or circuit distortion
Zero passage point moment is caused to be inaccurate.It being limited by circuit count clock frequency, the precision that this method measures high-frequency signal is not high,
It is only applicable to low frequency signal measurement.
Also two signal multiplications of analog multiplier pair is used to filter again later, measures DC component and two in product signal
At cosine function relationship between a signal, or measurement amplitude after signal is added and subtracted.This type method is needed with agc circuit input
Signal becomes the signal of same-amplitude, there is linear bad, precision deficiency, the higher problem of cost.
Utility model content
The utility model is to solve existing method to measure that high-frequency signal phase difference precision is low and measurement cost is larger etc. asks
Topic provides a kind of circuit of random frequency modulation sampling probability measurement electronic signal phase difference.
Random frequency modulation sampling probability measures the device of electronic signal phase difference, including the first signal input part, second signal
Input terminal, input end of clock, the first sampler, the second sampler, difference counter, sampling counter, output register, numerical value
The positive B of comparator, A is instead compared with logic gate, count upper-limit value input, frequency counter, randomizer, frequency dividing numerical value
Device, frequency dividing d type flip flop and OUT output ends；
The ends D of first signal input part and the first sampler electrically connect, second signal input terminal and the second sampler
The ends D electrically connect, the ends Q and the positive B of A of the first sampler are instead electrically connected with the positive input terminal of logic gate, the ends Q of the second sampler with
The positive B of A are instead electrically connected with the negative input end of logic gate；
The positive B of A are instead electrically connected with the output end of logic gate with the synchronous enabled end for differing counter, count upper-limit numerical value
The X bus input ends of input terminal and digital comparator electrically connect, and the output end for counter of sampling and the Y buses of digital comparator are defeated
Enter end to electrically connect, the output end of digital comparator simultaneously with the synchronous clear terminal of difference counter, sampling counter synchronize it is clear
Zero end and the synchronous enabled end of output register electrically connect；
The input terminal of the output end and output register that differ counter electrically connects, the output end and OUT of output register
Output end electrically connects；
The input end of clock of input end of clock and frequency counter, the input end of clock for dividing d type flip flop electrically connect, and divide
The output end of counter and the I bus input ends of frequency dividing digital comparator electrically connect；
The output end of the randomizer is as numerical value low data output end, VCC as high position data output end
J bus input ends after parallel connection with frequency dividing digital comparator electrically connect, and output end and the frequency dividing D of the frequency dividing digital comparator are touched
The D input terminals of hair device electrically connect；
Synchronous clear terminal, the clock of randomizer are defeated with frequency counter for the output end of the frequency dividing d type flip flop
Enter end, the input end of clock of the input end of clock of the first sampler, the second sampler, the input end of clock for differing counter, pumping
The input end of clock of sample counter and the input end of clock of output register electrically connect.
The beneficial effects of the utility model：Measuring circuit provided by the utility model can directly measure high-frequency signal, directly
It connecing to obtain the digitlization difference numerical value of specified physical unit, is well suited for measuring small phase difference, high certainty of measurement, the linearity is good,
Strong antijamming capability.Because the utility model does not need agc circuit, the complex components such as multiplier are not needed yet, so circuit
Very simple, with the relatively low digital circuit of cost or the microcontroller of hardware multiplier can not obtain preferable measurement effect.
Description of the drawings
Fig. 1 is the circuit logic diagram that random frequency modulation sampling probability described in the utility model measures electronic signal phase difference.
Specific implementation mode
Specific implementation mode, embodiment is described with reference to Fig. 1, and random frequency modulation sampling probability measures electronic signal phase difference
Circuit, including the first signal input part IN1, second signal input terminal IN2, input end of clock OSC, the first sampler U1,
Two sampler U2, difference counter U3, sampling counter U4, output register U5, the positive B of digital comparator U6, A are instead and logic gate
U7, count upper-limit value input M1, frequency counter U8, randomizer U9, frequency dividing digital comparator U10, frequency dividing D are touched
Send out device U11 and OUT output end；It is characterized in that；
The ends D of the first signal input part IN1 and the first sampler U1 electrically connect, second signal input terminal IN2 and
The ends D of two sampler U2 electrically connect, and the positive input terminal of the ends Q of the first sampler U1 with the positive B of A instead with logic gate U7 electrically connects, and
Negative input end of the ends Q of two sampler U2 with the positive B of A instead with logic gate U7 electrically connects；
The positive B of A are instead electrically connected with the output end of logic gate U7 with the synchronous enabled end for differing counter U3, count upper-limit
The X bus input ends of value input M1 and digital comparator U6 electrically connect, and the output end of sampling counter U4 is compared with numerical value
The Y bus input ends of device U6 electrically connect, the output end of digital comparator U6 simultaneously with the synchronous clear terminal of difference counter U3, pumping
The synchronization clear terminal of sample counter U4 and the synchronous enabled end of output register U5 electrically connect；
The input terminal of the output end and output register U5 of difference counter U3 electrically connects, the output end of output register U5
It is electrically connected with OUT output ends；
The input end of clock of input end of clock OSC and frequency counter U8, the input end of clock electricity of frequency dividing d type flip flop U11
The I bus input ends of connection, the output end and frequency dividing digital comparator U10 of frequency counter U8 electrically connect；
The output end of the randomizer U9 is defeated as high position data as numerical value low data output end, the ends VCC
J bus input ends after outlet parallel connection with frequency dividing digital comparator U10 electrically connect, the output of the frequency dividing digital comparator U10
The D input terminals with frequency dividing d type flip flop U11 are held to electrically connect；
The output end clear terminal synchronous with frequency counter U8's of the frequency dividing d type flip flop U11, randomizer U9
Input end of clock, the input end of clock of the first sampler U1, the input end of clock of the second sampler U2, difference counter U3 when
The input end of clock of clock input terminal, the input end of clock of sampling counter U4 and output register U5 electrically connects.
In present embodiment, the first sampler U1, the second sampler U2 are d type flip flops；It differs counter U3, take out
Sample counter U4 and frequency counter U8 is synchronous binary counter；Output register U5 is data latches；In counting
The numerical value M of limit value input M1 needs the fixed numbers being arranged according to measurement accuracy and physical unit.Need not often it change；
Randomizer U9 is to design the pseudorandom number generator of random frequency modulation range；The ends VCC and randomizer U9
Output end merge as a numerical value, as high position data output end as a data high position, random number occurs at the ends VCC
Device U9 outputs are used as data low level.According to the design requirement for measuring relative accuracy, the data bit width of randomizer U9 is determined
N, measurement accuracy d=1/2n。
Claims (2)
1. random frequency modulation sampling probability measures the circuit of electronic signal phase difference, including the first signal input part (IN1), the second letter
Number input terminal (IN2), the first sampler (U1), the second sampler (U2), difference counter (U3), is taken out input end of clock (OSC)
Sample counter (U4), output register (U5), digital comparator (U6), the positive B of A are anti-defeated with logic gate (U7), count upper-limit numerical value
Enter end (M1), frequency counter (U8), randomizer (U9), frequency dividing digital comparator (U10), frequency dividing d type flip flop (U11)
With OUT output ends；It is characterized in that；
First signal input part (IN1) and the ends D of the first sampler (U1) electrically connect, second signal input terminal (IN2) with
The ends D of second sampler (U2) electrically connect, and the ends Q of the first sampler (U1) and the positive B of A are electric instead with the positive input terminal of logic gate (U7)
Connection, the negative input end of the ends Q of the second sampler (U2) with the positive B of A instead with logic gate (U7) electrically connect；
The positive B of A are instead electrically connected with the output end of logic gate (U7) with the synchronous enabled end for differing counter (U3), count upper-limit
Value input (M1) and the X bus input ends of digital comparator (U6) electrically connect, the output end and number of sampling counter (U4)
The Y bus input ends of value comparator (U6) electrically connect, the output end of digital comparator (U6) simultaneously with differ counter (U3)
Synchronous clear terminal, the synchronization clear terminal of sampling counter (U4) and the synchronous enabled end of output register (U5) electrically connect；
The input terminal of the output end and output register (U5) of difference counter (U3) electrically connects, the output of output register (U5)
End is electrically connected with OUT output ends；
Input end of clock (OSC) and the input end of clock of frequency counter (U8), the input end of clock of frequency dividing d type flip flop (U11)
It electrically connects, the I bus input ends of the output end and frequency dividing digital comparator (U10) of frequency counter (U8) electrically connect；
The output end of the randomizer (U9) is as numerical value low data output end, VCC as high position data output end
J bus input ends after parallel connection with frequency dividing digital comparator (U10) electrically connect, the output of the frequency dividing digital comparator (U10)
The D input terminals with frequency dividing d type flip flop (U11) are held to electrically connect；
The output end and the synchronous clear terminal of frequency counter (U8), randomizer (U9) of the frequency dividing d type flip flop (U11)
Input end of clock, the input end of clock of the first sampler (U1), the input end of clock of the second sampler (U2), difference counter
(U3) input end of clock, the input end of clock of sampling counter (U4) and the input end of clock Electricity Federation of output register (U5)
It connects.
2. random frequency modulation sampling probability according to claim 1 measures the circuit of electronic signal phase difference, it is characterised in that；
First sampler (U1), the second sampler (U2) are all d type flip flops；Differ counter (U3), sampling counter (U4) and frequency dividing
Counter (U8) is synchronous binary counter；Output register (U5) is data latches；Count upper-limit value input
(M1) the numerical value M inputted is the fixed numbers for needing to be arranged according to measurement accuracy and physical unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820637431.2U CN208076611U (en) | 2018-04-28 | 2018-04-28 | Random frequency modulation sampling probability measures the circuit of electronic signal phase difference |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108710028A (en) * | 2018-04-28 | 2018-10-26 | 吉林省广播电视研究所(吉林省新闻出版广电局科技信息中心) | Random frequency modulation sampling probability measures the device and method of electronic signal phase difference |
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2018
- 2018-04-28 CN CN201820637431.2U patent/CN208076611U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108710028A (en) * | 2018-04-28 | 2018-10-26 | 吉林省广播电视研究所(吉林省新闻出版广电局科技信息中心) | Random frequency modulation sampling probability measures the device and method of electronic signal phase difference |
| CN108710028B (en) * | 2018-04-28 | 2023-06-09 | 吉林省广播电视研究所(吉林省新闻出版广电局科技信息中心) | Device and method for measuring phase difference of electronic signals by random frequency modulation sampling probability |
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