CN208027132U - Integrated circuit for pyroelectric infrared sensor controls chip - Google Patents

Abstract

Present disclose provides a kind of integrated circuits for pyroelectric infrared sensor to control chip, is related to pyroelectric infrared sensor technical field.Integrated circuit control chip includes signal acquisition circuit and the signal processing circuit that is connect with signal acquisition circuit.Signal acquisition circuit acquires opposite polarity first voltage signal and second voltage signal；In the first stage, in response at least one clock control signal, first voltage signal is output to the first input end of signal processing circuit, second voltage signal is output to the second input terminal of signal processing circuit；In second stage, in response at least one clock control signal, first voltage signal is output to the second input terminal, second voltage signal is output to first input end.Signal processing circuit carries out signal processing to first voltage signal and second voltage signal, to export control signal.

Description

Integrated circuit for pyroelectric infrared sensor controls chip

Technical field

This disclosure relates to pyroelectric infrared sensor technical field more particularly to a kind of for pyroelectric infrared sensor Integrated circuit controls chip.

Background technology

Pyroelectric infrared sensor can effectively detect the mobile source of infrared radiation in sensitizing range at normal temperatures, very suitable Close the smart home field being applied in Internet of Things.Pyroelectric infrared sensor can be used for detecting physical activity, each to realize Kind automation control.For example, pyroelectric infrared sensor can be used for intelligent lighting controls, corridor automatic switch control, antitheft Controlling alarm etc..In addition, pyroelectric infrared sensor can be also used for it is more intelligentized automatically control, for example, when room without Air-conditioning is automatically closed when people's activity, television set etc. is automatically closed after having fallen asleep in the people in parlor nobody or parlor.

Utility model content

When acquiring the signal of pyroelectric infrared sensor, need to adopt from the infrared sensor of pyroelectric infrared sensor Collect opposite polarity two signals.Inventors noted that due to infrared sensor two signals of difference and acquisition it is defeated The process deviation of inbound port can cause the ambient noise signal of collected two signals inconsistent, influence subsequently to two Signal carries out the accuracy of the control signal exported after signal processing, causes control result inaccurate.In view of collected letter It is number inherently very faint, therefore the final control result of inconsistent meeting degree of ambient noise signal causes prodigious adverse effect.

To solve the above-mentioned problems, the embodiment of the present disclosure provides following solution.

According to the one side of the embodiment of the present disclosure, a kind of integrated circuit control core for pyroelectric infrared sensor is provided Piece, including signal acquisition circuit and the signal processing circuit that is connect with the signal acquisition circuit.The signal acquisition circuit is adopted Collect opposite polarity first voltage signal and second voltage signal；In the first stage, in response at least one clock control signal, The first voltage signal is output to the first input end of the signal processing circuit, the second voltage signal is output to Second input terminal of the signal processing circuit；It, will be described in response at least one clock control signal in second stage First voltage signal is output to second input terminal, and the second voltage signal is output to the first input end.It is described Signal processing circuit carries out signal processing to the first voltage signal and the second voltage signal, to export control signal.

In some embodiments, at least one clock control signal includes the first clock control signal of with same frequency and reversed-phase Signal is controlled with second clock.

In some embodiments, the signal acquisition circuit includes：First switch, the first end of the first switch by with It is set to and receives the first voltage signal, the second end of the first switch is connected with the first input end, and described first opens The control terminal of pass is configured as receiving first clock control signal；Second switch, the first end of the second switch by with It is set to and receives the second voltage signal, the second end of the second switch is connected with the first input end, and described second opens The control terminal of pass is configured as receiving the second clock control signal；Third switchs, the first end of third switch by with It is set to and receives the second voltage signal, the second end of the third switch is connected with second input terminal, and the third is opened The control terminal of pass is configured as receiving first clock control signal；And the 4th switch, it is described 4th switch first end It is configured as receiving the first voltage signal, the second end of the 4th switch is connected with second input terminal, and described the The control terminal of four switches is configured as receiving the second clock control signal.

In some embodiments, the integrated circuit control chip further includes：Signal generating circuit is controlled, with the signal Acquisition Circuit connects, and signal is controlled for generating first clock control signal and the second clock.

In some embodiments, the control signal generating circuit includes the first phase inverter, the second phase inverter, third reverse phase Device, the 4th phase inverter, the 5th phase inverter, hex inverter, the first OR-NOT circuit and the second OR-NOT circuit, wherein：It is described The input terminal of first phase inverter is configured as receiving clock control signal, and the output end of first phase inverter is connected to described the The output end of the first input end of the input terminal of two phase inverters and second OR-NOT circuit, second phase inverter is connected to The output end of the first input end of first OR-NOT circuit, first OR-NOT circuit is anti-by the cascade third Phase device and the 4th phase inverter are connected to the second input terminal of second OR-NOT circuit, and are configured as exporting described One clock control signal；The output end of second OR-NOT circuit passes through cascade 5th phase inverter and the described 6th instead Phase device is connected to the second input terminal of first OR-NOT circuit, and is configured as exporting the second clock control signal.

In some embodiments, the signal processing circuit include amplifying circuit, the modulus that is connect with the amplifying circuit Conversion circuit and the control circuit being connect with analog-digital conversion circuit as described；Wherein, the amplifying circuit is by the first voltage The difference of signal and the second voltage signal is amplified to obtain amplified signal；Analog-digital conversion circuit as described is by the amplified signal Digital signal is converted to, and the digital signal is output to the control circuit；The control circuit is believed according to the number Number output control signal.

In some embodiments, the integrated circuit control chip further includes：Amplification factor conditioned circuit, with the control Circuit is connected with the amplifying circuit；Wherein, the amplification factor conditioned circuit is according to the multiple exported from the control circuit Signal is controlled to adjust the amplification factor of the amplifying circuit.

In some embodiments, the amplification factor conditioned circuit includes selection circuit and multiple constant-current circuits in parallel； Wherein, the selection circuit controls signal according to the multiple, controls the constant current of one or more of the multiple constant-current circuit Circuit is to the amplifying circuit output current.

In some embodiments, each constant-current circuit includes：The first electrode of controlling transistor, the controlling transistor connects It is connected to power voltage terminal, the coordination electrode of the controlling transistor is connected to the selection circuit；And switching transistor, it is described to open The first electrode for closing transistor is connected to the second electrode of the controlling transistor, the second electrode connection of the switching transistor To the amplifying circuit, the coordination electrode of the switching transistor is connected to the selection circuit.

In some embodiments, the amplifying circuit includes compensation circuit.

In the integrated circuit control chip that the embodiment of the present disclosure provides, in the different stages, first voltage signal is entered To the different input terminals of signal processing circuit, second voltage signal is also input to the different input terminals of signal processing circuit. It is fixedly input to first input end with by first voltage signal, first voltage signal is fixedly input to first input end phase Than the scheme of above-described embodiment can make the ambient noise signal in first input end received signal and the second input termination Ambient noise signal in the signal of receipts is almost the same, to improve the accuracy for controlling signal of output, avoids control result It is inaccurate.

By referring to the drawings to the detailed description of the exemplary embodiment of the disclosure, the other feature of the disclosure, side Face and its advantage will become apparent.

Description of the drawings

Attached drawing forms part of this specification, and which depict the exemplary embodiments of the disclosure, and together with specification Together for explaining the principles of this disclosure, in the accompanying drawings：

Fig. 1 is the knot that chip is controlled according to the integrated circuit for pyroelectric infrared sensor of the disclosure some embodiments Structure schematic diagram；

Fig. 2 is the signal that signal is controlled according to the first clock control signal and second clock of the disclosure some embodiments Figure；

Fig. 3 A are the integrated circuit control chips for pyroelectric infrared sensor according to other embodiments of the disclosure Structural schematic diagram；

Fig. 3 B are to control chip according to the integrated circuit for pyroelectric infrared sensor of the other embodiment of the disclosure Structural schematic diagram；

Fig. 4 is to control chip according to the integrated circuit for pyroelectric infrared sensor of the other embodiment of the disclosure Structural schematic diagram；

Fig. 5 is the structural schematic diagram for controlling signal generating circuit according to some realization methods of the disclosure；

Fig. 6 is controlled according to the clock signal of some realization methods of the disclosure, the first clock control signal and second clock The correspondence schematic diagram of signal；

Fig. 7 is to control chip according to the integrated circuit for pyroelectric infrared sensor of disclosure still other embodiments Structural schematic diagram；

Fig. 8 is the structural schematic diagram according to the amplification factor conditioned circuit of the disclosure some realization methods；

Fig. 9 is to control chip according to the integrated circuit for pyroelectric infrared sensor of the disclosure also some embodiments Structural schematic diagram；

Figure 10 is the structural schematic diagram according to the compensation circuit of the disclosure some realization methods；

Figure 11 is the flow diagram according to the control method of the disclosure some embodiments.

It should be understood that the size of attached various pieces shown in the drawings is not to be drawn according to actual proportionate relationship. In addition, same or similar reference label indicates same or similar component.

Specific implementation mode

The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.Description to exemplary embodiment It is merely illustrative, never as to the disclosure and its application or any restrictions used.The disclosure can be with many differences Form realize, be not limited to the embodiments described herein.These embodiments are provided so that the disclosure is thorough and complete, and The scope of the present disclosure is given full expression to those skilled in the art.It should be noted that：Unless specifically stated otherwise, otherwise in these implementations Component and positioned opposite, material component, numerical expression and the numerical value of step described in example should be construed as merely and show Example property, not as limitation.

" first ", " second " and the similar word used in the disclosure is not offered as any sequence, quantity or again The property wanted, and be used only to distinguish different parts.The similar word such as " comprising " or "comprising" means the element before the word Cover the element enumerated after the word, it is not excluded that be also covered by the possibility of other element."upper", "lower" etc. are only used for indicating opposite Position relationship, after the absolute position for being described object changes, then the relative position relation may also correspondingly change.

In the disclosure, when being described to particular elements between the first component and second component, in the particular elements May exist intervening elements between the first component or second component, there can not also be intervening elements.When being described to particular portion When part connects other components, which can be directly connected to other components without intervening elements, can also It is not directly connected to other components and there are intervening elements.

All terms (including technical term or scientific terminology) that the disclosure uses are common with disclosure fields The meaning that technical staff understands is identical, unless otherwise specifically defined.It is also understood that in term such as defined in the general dictionary The meaning consistent with their meanings in the context of the relevant technologies should be interpreted as having, without application idealization or The meaning of extremely formalization explains, unless being clearly defined herein.

Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable In the case of, the technology, method and apparatus should be considered as part of specification.

Fig. 1 is the knot that chip is controlled according to the integrated circuit for pyroelectric infrared sensor of the disclosure some embodiments Structure schematic diagram.In the following description, for sake of simplicity, integrated circuit control chip is called control chip for short.

As shown in Figure 1, control chip may include signal acquisition circuit 101 and the letter that is connect with signal acquisition circuit 101 Number processing circuit 102.

Signal acquisition circuit 101 is configured as acquiring opposite polarity first voltage signal V1 and second voltage signal V2. For example, the first input end M1 of signal acquisition circuit 101 is for acquiring first voltage signal V1, the of signal acquisition circuit 101 Two input terminal M2 are for acquiring second voltage signal V2.

Signal acquisition circuit 101 is additionally configured to receive at least one clock control signal.In some embodiments, described At least one clock control signal may include a clock control signal, can also include two clocks letter of with same frequency and reversed-phase Number, such as the first clock control signal CS1 shown in FIG. 1 and second clock control signal CS2.

In the first stage, signal acquisition circuit 101 in response at least one first clock control signal (for example, One clock control signal CS1 and second clock control signal CS2) CS1 and second clock control signal CS2, first voltage believed Number V1 is output to the first input end P1 of signal processing circuit 102, and second voltage signal V2 is output to signal processing circuit 102 The second input terminal P2.

In second stage, signal acquisition circuit 101 is in response at least one clock control signal (for example, when first Clock signal CS1 and second clock control signal CS2), first voltage signal V1 is output to the second input terminal P2, by second Voltage signal V2 is output to first input end P1.

Signal processing circuit 102 is configured as carrying out signal processing to first voltage signal V1 and second voltage signal V2, Signal is controlled with output.Here the processing such as can be amplification, filtering of signal processing.What signal processing circuit 102 exported Control signal can be used for controlling external devices, such as control air-conditioning switch, TV switch etc..

In above-described embodiment, in the different stages, the difference that first voltage signal V1 is input into signal processing circuit is defeated Enter end, second voltage signal V2 is also input to the different input terminals of signal processing circuit.Consolidate with by first voltage signal V1 Surely it is input to first input end P1, second voltage signal V2, which is fixedly input to the second input terminal P2, to be compared, above-mentioned implementation The scheme of example can make the letter of ambient noise signal and the second input terminal P2 receptions in first input end P1 received signals Ambient noise signal in number is almost the same, to improve the accuracy for controlling signal of output, avoids control result inaccurate.

Fig. 2 is the signal that signal is controlled according to the first clock control signal and second clock of the disclosure some embodiments Figure.As shown in Fig. 2, the first clock control signal CS1 is identical with the frequency of second clock control signal CS2, and opposite in phase.Example Such as, S1, the first clock control signal CS1 are high level in the first stage, and it is low level that second clock, which controls signal CS2,；? Two-stage S2, the first clock control signal CS1 are low level, and it is high level that second clock, which controls signal CS2,.However, the disclosure Be not limited to this, if the first clock control signal CS1 in the first stage the logic level under S1 and second stage S2 on the contrary, simultaneously And logic levels of the second clock control signal CS2 in the first stage under S1 and second stage S2 is opposite.

Fig. 3 A are the integrated circuit control chips for pyroelectric infrared sensor according to other embodiments of the disclosure Structural schematic diagram.As shown in Figure 3A, the signal acquisition circuit 101 in the embodiment includes first switch 111, second switch 121, third switch 131 and the 4th switch 141.

The first end of first switch 111 is configured as receiving first voltage signal V1, the second end of first switch 111 and the One input terminal P1 is connected, and the control terminal of first switch 111 is configured as receiving the first clock control signal CS1.Second switch 121 First end be configured as receiving second voltage signal V2, the second end of second switch is connected with first input end P1, and second opens The control terminal of pass is configured as receiving second clock control signal CS2.The first end of third switch 131 is configured as reception second Voltage signal V2, the second end of third switch 131 are connected with the second input terminal P2, and the control terminal of third switch 131 is configured as Receive the first clock control signal CS1.The first end of 4th switch 141 is configured as receiving first voltage signal V1, and the 4th opens The second end of pass 141 is connected with the second input terminal P2, and the control terminal of the 4th switch 141 is configured as receiving second clock control letter Number CS2.

It should be noted that first switch 111, second switch 121 shown in Fig. 3 A, third switch 131 and the 4th switch 141 can be NMOS (N-channel Metal OxideSemiconductor, N-type channel metal-oxide semiconductor (MOS)) crystalline substances Body pipe, but the disclosure is not limited to this.For example, in certain embodiments, first switch 111, second switch 121, third are opened Pass 131 and the 4th switch 141 can also be PMOS (P-channel MetalOxide Semiconductor, P-type channel gold Belong to oxide semiconductor) transistor or bipolar transistor etc..

In the case that the first clock control signal CS1 be high level, second clock control signal CS2 be it is low level, the One switch 111 and third switch 131 are connected, second switch 121 and the shutdown of the 4th switch 141, so that first voltage signal V1 is input into first input end P1, and first voltage signal V1 is input into the second input terminal P2.In the first clock control signal CS1 be low level, second clock control signal CS2 be high level in the case of, first switch 111 and third switch 131 shutdown, Second switch 121 and the conducting of the 4th switch 141, so that first voltage signal V1 is input into first input end P1, first Voltage signal V1 is input into first input end P1.

Fig. 3 B are the structural schematic diagrams according to the pyroelectric infrared sensor of the disclosure other embodiments.Only emphasis below The difference of Fig. 3 B and Fig. 3 A are described, other same or similar place is referred to above description.

As shown in Figure 3B, the signal acquisition circuit 101 in the embodiment includes first switch 111, second switch 121, the Three switches 131 and the 4th switch 141.

Fig. 3 B and Fig. 3 A are the difference is that first switch 111, second switch 121, third switch 131 and the 4th switch 141 control terminal receives a clock control signal CS.In this case, first switch 111 and third switch 131 are NMOS Transistor, second switch 121 and the 4th switch 141 are PMOS transistors.Alternatively, first switch 111 and third switch 131 are PMOS transistor, second switch 121 and the 4th switch 141 are NMOS transistors.

In above-described embodiment, the function of signal acquisition circuit 101 can also be realized by a clock control signal CS.

Fig. 4 is to control chip according to the integrated circuit for pyroelectric infrared sensor of the other embodiment of the disclosure Structural schematic diagram.As shown in figure 4, the control chip in the embodiment can also include the control letter being connect with signal acquisition circuit Number generation circuit 103, the first clock control signal CS1 for generating with same frequency and reversed-phase and second clock control signal CS2.

Fig. 5 is the structural schematic diagram for controlling signal generating circuit according to some realization methods of the disclosure.As shown in figure 5, It may include the first phase inverter 113, the second phase inverter 123, third phase inverter 133, the 4th reverse phase to control signal generating circuit 103 Device 143, the 5th phase inverter 153, hex inverter 163, the first OR-NOT circuit 173 and the second OR-NOT circuit 183.

The input terminal of first phase inverter 113 is configured as receiving clock signal clk, and the output end of the first phase inverter 113 connects It is connected to the first input end B1 of the input terminal and the second OR-NOT circuit 183 of the second phase inverter 123.Second phase inverter 123 it is defeated Outlet is connected to the first input end A1 of the first OR-NOT circuit 173.The output end OUT1 of first OR-NOT circuit 173 passes through grade The third phase inverter 133 and the 4th phase inverter 143 of connection are connected to the second input terminal B2 of the second OR-NOT circuit 183, and export End OUT1 is configured as the first clock control signal CS1 of output.The output end OUT2 of second OR-NOT circuit 183 is by cascade 5th phase inverter 153 and hex inverter 163 are connected to the second input terminal A2 of the first OR-NOT circuit 173, and output end OUT2 is configured as output second clock control signal CS2.

Fig. 6 is the clock control signal, the first clock control signal and second clock according to some realization methods of the disclosure Control the correspondence schematic diagram of signal.Control signal generating circuit 103 shown in fig. 5 can clock signal clk according to figure 6 Generate the first clock control signal CS1 and second clock control signal CS2 of with same frequency and reversed-phase.

The operation principle for controlling signal generating circuit 103 is introduced so that clock signal clk is high level as an example below.

In the case where clock signal clk is high level, the first input end A1 of the first OR-NOT circuit 173 is high electricity Flat, the first input end B1 of the second OR-NOT circuit 183 is low level.In the first input end A1 of the first OR-NOT circuit 173 In the case of for high level, the first clock control signal CS1 of the output end OUT1 outputs of the first OR-NOT circuit 173 is low electricity It is flat.Low level first clock control signal CS1 is input to after 133 and the 4th phase inverter 143 of cascade third phase inverter Second input terminal B2 of the second OR-NOT circuit 183.In the first input end B1 and the second input terminal of the second OR-NOT circuit 183 In the case of B2 is low level, the second clock control signal CS2 of the output end OUT2 outputs of the second OR-NOT circuit 183 is High level.The second clock control signal CS2 of high level is defeated after cascade 5th phase inverter 153 and hex inverter 163 Enter the second input terminal A2 to the first OR-NOT circuit 173.

By analyzing above it is found that in the case where clock signal clk is high level, the output of the first OR-NOT circuit 173 It is low level to hold the first clock control signal CS1 of OUT1 outputs, the of the output end OUT2 output of the second OR-NOT circuit 183 Two clock control signal CS2 are high level.Similarly, it is low level, the first OR-NOT circuit in clock signal clk First clock control signal CS1 of 173 output end OUT1 outputs is high level, the output end of the second OR-NOT circuit 183 The second clock control signal CS2 of OUT2 outputs is low level.

It should be noted that Fig. 5 provide realize control signal generating circuit using 6 phase inverters and two nor gates 103 mode is only an illustrative example.The disclosure is not limited to this.For example, in some implementations, it can also Control signal generating circuit is realized with door, be no longer described in detail herein using 8 phase inverters and two.

Fig. 7 is to control chip according to the integrated circuit for pyroelectric infrared sensor of disclosure still other embodiments Structural schematic diagram.As shown in fig. 7, the signal processing circuit 102 in the embodiment includes amplifying circuit 112 and amplifying circuit 112 The analog to digital conversion circuit 122 of connection and the control circuit 132 being connect with analog to digital conversion circuit 122.

Amplifying circuit 112 is configured as amplifying the difference of first voltage signal V1 and second voltage signal V2 to be put Big signal.In some embodiments, the multiple that amplifying circuit 112 is amplified can be 1-100 times, such as 30 times, 50 times etc..

Analog to digital conversion circuit 122 is configured as amplified signal being converted to digital signal, and digital signal is output to control Circuit 132 processed.Here, effective sensor output signal had both been contained in digital signal, while also containing ambient noise letter Number.For example, analog to digital conversion circuit 122 can be the analog-digital converter (ADC) of sigma-Delta types.Sigma-Delta types ADC It can be by ambient noise high frequency.Preferably, analog to digital conversion circuit 122 can be 16 sigma-Delta types ADC.

Control circuit 132 is configured as according to the digital signal output control signal received.For example, control circuit 132 Control signal can be output to intelligent switch, to control the shutdown of intelligent switch.For example, control circuit 132 can be special Integrated circuit.

In some embodiments, referring to Fig. 7, control chip can also include connecting with control circuit 132 and amplifying circuit 112 The amplification factor conditioned circuit 104 connect.Amplification factor conditioned circuit 104 is configured as according to times exported from control circuit 132 Number controls signal to adjust the amplification factor of amplifying circuit 112.

In some implementations, multiple control signal may include multiple tune up control signal and multiple turn down control letter Number.Control circuit 132 is configured as in the case where first voltage signal V1 and second voltage signal V2 is ambient noise signal, Compare the amplitude of digital signal and the size of threshold value；It, can to amplification factor in the case where the amplitude of digital signal is less than threshold value It adjusts circuit 104 to export multiple and tunes up control signal；It is adjustable to amplification factor in the case where the amplitude of digital signal is more than threshold value Circuit 104 exports multiple and turns control signal down.Correspondingly, amplification factor conditioned circuit 104 is configured as tuning up control according to multiple Signal processed increases the amplification factor of amplifying circuit 112, and the times magnification that control signal reduces amplifying circuit 112 is turned down according to multiple Number.

For example, special function register (SFR) can be contained in control circuit 132, the threshold of setting can be stored in SFR Value.

In above-mentioned realization method, the case where first voltage signal V1 and second voltage signal V2 is ambient noise signal Under, the amplitude of digital signal can reflect the size of ambient noise signal.By being close to threshold by the range-adjusting of digital signal Value, the ambient noise signal that can to control in the signal of chip acquisition are almost the same.In this way, using such control chip Ambient noise signal of the different pyroelectric infrared sensors when acquiring signal can be essentially identical, ensure that rpyroelectric infrared The consistency of the performance of sensor.

In practical applications, amplification factor conditioned circuit 104 can by adjust be output to amplifying circuit 112 electric current it is big It is small to adjust the amplification factor of amplifying circuit 112, it can also be output to the voltage swing of amplifying circuit 112 by adjusting and adjust The amplification factor of amplifying circuit 112.An example of amplification factor conditioned circuit is introduced below in conjunction with Fig. 8.

Fig. 8 is the structural schematic diagram according to the amplification factor conditioned circuit of the disclosure some realization methods.As shown in figure 8, Amplification factor conditioned circuit 104 may include selection circuit 114 and multiple constant-current circuits 124 in parallel.Selection circuit 114 can be with It is configured as controlling signal according to the multiple that control circuit 132 exports, controls one or more of multiple constant-current circuits 124 perseverance 112 output current of galvanic electricity road direction amplifying circuit.

In some embodiments, the size of current that different constant-current circuits 124 exports can be identical.In other embodiments In, the size of current of different constant-current circuits 124 output can also be different.Selection circuit 114 can control one or more perseverances Current circuit 124 is to 112 output current of amplifying circuit, so as to control the total size of the electric current exported to amplifying circuit 112.Example Such as, selection circuit 114 can tune up control signal to reduce the electric current exported to amplifying circuit 112, to increase according to multiple The amplification factor of amplifying circuit 112.In another example selection circuit 114 can turn control signal down to increase to amplification according to multiple The electric current that circuit 112 exports, to reduce the amplification factor of amplifying circuit 112.

In some implementations, referring to Fig. 8, each constant-current circuit 124 may include that controlling transistor T1 and switch are brilliant Body pipe T2.The first electrode of controlling transistor T1 is connected to power voltage terminal VDD, and the coordination electrode of controlling transistor T1 is connected to Selection circuit 114, the second electrode of controlling transistor T2 are connected to the first electrode of switching transistor T2.Switching transistor T2's Second electrode is connected to amplifying circuit 112, and the coordination electrode of switching transistor T2 is connected to selection circuit 114.Controlling transistor T1 and switching transistor T2

Fig. 9 is to control chip according to the integrated circuit for pyroelectric infrared sensor of the disclosure also some embodiments Structural schematic diagram.As shown in figure 9, the signal processing circuit 102 in the embodiment can also include connecting with analog to digital conversion circuit 122 The filter 142 connect.Filter 142 can filter the noise outside useful signal band, it is ensured that digital signal accurately reflects sensing The variation for the analog signal that device generates.

In some embodiments, filter 142 can be Butterworth filter, Bessel filter, Bei Qiexuefu filters At least one of wave device.In some embodiments, filter 142 can be digital filter, low-pass filter, bandpass filtering At least one of device, analog filter, SAW filter, dielectric filter, Active Power Filter-APF.Illustratively, it filters The effective bandwidth of wave device 142 can be 0.4Hz~7Hz.

Preferably, above-mentioned filter 142 can be Butterworth filter, and be bandpass filter, and effective bandwidth is 0.4Hz~7Hz.For example, 16 digital signals can be formed after the processing of Butterworth bandpass filter.

In some embodiments, the amplifying circuit 112 in signal processing circuit 102 can also include compensation circuit 1121. Compensation circuit 1121 maintains the stabilization of amplifying circuit 112 by the way of automatic growth control.

Different realization methods may be used to realize in compensation circuit 1121, as long as can be maintained by way of negative-feedback The stabilization of amplifying circuit 112.A kind of specific implementation of compensation circuit is introduced below in conjunction with Figure 10.

Figure 10 is the structural schematic diagram according to the compensation circuit of the disclosure some realization methods.As shown in Figure 10, compensation electricity Road may include transistor T11, T12, T13 ... and T41.

The first electrode of transistor T11 is connected to supply voltage VDD, and the coordination electrode of transistor T11 is for receiving second The second electrode of voltage signal V2, transistor T11 are connected to first node Nd1.

The first electrode of transistor T12 is connected to supply voltage VDD, and the coordination electrode of transistor T12 is for receiving first The second electrode of voltage signal V1, transistor T12 are connected to second node Nd2.

The first electrode of transistor T13 and transistor T14 are connected to supply voltage VDD, transistor T13 and transistor The coordination electrode of T14 is used to receive bias voltage V_BIAS, the second electrode of transistor T13 is connected to the first of transistor T15 Electrode, the second electrode of transistor T14 are connected to the first electrode of transistor T16.

The coordination electrode of transistor T15 and transistor T16 are used to receive bias voltage V_BIAS, the second of transistor T15 The second electrode that electrode is connected to third node Nd3, transistor T16 is connected to fourth node Nd4.

The coordination electrode of transistor T17 and transistor T18 are used to receive bias voltage V_BIAS, the first of transistor T17 The first electrode that electrode is connected to third node Nd3, transistor T18 is connected to fourth node Nd4, the second electricity of transistor T17 Pole is connected to first node Nd1, and the second electrode of transistor T18 is connected to second node Nd2.

The coordination electrode of transistor T19 and transistor T20 are used to receive bias voltage V_BIAS, the first of transistor T19 Electrode is connected to second node Nd2, and the first electrode of transistor T20 is connected to first node Nd1, the second electricity of transistor T19 Pole is connected to the first electrode of transistor T38, and the second electrode of transistor T20 is connected to the first electrode of transistor T39.

The coordination electrode of transistor T21 and transistor T22 are used to receive bias voltage V_BIAS, the first of transistor T21 Electrode is connected to second node Nd2, and the first electrode of transistor T22 is connected to first node Nd1, the second electricity of transistor T21 Pole is connected to the first electrode of transistor T40, and the second electrode of transistor T22 is connected to the first electrode of transistor T41.

The control electricity of transistor T23, transistor T24, transistor T25, transistor T26, transistor T27 and transistor T28 The first electrode that pole is connected to third node Nd3, transistor T23 is connected to the 5th node Nd5, the second electricity of transistor T23 Pole is connected to the first electrode of transistor T24, and the second electrode of transistor T24 is connected to the first electrode of transistor T25, crystal The second electrode of pipe T25 is connected to the first electrode of transistor T26, and the second electrode of transistor T26 is connected to transistor T27's First electrode, the second electrode of transistor T27 are connected to the first electrode of transistor T28, the second electrode connection of transistor T28 To ground VSS.

The control electricity of transistor T29, transistor T30, transistor T31, transistor T32, transistor T33 and transistor T34 Pole is connected to fourth node Nd4, and the first electrode of transistor T29 is connected to the 5th node Nd5, the second electricity of transistor T29 Pole is connected to the first electrode of transistor T30, and the second electrode of transistor T30 is connected to the first electrode of transistor T31, crystal The second electrode of pipe T31 is connected to the first electrode of transistor T32, and the second electrode of transistor T32 is connected to transistor T33's First electrode, the second electrode of transistor T33 are connected to the first electrode of transistor T34, the second electrode connection of transistor T34 To ground VSS.

The coordination electrode of transistor T35 and transistor 36 is connected to the 5th node Nd5, transistor T35 and transistor 36 First electrode be connected to supply voltage VDD, the second electrode of transistor T35 is connected to the 5th node Nd5, transistor T36 Second electrode be connected to the first electrode of transistor T37.

The coordination electrode of transistor T37 is connected to the 6th node Nd6, and the second electrode of transistor T37 is connected to the ground VSS.

The coordination electrode of transistor T38 and transistor T40 are connected to the 6th node Nd6, transistor T38 and transistor T40 Second electrode be connected to the ground VSS.

The coordination electrode of transistor T39 and transistor T41 are connected to bias voltage V_BIAS, transistor T39 and transistor T41 Second electrode be connected to the ground VSS.

Compensation circuit in above-described embodiment can make amplifying circuit keep stablizing.

Figure 11 is the flow diagram according to the control method of the disclosure some embodiments.The control method can be based on upper The control chip of any one embodiment is stated to realize.

In step 1102, opposite polarity first voltage signal and second voltage signal are acquired.

In step 1104, in the first stage, in response at least one clock control signal, by the first voltage signal of acquisition It is output to the first input end of signal processing circuit, the second voltage signal of acquisition is output to the second defeated of signal processing circuit Enter end.In some embodiments, at least one clock control signal can be two clock control signals of with same frequency and reversed-phase.

In step 1106, in second stage, in response at least one clock control signal, by the first voltage of acquisition Signal is output to the second input terminal, and the second voltage signal of acquisition is output to first input end.

In step 1108, signal processing is carried out to export control signal to first voltage signal and second voltage signal.This In signal processing such as can be amplification, filtering processing.

In above-described embodiment, in the different stages, first voltage signal is input into the different inputs of signal processing circuit End, second voltage signal are also input to the different input terminals of signal processing circuit.With first voltage signal is fixedly defeated Enter to first input end, first voltage signal, which is fixedly input to first input end, to be compared, and the scheme of above-described embodiment can be with Make the ambient noise letter in the ambient noise signal and the second input terminal received signal in first input end received signal It is number almost the same, to improve output control signal accuracy, avoid control result inaccurate.

In some embodiments, control method shown in Figure 11 can also include the following steps：In first voltage signal and In the case that two voltage signals are noise signal, compare the amplitude of digital signal and the size of threshold value；In the amplitude of digital signal In the case of less than threshold value, increase the amplification factor of amplifying circuit；In the case where the amplitude of digital signal is more than threshold value, reduce The amplification factor of amplifying circuit.

In above-described embodiment, in the initial phase of pyroelectric infrared sensor, first voltage signal and second voltage letter Number can be ambient noise signal.In this case, the amplitude of digital signal can reflect the size of ambient noise signal.Pass through It is that the ambient noise signal in the signal of acquisition can be made almost the same close to threshold value by the range-adjusting of digital signal.

So far, the presently disclosed embodiments is described in detail.In order to avoid covering the design of the disclosure, do not describe Some details known in the field.Those skilled in the art as described above, can be appreciated how to implement here completely Disclosed technical solution.

Although some specific embodiments of the disclosure are described in detail by example, the skill of this field Art personnel it should be understood that above example merely to illustrate, rather than in order to limit the scope of the present disclosure.The skill of this field Art personnel it should be understood that can not depart from the scope of the present disclosure and spirit in the case of, modify to above example or Equivalent replacement is carried out to some technical characteristics.The scope of the present disclosure is defined by the following claims.

Claims (10)

1. a kind of integrated circuit for pyroelectric infrared sensor controls chip, which is characterized in that including signal acquisition circuit The signal processing circuit being connect with the signal acquisition circuit, wherein：

The signal acquisition circuit acquires opposite polarity first voltage signal and second voltage signal；In the first stage, it responds In at least one clock control signal, the first voltage signal is output to the first input end of the signal processing circuit, The second voltage signal is output to the second input terminal of the signal processing circuit；In second stage, in response to it is described extremely A few clock control signal, is output to second input terminal, by the second voltage signal by the first voltage signal It is output to the first input end；And

The signal processing circuit carries out signal processing to the first voltage signal and the second voltage signal, to export control Signal processed.

2. integrated circuit according to claim 1 controls chip, which is characterized in that at least one clock control signal The first clock control signal and second clock including with same frequency and reversed-phase control signal.

3. integrated circuit according to claim 2 controls chip, which is characterized in that the signal acquisition circuit includes：

First switch, the first end of the first switch are configured as receiving the first voltage signal, the first switch Second end is connected with the first input end, and the control terminal of the first switch is configured as receiving the first clock control letter Number；

Second switch, the first end of the second switch are configured as receiving the second voltage signal, the second switch Second end is connected with the first input end, and the control terminal of the second switch is configured as receiving the second clock control letter Number；

Third switchs, and the first end of the third switch is configured as receiving the second voltage signal, the third switch Second end is connected with second input terminal, and the control terminal of the third switch is configured as receiving the first clock control letter Number；And

4th switch, the first end of the 4th switch are configured as receiving the first voltage signal, the 4th switch Second end is connected with second input terminal, and the control terminal of the 4th switch is configured as receiving the second clock control letter Number.

4. integrated circuit according to claim 2 controls chip, which is characterized in that further include：

Signal generating circuit is controlled, is connect with the signal acquisition circuit, for generating first clock control signal and institute State second clock control signal.

5. integrated circuit according to claim 4 controls chip, which is characterized in that the control signal generating circuit includes First phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, the first nor gate Circuit and the second OR-NOT circuit, wherein：

The input terminal of first phase inverter is configured as receiving clock control signal, the output end connection of first phase inverter The extremely first input end of the input terminal and second OR-NOT circuit of second phase inverter,

The output end of second phase inverter is connected to the first input end of first OR-NOT circuit,

The output end of first OR-NOT circuit is connected to by the cascade third phase inverter and the 4th phase inverter Second input terminal of second OR-NOT circuit, and be configured as exporting first clock control signal；

The output end of second OR-NOT circuit is connected to by cascade 5th phase inverter and the hex inverter Second input terminal of first OR-NOT circuit, and be configured as exporting the second clock control signal.

6. the integrated circuit according to claim 1 to 5 any one controls chip, which is characterized in that the signal processing Circuit includes amplifying circuit, the analog to digital conversion circuit being connect with the amplifying circuit and is connect with analog-digital conversion circuit as described Control circuit；

Wherein, the amplifying circuit amplifies the difference of the first voltage signal and the second voltage signal to be amplified Signal；The amplified signal is converted to digital signal by analog-digital conversion circuit as described, and the digital signal is output to described Control circuit；The control circuit exports the control signal according to the digital signal.

7. integrated circuit according to claim 6 controls chip, which is characterized in that further include：

Amplification factor conditioned circuit is connect with the control circuit and the amplifying circuit；

Wherein, the amplification factor conditioned circuit adjusts described put according to the multiple control signal exported from the control circuit The amplification factor of big circuit.

8. integrated circuit according to claim 7 controls chip, which is characterized in that the amplification factor conditioned circuit includes Selection circuit and multiple constant-current circuits in parallel；

Wherein, the selection circuit controls signal according to the multiple, controls one or more of the multiple constant-current circuit Constant-current circuit is to the amplifying circuit output current.

9. integrated circuit according to claim 8 controls chip, which is characterized in that each constant-current circuit includes：

The first electrode of controlling transistor, the controlling transistor is connected to power voltage terminal, the control of the controlling transistor Electrode is connected to the selection circuit；With

Switching transistor, the first electrode of the switching transistor is connected to the second electrode of the controlling transistor, described to open The second electrode for closing transistor is connected to the amplifying circuit, and the coordination electrode of the switching transistor is connected to the selection electricity Road.

10. integrated circuit according to claim 6 controls chip, which is characterized in that the amplifying circuit includes compensation electricity Road.