CN208001272U - Anti- latch circuit and integrated circuit - Google Patents
Anti- latch circuit and integrated circuit Download PDFInfo
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- CN208001272U CN208001272U CN201820377119.4U CN201820377119U CN208001272U CN 208001272 U CN208001272 U CN 208001272U CN 201820377119 U CN201820377119 U CN 201820377119U CN 208001272 U CN208001272 U CN 208001272U
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- 238000010586 diagram Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000024241 parasitism Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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Abstract
A kind of anti-latch circuit is disclosed, including:The first transistor, control terminal receive the first control voltage, and first end receives the first supply voltage;Second transistor with the first transistor type on the contrary, its control terminal receives the second control voltage, and is connected with the second end of the first transistor, and first end is connected with the control terminal of the first transistor, and second end receives the second supply voltage;Control circuit is arranged on the access formed by the first transistor and second transistor between the first supply voltage and the second supply voltage, for disconnecting access when the first control voltage and/or the second control voltage are beyond preset range.Anti- latch circuit provided by the utility model, control circuit is set on the access formed by the first transistor and second transistor between the first supply voltage and the second supply voltage, access is disconnected when the first control voltage and/or the second control voltage exceed preset range, to prevent the generation of latch-up under electrifying condition.
Description
Technical field
The utility model is related to technical field of integrated circuits, more particularly to a kind of anti-latch circuit and integrated circuit.
Background technology
With the development of IC manufacturing process, the size of chip is smaller and smaller, and chip package density and integrated level are higher and higher,
The possibility for generating latch-up (Latch up) will be increasing, and the possibility interfered with each other between module also can be increasingly
Greatly.There is parasitic transistor (also known as silicon-controlled, the abbreviation SCR of parasitism) in general integrated circuit, latch-up refers to parasitism
Bipolar transistor is triggered conducting, forms low impedance heavy current access between power vd D and ground GND, causes circuit can not
The phenomenon that working normally, or even burning.There are the various pieces of integrated circuit, including input for this parasitic bipolar transistor
End, output end, internal inverters etc..
Fig. 1 and Fig. 2 respectively illustrates parasitic silicon-controlled structural schematic diagram and equivalent circuit diagram in the prior art.Such as Fig. 1
Shown in Fig. 2, parasitic bipolar transistor is made of a PNP transistor and a lateral NPN transistor.Q1 is rectilinear crystal
It manages (Bipolar Junction Transistor-BJT), control terminal is N-type well region, and second end is P type substrate, and first end is
P-channel;Q2 is side formula transistor BJT, and control terminal is P type substrate, and second end is N-type well region, and first end is N-channel.More than
Two elements constitute controllable silicon SCR circuit, and when no external interference does not cause triggering, two BJT are in cut-off state, second end electricity
Stream is that the reverse leakage current of second end-control terminal is constituted, and current gain is very small, not will produce latch-up at this time.When wherein
When the second end electric current of one BJT is suddenly increased to certain value by external disturbance, another BJT can be fed back to, to make two
A BJT is connected because of triggering, and power vd D forms low impedance heavy current access between ground GND, generates latch-up.For example, working as Q1
Second end at voltage VPRise, voltage V at the second end of Q2NWhen decline, latch-up is generated.
Utility model content
In view of the above problems, the purpose of this utility model is to provide a kind of anti-latch circuit and integrated circuits, have anti-
Latch ability.
It is according to the present utility model in a first aspect, provide a kind of anti-latch circuit, including:The first transistor has control
End, first end and second end, control terminal receive the first control voltage, and first end receives the first supply voltage;Second transistor, with
For the first transistor type on the contrary, with control terminal, first end and second end, control terminal receives the second control voltage, and with the
The second end of one transistor is connected, and first end is connected with the control terminal of the first transistor, and second end receives the second supply voltage;Control
The access formed by the first transistor and second transistor between the first supply voltage and the second supply voltage is arranged in circuit processed
On, for the access to be disconnected when first controls voltage and/or the second control voltage exceeds preset range.
Preferably, the control circuit is arranged between first supply voltage and the first transistor, including the
One comparison module and first switch module, first comparison module are used to exceed preset first range in the first control voltage
When output for make first switch module turn off first switch signal;First switch module is used to receive first switch letter
Number when the first supply voltage and the first transistor are disconnected.
Preferably, first comparison module is first comparator, and the first switch module is first switch pipe;It is described
The first input end of first comparator receives the first control voltage, and the second input terminal receives the first reference voltage, output end and institute
State the control terminal connection of first switch pipe;The first end of the first switch pipe receives the first supply voltage, second end with it is described
The first end of the first transistor connects.
Preferably, the control circuit is arranged between second supply voltage and the second transistor, including the
Two comparison modules and second switch module, second comparison module are used to exceed preset second range in the second control voltage
When output for make second switch module turn off second switch signal;Second switch module is used to receive second switch letter
Number when the second supply voltage and second transistor are disconnected.
Preferably, second comparison module is the second comparator, and the second switch module is second switch pipe;It is described
The first input end of second comparator receives the second control voltage, and the second input terminal receives the second reference voltage, output end and institute
State the control terminal connection of second switch pipe;The first end of the second switch pipe receives the second supply voltage, second end with it is described
The first end of second transistor connects.
Preferably, the control circuit is arranged between first supply voltage and the first transistor and second
Between supply voltage and the second transistor, including the first comparison module, first switch module, the second comparison module and second
Switch module, first comparison module are used to export for making first when the first control voltage exceeds preset first range
The first switch signal of switch module shutdown;First switch module is used for the first power supply electricity when receiving first switch signal
Pressure is disconnected with the first transistor;Second comparison module is used to export when the second control voltage exceeds preset second range
Second switch signal for making second switch module turn off;Second switch module is used for will when receiving second switch signal
Second supply voltage is disconnected with second transistor.
Preferably, first comparison module is first comparator, and the first switch module is first switch pipe;It is described
Second comparison module is the second comparator, and the second switch module is second switch pipe;The first of the first comparator is defeated
Enter end and receive the first control voltage, the second input terminal receives the first reference voltage, the control of output end and the first switch pipe
End connection;The first end of the first switch pipe receives the first supply voltage, the first end of second end and the first transistor
Connection;The first input end of second comparator receives the second control voltage, and the second input terminal receives the second reference voltage, defeated
Outlet is connect with the control terminal of the second switch pipe;First end the second supply voltage of reception of the second switch pipe, second
End is connect with the first end of the second transistor.
Preferably, the first switch pipe is PMOS transistor, and the second switch pipe is NMOS transistor.
Preferably, the first transistor is PNP transistor, and the second transistor is NPN transistor.
Preferably, first supply voltage is more than the second supply voltage.
Another aspect according to the present utility model provides a kind of integrated circuit, including anti-latch circuit described above.
Anti- latch circuit and integrated circuit provided by the utility model, between the first supply voltage and the second supply voltage
Control circuit is set on the access formed by the first transistor and second transistor, first when the first transistor controls voltage
And/or the second of second transistor controls when voltage exceeds preset range and disconnects access, to prevent latch under electrifying condition
The generation of effect.
Description of the drawings
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows parasitic silicon-controlled structural schematic diagram in the prior art;
Fig. 2 shows the equivalent circuit diagrams that parasitism shown in FIG. 1 is silicon-controlled;
Fig. 3 shows the circuit diagram for the anti-latch circuit that the utility model first embodiment provides;
Fig. 4 shows the circuit diagram for the anti-latch circuit that the utility model second embodiment provides;
Fig. 5 shows the circuit diagram for the anti-latch circuit that the utility model 3rd embodiment provides.
Specific implementation mode
Hereinafter reference will be made to the drawings is more fully described the various embodiments of the utility model.In various figures, identical
Element is indicated using same or similar reference numeral.For the sake of clarity, the various pieces in attached drawing are not drawn to paint
System.
With reference to the accompanying drawings and examples, specific embodiment of the present utility model is described in further detail.
Fig. 3 shows the circuit diagram for the anti-latch circuit that the utility model first embodiment provides.As shown in Figure 1, described
Anti- latch circuit includes the first transistor Q1 and second transistor Q2 and control circuit 10.
There is the first transistor Q1 control terminal, first end and second end, control terminal to receive the first control voltage VN, first end
Receive the first supply voltage VH。
Second transistor Q2, with the first transistor type on the contrary, with control terminal, first end and second end, control termination
Receive the second control voltage VP, and be connected with the second end of the first transistor Q1, the control terminal of first end and the first transistor Q1
It is connected, second end receives the second supply voltage VL.In the present embodiment, the first transistor and second transistor are that type is opposite
Bipolar transistor, control terminal are base stage, and first end is emitter, and second end is collector.
In a preferred embodiment, the first transistor Q1 is positive-negative-positive bipolar transistor, and second transistor Q2 is
Bipolar npn transistor.
The first supply voltage V is arranged in control circuit 10HWith the second supply voltage VLBetween it is brilliant by the first transistor Q1 and second
On the access that body pipe Q2 is formed, for as the first control voltage VNAnd/or the second control voltage VPIt will be described when beyond preset range
Access disconnects.
The control circuit 10 is arranged in the first supply voltage VHBetween the first transistor Q1, including first
Comparison module 101 and first switch module 102.
Wherein, first comparison module 101 is used in the first control voltage VNIt is exported when beyond preset first range
First switch signal for making first switch module 102 turn off;First switch module 102 is used to receive first switch letter
Number when by the first supply voltage VHIt is disconnected with the first transistor Q1.
In the present embodiment, first comparison module 101 is first comparator U1, and the first switch module 102 is
First switch pipe M1.The first input end of the first comparator U1 receives the first control voltage VN, the second input terminal receives the
One reference voltage VRH, output end connect with the control terminal of the first switch pipe M1;
The first end of the first switch pipe M1 receives the first supply voltage VH, second end is with the first transistor Q1's
First end connects.
Work as VN< VRHWhen, the first switch signal control first switch pipe M1 shutdowns of first comparator U1 outputs.Wherein,
One reference voltage VRHThe first supply voltage V can be equal toH。
In a preferred embodiment, first switch pipe M1 is PMOS transistor, and the control terminal of first switch pipe M1 is
Grid, first end are source electrode, and second end is drain electrode.First switch signal is high level.
In a preferred embodiment, first switch pipe M1 is NMOS transistor, and the control terminal of first switch pipe M1 is
Grid, first end are drain electrode, and second end is source electrode.First switch signal is low level.
When occur voltage entanglement (such as electrostatic caused by or circuit operation mistake caused by voltage entanglement) when, may
Cause the first control voltage VNOr the second control voltage VPIt changes.If first causing the first control voltage VNDecline, when the first crystalline substance
When the first end of body pipe Q1 is more than the cut-in voltage of the first transistor Q1 with the pressure difference of control terminal electricity, the first transistor Q1 can be led
Logical, the first supply voltage will provide for the control terminal voltage V for leading to second transistor Q2 to the control terminal of second transistor Q2P
Rise, when the pressure difference of the control terminal of second transistor Q2 and first end is more than the cut-in voltage of second transistor Q2, second is brilliant
Body pipe Q2 can be connected, and generate latch path.If first causing the second control voltage VPRise, when second transistor Q2 control terminal with
When the pressure difference of first end is more than the cut-in voltage of second transistor Q2, second transistor Q2 can be connected, and the second supply voltage can carry
The control terminal for supplying the first transistor Q1, leads to the first control voltage VNDecline, the first end as the first transistor Q1 and control
When the pressure difference at end is more than the cut-in voltage of the first transistor Q1, the first transistor Q1 can be connected, and generate latch path.
Therefore, the first control voltage V can be directly or indirectly caused in the case of voltage entanglementNDecline, by VNWith the first ginseng
Examine voltage VRHIt is compared, works as VN< VRHWhen, first comparator U1 exports first switch signal, and control first switch pipe M1 is closed
It is disconnected so that current path is closed, and latch-up is not will produce.
Anti- latch circuit provided by the utility model, by first crystal between the first supply voltage and the second supply voltage
Control circuit is set on the access that pipe and second transistor are formed, when the control voltage of the first transistor exceeds preset first model
The first supply voltage and the first transistor are disconnected when enclosing, to prevent the generation of latch-up under electrifying condition.
Fig. 4 shows the circuit diagram for the anti-latch circuit that the utility model second embodiment provides.With first embodiment phase
Than difference lies in the control circuit 20 is arranged in the second supply voltage VLBetween the second transistor Q2, including
Second comparison module 201 and second switch module 202.
Wherein, second comparison module 201 is used in the second control voltage VPIt is exported when beyond preset second range
Second switch signal for making second switch module 202 turn off;Second switch module 202 is used to receive second switch letter
Number when by the second supply voltage VLIt is disconnected with second transistor Q2.
In the present embodiment, second comparison module 201 is the second comparator U2, and the second switch module 202 is
Second switch pipe M2.The first input end of the second comparator U2 receives the second control voltage VP, the second input terminal receives the
Two reference voltage VRL, output end connect with the control terminal of the second switch pipe M2;
The first end of the second switch pipe M2 receives the second supply voltage VL, second end is with the second transistor Q2's
First end connects.
Work as VP> VRLWhen, the second switch signal control second switch pipe M2 shutdowns of the second comparator U2 outputs.Wherein,
Two reference voltage VRLThe second supply voltage V can be equal toL。
In a preferred embodiment, second switch pipe M2 is PMOS transistor, and the control terminal of second switch pipe M2 is
Grid, first end are drain electrode, and second end is source electrode.Second switch signal is high level.
In a preferred embodiment, second switch pipe M2 is NMOS transistor, and the control terminal of second switch pipe M2 is
Grid, first end are source electrode, and second end is drain electrode.Second switch signal is low level.
The second control voltage V can directly or indirectly be caused in the case of voltage entanglementPRise, by VPWith second with reference to electricity
Press VRLIt is compared, as VP > VRLWhen, the second comparator U2 exports second switch signal, and the M2 shutdowns of control second switch pipe make
It obtains current path to close, not will produce latch-up.
Anti- latch circuit provided by the utility model, by first crystal between the first supply voltage and the second supply voltage
Control circuit is set on the access that pipe and second transistor are formed, when the control voltage of second transistor exceeds preset second model
The second common voltage and second transistor are disconnected when enclosing, to prevent the generation of latch-up under electrifying condition.
Fig. 5 shows the circuit diagram for the anti-latch circuit that the utility model 3rd embodiment provides.With first embodiment phase
Than difference lies in the control circuit includes first control circuit 10 and second control circuit 20, wherein first control circuit
10 are arranged in the first supply voltage VHBetween the first transistor Q1, including the first comparison module 101 and first is opened
Close module 102.Second control circuit 20 is arranged in the second supply voltage VLBetween the second transistor Q2, including the
Two comparison modules 201 and second switch module 202.
Wherein, first comparison module 101 is used in the first control voltage VNIt is exported when beyond preset first range
First switch signal for making first switch module 102 turn off;First switch module 102 is used to receive first switch letter
Number when by the first supply voltage VHIt is disconnected with the first transistor Q1.
In the present embodiment, first comparison module 101 is first comparator U1, and the first switch module 102 is
First switch pipe M1.The first input end of the first comparator U1 receives the first control voltage VN, the second input terminal receives the
One reference voltage VRH, output end connect with the control terminal of the first switch pipe M1;
The first end of the first switch pipe M1 receives the first supply voltage VH, second end is with the first transistor Q1's
First end connects.
Work as VN< VRHWhen, the first switch signal control first switch pipe M1 shutdowns of first comparator U1 outputs.Wherein,
One reference voltage VRHThe first supply voltage V can be equal toH。
In a preferred embodiment, first switch pipe M1 is PMOS transistor, and the control terminal of first switch pipe M1 is
Grid, first end are source electrode, and second end is drain electrode.First switch signal is high level.
In a preferred embodiment, first switch pipe M1 is NMOS transistor, and the control terminal of first switch pipe M1 is
Grid, first end are drain electrode, and second end is source electrode.First switch signal is low level.
Second comparison module 201 is used in the second control voltage VPOutput is for making when beyond preset second range
The second switch signal that second switch module 202 turns off;Second switch module 202 is used for will when receiving second switch signal
Second supply voltage VLIt is disconnected with second transistor Q2.
In the present embodiment, second comparison module 201 is the second comparator U2, and the second switch module 202 is
Second switch pipe M2.The first input end of the second comparator U2 receives the second control voltage VP, the second input terminal receives the
Two reference voltage VRL, output end connect with the control terminal of the second switch pipe M2;
The first end of the second switch pipe M2 receives the second supply voltage VL, second end is with the second transistor Q2's
First end connects.
Work as VP> VRLWhen, the second switch signal control second switch pipe M2 shutdowns of the second comparator U2 outputs.Wherein,
Two reference voltage VRLThe second supply voltage V can be equal toL。
In a preferred embodiment, second switch pipe M2 is PMOS transistor, and the control terminal of second switch pipe M2 is
Grid, first end are drain electrode, and second end is source electrode.Second switch signal is high level.
In a preferred embodiment, second switch pipe M2 is NMOS transistor, and the control terminal of second switch pipe M2 is
Grid, first end are source electrode, and second end is drain electrode.Second switch signal is low level.
The first control voltage V can directly or indirectly be caused in the case of voltage entanglementNDecline and second controls voltage VP
Rise, by VNWith the first reference voltage VRHIt is compared and by VPWith the second reference voltage VRLIt is compared, works as VN< VRHWhen,
First comparator U1 exports first switch signal, the M1 shutdowns of control first switch pipe, and works as VP > VRLWhen, the second comparator U2
Export second switch signal, control second switch pipe M2 shutdowns so that current path is closed, and latch-up is not will produce.
Anti- latch circuit provided by the utility model, by first crystal between the first supply voltage and the second supply voltage
Control circuit is set on the access that pipe and second transistor are formed, when the control voltage of the first transistor exceeds preset first model
By the first supply voltage and the first transistor disconnection and when the control voltage of second transistor exceeds preset second model when enclosing
The second common voltage and second transistor are disconnected when enclosing, to prevent the generation of latch-up under electrifying condition.
The utility model also provides a kind of integrated circuit, including the anti-latch circuit described in any of the above-described embodiment.
It is as described above according to the embodiments of the present invention, these embodiments there is no all details of detailed descriptionthe,
The specific embodiment that the utility model is only described is not limited yet.Obviously, as described above, many modification and change can be made
Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer
With to enable skilled artisan to utilize the utility model and repairing on the basis of the utility model well
Change use.The utility model is limited only by the claims and their full scope and equivalents.
Claims (11)
1. a kind of anti-latch circuit, which is characterized in that including:
There is the first transistor control terminal, first end and second end, control terminal to receive the first control voltage, and first end receives the
One supply voltage;
Second transistor, with the first transistor type on the contrary, with control terminal, first end and second end, control terminal receives second
Voltage is controlled, and is connected with the second end of the first transistor, first end is connected with the control terminal of the first transistor, the second termination
Receive the second supply voltage;
Control circuit is formed between the first supply voltage of setting and the second supply voltage by the first transistor and second transistor
On access, for the access to be disconnected when first controls voltage and/or the second control voltage exceeds preset range.
2. anti-latch circuit according to claim 1, which is characterized in that the control circuit setting is in first power supply
Between voltage and the first transistor, including the first comparison module and first switch module,
First comparison module is used to export for making first switch when the first control voltage exceeds preset first range
The first switch signal of module shutdown;
First switch module is used to disconnect the first supply voltage and the first transistor when receiving first switch signal.
3. anti-latch circuit according to claim 2, which is characterized in that first comparison module is first comparator,
The first switch module is first switch pipe;
The first input end of the first comparator receives the first control voltage, and the second input terminal receives the first reference voltage, defeated
Outlet is connect with the control terminal of the first switch pipe;
The first end of the first switch pipe receives the first supply voltage, and second end and the first end of the first transistor connect
It connects.
4. anti-latch circuit according to claim 1, which is characterized in that the control circuit setting is in second power supply
Between voltage and the second transistor, including the second comparison module and second switch module,
Second comparison module is used to export for making second switch when the second control voltage exceeds preset second range
The second switch signal of module shutdown;
Second switch module is used to disconnect the second supply voltage and second transistor when receiving second switch signal.
5. anti-latch circuit according to claim 4, which is characterized in that second comparison module is the second comparator,
The second switch module is second switch pipe;
The first input end of second comparator receives the second control voltage, and the second input terminal receives the second reference voltage, defeated
Outlet is connect with the control terminal of the second switch pipe;
The first end of the second switch pipe receives the second supply voltage, and second end and the first end of the second transistor connect
It connects.
6. anti-latch circuit according to claim 1, which is characterized in that the control circuit setting is in first power supply
Between voltage and the first transistor and between the second supply voltage and the second transistor, including first compares mould
Block, first switch module, the second comparison module and second switch module,
First comparison module is used to export for making first switch when the first control voltage exceeds preset first range
The first switch signal of module shutdown;
First switch module is used to disconnect the first supply voltage and the first transistor when receiving first switch signal;
Second comparison module is used to export for making second switch when the second control voltage exceeds preset second range
The second switch signal of module shutdown;
Second switch module is used to disconnect the second supply voltage and second transistor when receiving second switch signal.
7. anti-latch circuit according to claim 6, which is characterized in that first comparison module is first comparator,
The first switch module is first switch pipe;Second comparison module is the second comparator, and the second switch module is
Second switch pipe;
The first input end of the first comparator receives the first control voltage, and the second input terminal receives the first reference voltage, defeated
Outlet is connect with the control terminal of the first switch pipe;
The first end of the first switch pipe receives the first supply voltage, and second end and the first end of the first transistor connect
It connects;
The first input end of second comparator receives the second control voltage, and the second input terminal receives the second reference voltage, defeated
Outlet is connect with the control terminal of the second switch pipe;
The first end of the second switch pipe receives the second supply voltage, and second end and the first end of the second transistor connect
It connects.
8. anti-latch circuit according to claim 7, which is characterized in that the first switch pipe is PMOS transistor, institute
It is NMOS transistor to state second switch pipe.
9. anti-latch circuit according to claim 1, which is characterized in that the first transistor is PNP transistor, institute
It is NPN transistor to state second transistor.
10. anti-latch circuit according to claim 9, which is characterized in that first supply voltage is more than the second power supply
Voltage.
11. a kind of integrated circuit includes the anti-latch circuit as described in any one of claim 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820377119.4U CN208001272U (en) | 2018-03-20 | 2018-03-20 | Anti- latch circuit and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820377119.4U CN208001272U (en) | 2018-03-20 | 2018-03-20 | Anti- latch circuit and integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208001272U true CN208001272U (en) | 2018-10-23 |
Family
ID=63839880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820377119.4U Withdrawn - After Issue CN208001272U (en) | 2018-03-20 | 2018-03-20 | Anti- latch circuit and integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208001272U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108270422A (en) * | 2018-03-20 | 2018-07-10 | 北京集创北方科技股份有限公司 | Anti- latch circuit and integrated circuit |
-
2018
- 2018-03-20 CN CN201820377119.4U patent/CN208001272U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108270422A (en) * | 2018-03-20 | 2018-07-10 | 北京集创北方科技股份有限公司 | Anti- latch circuit and integrated circuit |
| WO2019179432A1 (en) * | 2018-03-20 | 2019-09-26 | 北京集创北方科技股份有限公司 | Anti-latch circuit and integrated circuit |
| CN108270422B (en) * | 2018-03-20 | 2024-07-12 | 北京集创北方科技股份有限公司 | Latch-up prevention circuit and integrated circuit |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20181023 Effective date of abandoning: 20240712 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20181023 Effective date of abandoning: 20240712 |