CN207896684U - A kind of pulse activation and dormant circuit - Google Patents
A kind of pulse activation and dormant circuit Download PDFInfo
- Publication number
- CN207896684U CN207896684U CN201721749827.8U CN201721749827U CN207896684U CN 207896684 U CN207896684 U CN 207896684U CN 201721749827 U CN201721749827 U CN 201721749827U CN 207896684 U CN207896684 U CN 207896684U
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- China
- Prior art keywords
- resistance
- diode
- module
- nmos tube
- pmos tube
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
A kind of pulse activation and dormant circuit, including active module, voltage reduction module and self-locking module, it is characterised in that：The active module includes optocoupler U1, resistance R1, resistance R3, diode D1, diode D2, resistance R2, resistance R4, NMOS tube Q2, PMOS tube Q1, it can be activated and be powered on by action of low-voltage pulse the utility model proposes one kind, when system judges to need lower electricity system can with complete independently under electronic work, it ensure that product is safe and reliable, battery capacity is saved to the greatest extent, ensure battery life, realizes intelligent control.
Description
Technical field
The utility model is related to the technical fields of battery powered control system, specifically, be related to a kind of pulse activation and
Dormant circuit.
Background technology
In existing battery-powered control system, discharged back using normal electricity output or artificial being connected to shorting switch
The scheme on road.So whole system can not achieve intelligent switching control, and since battery capacity is limited, electricity can be lost when standby
Pond electricity causes battery over-discharge even to damage battery, and system often charge the when of using and also has certain risk.
Invention content
In order to overcome the above-mentioned problems in the prior art, the utility model, which provides one kind, can pass through low pressure
The pulse activation and dormant circuit that pulse activation powers on.
A kind of pulse activation and dormant circuit, including active module, voltage reduction module and self-locking module, the active module
Including optocoupler U1, resistance R1, resistance R3, diode D1, diode D2, resistance R2, resistance R4, NMOS tube Q2, PMOS tube Q1, institute
The optocoupler U1 primary side positive and negative terminals stated are connected with sensitizing pulse, and primary side anode is connecting cell voltage just, the series connection of primary side negative terminal
It is grounded after resistance R1, R3, the anode of the tie point connection diode D1 of described resistance R1, R3, the cathode connection of the diode
The gate pole of NMOS tube Q2, the gate pole of connection PMOS tube Q1, the source of NMOS tube Q2 after the drain series resistance R2 of the NMOS tube Q2
Pole is grounded, and the source electrode of the PMOS tube Q1 and one end of resistance R4 are connected to cell voltage output cathode simultaneously, and resistance R4's is another
One end is connected to the gate pole of PMOS tube Q1, and the source electrode of the PMOS tube Q1 is connected to the input terminal of the voltage reduction module, the drop
The output end of die block is connected to the feeder ear of self-locking module, and the GPIO mouths of the self-locking module connect the anode of diode D2,
The cathode of the diode D2 is connected to the gate pole of the NMOS tube Q2.
Preferably, the voltage reduction module is LDO.
Preferably, the self-locking module is MCU.
Preferably, the resistance value proportioning of the resistance R1 and R3 will can open NMOS tube Q2 in battery voltage range.
Preferably, the resistance value proportioning of the resistance R2 and R4 will can open PMOS tube Q1 in battery voltage range.
A kind of pulse activation described in the utility model and dormant circuit, it is proposed that one kind can be activated by action of low-voltage pulse
The technical solution powered on, when system judges to need lower electricity system can with complete independently under electronic work, ensure that product uses peace
It is complete reliable, battery capacity is saved to the greatest extent, ensures battery life, realizes intelligent control.
Description of the drawings
Fig. 1 is the circuit diagram of embodiment 1.
Specific implementation mode
To further appreciate that the content of the utility model, the utility model is described in detail in conjunction with the accompanying drawings and embodiments.
It should be understood that embodiment be only to the utility model explain and and it is non-limiting.
Embodiment 1
As shown in Figure 1, present embodiments providing a kind of pulse activation and dormant circuit, including active module 1, voltage reduction module
2 and self-locking module 3, the active module 1 includes optocoupler U1, resistance R1, resistance R3, diode D1, diode D2, resistance
R2, resistance R4, NMOS tube Q2, PMOS tube Q1, the optocoupler U1 primary side positive and negative terminals are connected with sensitizing pulse, primary side anode
It connects cell voltage just, is grounded after primary side negative terminal series resistance R1, R3, the tie point of described resistance R1, R3 connect diode
The anode of D1, the cathode of the diode connect the gate pole of NMOS tube Q2, connect after the drain series resistance R2 of the NMOS tube Q2
The gate pole of PMOS tube Q1 is connect, the source electrode ground connection of NMOS tube Q2, the source electrode of the PMOS tube Q1 and one end of resistance R4 connect simultaneously
To cell voltage output cathode, the other end of resistance R4 is connected to the gate pole of PMOS tube Q1, the source electrode connection of the PMOS tube Q1
To the input terminal of the voltage reduction module, the output end of the voltage reduction module 2 is connected to the feeder ear of self-locking module 3, the self-locking
The anode of the GPIO mouths connection diode D2 of module 3, the cathode of the diode D2 are connected to the gate pole of the NMOS tube Q2, institute
The voltage reduction module 2 stated is LDO, and the self-locking module 3 is MCU, and the resistance value proportioning of the resistance R1 and R3 will be in battery electricity
The resistance value proportioning that pressure range interior energy opens NMOS tube Q2, the resistance R2 and R4 will can open PMOS in battery voltage range
Pipe Q1.
In the present embodiment, when system, which needs to activate, to be powered on, optocoupler primary side receives sensitizing pulse, primary side conducting, resistance
R1 and R3 partial pressure gained voltages are exported by diode D1 gives NMOS tube Q2 gate poles, and Q2 is made to be connected.After further Q2 conductings,
Resistance R4 and R2 partial pressure gained voltage makes PMOS tube be connected.It is further to pass through power supply of the LDO output voltages to MCU, MCU electrifications
It is exported afterwards by diode D2 by GPIO mouthfuls of output high level and gives NMOS tube gate pole, formed stable state, power on sensitizing pulse at this time
Disappearance will not cause system cut-off, complete power up.
Conversely, when system judges to need lower electricity, MCU is output to by GPIO mouthfuls of output low levels by diode D2
The gate pole of NMOS tube, Q2 pipes disconnect, and further Q1 is disconnected, and electricity is completed under system.
In the present embodiment, the type selecting of the PMOS tube Q1 depends on system operating current, and the type selecting of the optocoupler U1 depends on
Time in sensitizing pulse and amplitude.
Schematically the utility model and embodiments thereof are described above, description is not limiting, attached drawing
Shown in also be the utility model one of embodiment, actual structure is not limited to this.So if this field
Those of ordinary skill enlightened by it, without deviating from the purpose of the present invention, not inventively design
Frame mode similar with the technical solution and embodiment, all should belong to the protection range of the utility model.
Claims (5)
1. a kind of pulse activation and dormant circuit, including active module, voltage reduction module and self-locking module, it is characterised in that：It is described
Active module include optocoupler U1, resistance R1, resistance R3, diode D1, diode D2, resistance R2, resistance R4, NMOS tube Q2,
PMOS tube Q1, the optocoupler U1 primary side positive and negative terminals are connected with sensitizing pulse, and primary side anode is connecting cell voltage just, secondary
It is grounded after negative terminal series resistance R1, R3 of side, the anode of the tie point connection diode D1 of described resistance R1, R3, the diode
Cathode connection NMOS tube Q2 gate pole, the gate pole of connection PMOS tube Q1 after the drain series resistance R2 of the NMOS tube Q2,
The source electrode of NMOS tube Q2 is grounded, and the source electrode of the PMOS tube Q1 and one end of resistance R4 are being connected to cell voltage output just simultaneously
Pole, the other end of resistance R4 are connected to the gate pole of PMOS tube Q1, and the source electrode of the PMOS tube Q1 is connected to the voltage reduction module
Input terminal, the output end of the voltage reduction module are connected to the feeder ear of self-locking module, the GPIO mouths connection two of the self-locking module
The anode of pole pipe D2, the cathode of the diode D2 are connected to the gate pole of the NMOS tube Q2.
2. a kind of pulse activation according to claim 1 and dormant circuit, it is characterised in that：The voltage reduction module is
LDO。
3. a kind of pulse activation according to claim 1 and dormant circuit, it is characterised in that：The self-locking module is
MCU。
4. a kind of pulse activation according to claim 1 and dormant circuit, it is characterised in that：The resistance R1's and R3
Resistance value proportioning will can open NMOS tube Q2 in battery voltage range.
5. a kind of pulse activation according to claim 1 and dormant circuit, it is characterised in that：The resistance R2's and R4
Resistance value proportioning will can open PMOS tube Q1 in battery voltage range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721749827.8U CN207896684U (en) | 2017-12-15 | 2017-12-15 | A kind of pulse activation and dormant circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721749827.8U CN207896684U (en) | 2017-12-15 | 2017-12-15 | A kind of pulse activation and dormant circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207896684U true CN207896684U (en) | 2018-09-21 |
Family
ID=63548729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721749827.8U Expired - Fee Related CN207896684U (en) | 2017-12-15 | 2017-12-15 | A kind of pulse activation and dormant circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207896684U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109049020A (en) * | 2018-10-22 | 2018-12-21 | 浙江亚尚智能科技有限公司 | The control circuit of electric shaver |
| EP3823130A1 (en) * | 2019-11-15 | 2021-05-19 | Globe (Jiangsu) Co., Ltd. | Battery pack charging and discharging protection system |
-
2017
- 2017-12-15 CN CN201721749827.8U patent/CN207896684U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109049020A (en) * | 2018-10-22 | 2018-12-21 | 浙江亚尚智能科技有限公司 | The control circuit of electric shaver |
| CN109049020B (en) * | 2018-10-22 | 2023-09-05 | 浙江亚尚智能科技有限公司 | Control circuit of electric shaver |
| EP3823130A1 (en) * | 2019-11-15 | 2021-05-19 | Globe (Jiangsu) Co., Ltd. | Battery pack charging and discharging protection system |
| US11721986B2 (en) | 2019-11-15 | 2023-08-08 | Globe (Jiangsu) Co., Ltd | Battery pack charging and discharging protection system |
| EP4344015A3 (en) * | 2019-11-15 | 2024-07-10 | Globe (Jiangsu) Co., Ltd. | Battery pack charging and discharging protection system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180921 Termination date: 20211215 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |