CN207835897U - High-frequency synchronous system and synchrotron equipment comprising it - Google Patents

Abstract

The utility model provides a kind of high-frequency synchronous system, including：Prime accelerator Zero-cross comparator circuit is configured to the high frequency waveforms signal of input prime accelerator, exports the zero phase of the prime accelerator after Zero-cross comparator；Rear class accelerator Zero-cross comparator circuit is configured to the high frequency waveforms signal of input rear class accelerator, exports the zero phase of the rear class accelerator after Zero-cross comparator；Master controller FPGA, input the zero phase of the zero phase and rear class accelerator of prime accelerator, example trigger signal is also inputted, is configured to export respectively after delay and meets signal to kicker magnet (Kicker) power-supply controller of electric of prime accelerator and rear class accelerator.It is synchronized by the clock, the perimeter of two synchrotrons can be arbitrary proportion, and injecting accumulation number can be more than perimeter ratio, the higher strong gain of stream of acquisition.

Description

High-frequency synchronous system and synchrotron equipment comprising it

Technical field

The utility model designs synchrotron field, further to the high-frequency synchronous system between a kind of synchrotron System.

Background technology

In order to obtain higher energy, synchrotron is frequently with cascade mode, by adding in prime synchrotron The beam group that speed is completed draws, and continues to accelerate in the rear class synchrotron of injection.In this beam rolls into a ball transfer process, need simultaneously Meet two conditions：1. prime synchrotron extraction elements action moment is to draw required high-frequency phase；Add 2. rear class synchronizes Fast device injection element action moment is high-frequency phase needed for injection.Conventional way is the perimeter design of two synchrotrons For simple integer ratio, the clock of two synchrotrons is synchronized with same crystal oscillator.The method of synchronization it is maximum the disadvantage is that： The perimeter ratio of two synchrotrons is simple integer, limits the flexibility of synchrotron design；Rear class synchrotron Strong gain is flowed no more than perimeter ratio.

During the interfascicular fasciculus group transfer of synchrotron, need to meet simultaneously prime synchrotron extraction phase with after Grade synchrotron injects phase, and traditional scheme is that two synchrotrons use the same crystal oscillator as clock, this The result is that needing to set perimeter to simple integer ratio in two synchrotron design processes caused by sample, significantly limit The flexibility of synchronous ring design, in addition rear class accelerator injection accumulate number less than or equal to the perimeter ratio, it is low to flow strong gain.

Utility model content

(1) technical problems to be solved

In view of this, the purpose of this utility model is to provide a kind of high-frequency synchronous system and including its synchrotron Equipment, at least partly to solve the problems, such as techniques discussed above.

(2) technical solution

One side according to the present utility model provides a kind of high-frequency synchronous system, including：Prime accelerator Zero-cross comparator electricity Road is configured to the high frequency waveforms signal of input prime accelerator, exports the zero phase of the prime accelerator after Zero-cross comparator；Rear class Accelerator Zero-cross comparator circuit is configured to the high frequency waveforms signal of input rear class accelerator, exports the rear class after Zero-cross comparator and adds The zero phase of fast device；Master controller FPGA inputs the zero phase of the zero phase and rear class accelerator of prime accelerator, also inputs thing Example trigger signal is configured to export respectively after delay and meets signal to the kicker magnet of prime accelerator and rear class accelerator (Kicker) power-supply controller of electric.

In a further embodiment, further include pilot controller, coupled with the master controller FPGA, be used for master control Device FPGA processed is communicated with the other equipment for being connected to pilot controller.

In a further embodiment, the pilot controller is configured to one host computer of connection, the master for that will acquire The signal of controller FPGA is sent to host computer, is additionally operable to the parameter that host computer issues passing to FPGA.

In a further embodiment, master controller FPGA acquisition meets signal and includes：It captures rear class and synchronizes and add After fast device high frequency waveforms zero phase, by delay, capture window is opened, if the period interior energy captures prime sync plus white Device high frequency waveforms zero phase signal, and example trigger signal exists, then and output meets signal.

It is according to the present utility model in another aspect, provide a kind of high-frequency synchronous system, including：

Master controller FPGA is configured to the zero phase of the zero phase and rear class accelerator of input prime accelerator, inputs thing Example trigger signal is additionally configured to export respectively after delay and meets signal to prime accelerator and rear class accelerator；Auxiliary control Device is coupled with the master controller, is additionally configured to one host computer of connection, is configured to keep master controller FPGA logical with the host computer Letter.

Another aspect according to the present utility model provides a kind of synchrotron equipment, including：

Prime accelerator and rear class accelerator accelerate in the prime synchrotron beam completed group to draw, after injection Grade synchrotron；

With the high-frequency synchronous system of any of the above.

It is according to the present utility model in another aspect, provide a kind of synchrotron equipment, including：

Prime accelerator, including built-in high frequency low level control field programmable gate array, before determining and exporting The zero phase of grade accelerator；

Rear class accelerator, including built-in high frequency low level control field programmable gate array, after determining and exporting Rear class accelerator injects after drawing in the zero phase of grade accelerator, the beam group that the acceleration in the prime accelerator is completed；

And above-mentioned high-frequency synchronous system.

(3) advantageous effect

The high-frequency synchronous system of the utility model acquires the clock of two synchrotrons, full with prime synchrotron Sufficient extraction condition, rear class synchrotron meet injection condition and triggering example does and meets, triggering prime synchrotron The injection element of extraction elements and rear class synchrotron acts, in this way, the perimeter of two synchrotrons can be arbitrary proportion, And perimeter ratio can be more than by injecting accumulation number, obtain the higher strong gain of stream.

Description of the drawings

Fig. 1 is the high-frequency synchronous system block diagram of one embodiment of the utility model.

Fig. 2 is the high-frequency synchronous system block diagram of another embodiment of the utility model.

Fig. 3 is the master controller FPGA phase acquisition algorithm structure figures of the utility model embodiment.

Specific implementation mode

Some embodiments of the present disclosure are described more detail below.In next explanation, some concrete details, such as The design parameter of particular circuit configurations and these circuit elements in embodiment is all used to provide embodiment of the disclosure more preferable Understanding.Those skilled in the art are appreciated that even if lacking some details or other methods, element, material In the case of combining, the embodiments of the present invention can also be implemented.

It should be appreciated by those skilled in the art disclose in one or more embodiment of the utility model specification Each specific features, structure or parameter, step etc. can combine in any suitable manner.In addition, in the utility model In specification and claim, " coupling " word, which means to realize by way of electrical or non-electrical, directly or indirectly to be connected It connects."one" is not used to refer in particular to individually, but may include plural form." circuit " means at least there is one or more Source or passive element are coupled together to provide the structure of specific function." signal " can at least refer to including electric current, voltage, electricity Lotus, temperature, data, pressure or other types of signal.It should be appreciated by those skilled in the art, enumerate above to this reality The explanation of the term described in novel is only exemplary, and is not used to carry out each term absolute restriction.

The main thought of the utility model is that independent clock system, high-frequency synchronous system may be used in two synchrotrons The clock for acquiring two synchrotrons simultaneously meets extraction condition with prime synchrotron, rear class synchrotron meets note Enter condition and triggering example does and meets, triggers the extraction elements of prime synchrotron and the injection member of rear class synchrotron Part acts.In this way, the perimeter of two synchrotrons can be arbitrary proportion, and inject accumulation number can be more than perimeter ratio, Obtain the higher strong gain of stream.

According to the one side of the utility model embodiment, a kind of high-frequency synchronous system is provided, including：Prime accelerator zero passage Comparison circuit is configured to the high frequency waveforms signal of input prime accelerator, exports zero phase of the prime accelerator after Zero-cross comparator Position；Rear class accelerator Zero-cross comparator circuit is configured to the high frequency waveforms signal of input rear class accelerator, after exporting Zero-cross comparator The zero phase of rear class accelerator；And master controller FPGA, input zero phase of the zero phase and rear class accelerator of prime accelerator Position also inputs example trigger signal, is configured to export respectively after delay and meets signal to prime accelerator and rear class accelerator Kicker magnet power-supply controller of electric.It is specifically described below with reference to attached drawing 1.

As shown in Figure 1, the high-frequency synchronous system of the utility model includes the signal shaping of synchrotron high frequency waveforms, zero passage Comparison circuit, master controller FPGA, pilot controller ARM.Relationship between above-mentioned each unit is as follows：Prime is synchronous with rear class to be added Fast device high frequency sinusoidal signal is fed to high-frequency synchronous system through coaxial cable, obtains front stage synchronization respectively by Zero-cross comparator and adds Fast device high frequency zero phase, is then sent to FPGA and is met, this meets signal and meets again with example trigger signal, after delay It is sent to front stage synchrotron kicker magnet power-supply controller of electric respectively.The effect of ARM is the system shape for acquiring FPGA in real time State is sent to host computer, and the parameters such as delay that host computer issues are passed to FPGA.

According to the utility model embodiment in another aspect, provide a kind of synchrotron equipment, including：Prime accelerator With rear class accelerator, the beam group that the acceleration in the prime synchrotron is completed draws, and injects rear class synchrotron；And High-frequency synchronous system described in Fig. 1.

According to the another aspect of the utility model embodiment, a kind of high-frequency synchronous system is provided, including：Master controller The zero phase of FPGA, the zero phase and rear class accelerator that are configured to input prime accelerator also input example trigger signal, configure Meet signal to the controller of prime accelerator and rear class accelerator after delay to export respectively；With the master controller FPGA Connection, for the communication between master controller FPGA and the host computer for being connected to pilot controller.

As shown in Fig. 2, can by modifying to high frequency control panel, make FPGA (FPGA is different from main controller FPGA, It belongs to synchrotron high frequency low level control system, is the source of sine voltage signal) built in DDS phase zero passages when it is defeated Go out a pulse, can thus simplify Zero-cross comparator function, while improving system stability.

FPGA (field programmable gate array) is the master controller of the high-frequency synchronous system, and phase acquisition algorithm structure is such as Shown in Fig. 3.Rear class synchrotron high frequency waveforms zero phase capture after, through delay d1, open capture window 2, if this when Between section interior energy capture prime synchrotron high frequency waveforms zero phase signal, and example trigger signal exists, then exports symbol Close signal (d2 and d3).2 size of window is captured by adjusting, with regulating time synchronization accuracy and signal frequency can be met.Simultaneously Signal d2 and d3 will be met to be exported respectively to prime synchrotron kicker magnet power supply and rear class synchrotron kicker magnet Power supply.

According to the another aspect of the utility model embodiment, a kind of synchrotron equipment is provided, including：Prime accelerates Device, including built-in Direct Digital Synthesizer, the zero phase for obtaining prime accelerator；Rear class accelerator, including Built-in Direct Digital Synthesizer, the zero phase for obtaining prime accelerator, in the prime synchrotron Accelerate the beam completed group to draw, injects the high-frequency synchronous system described in rear class synchrotron and Fig. 2.

Particular embodiments described above has carried out into one the purpose of this utility model, technical solution and advantageous effect Step is described in detail, it should be understood that the foregoing is merely specific embodiment of the utility model, are not limited to this reality With novel, within the spirit and principle of the utility model, any modification, equivalent substitution, improvement and etc. done should all include It is within the protection scope of the utility model.

Claims (7)

1. a kind of high-frequency synchronous system, which is characterized in that including：

Prime accelerator Zero-cross comparator circuit is configured to the high frequency waveforms signal of input prime accelerator, after exporting Zero-cross comparator Prime accelerator zero phase；

Rear class accelerator Zero-cross comparator circuit is configured to the high frequency waveforms signal of input rear class accelerator, after exporting Zero-cross comparator Rear class accelerator zero phase；

Master controller FPGA inputs the zero phase of the zero phase and rear class accelerator of prime accelerator, also inputs example triggering letter Number, it is configured to export respectively after delay and meets signal to the kicker magnet of prime accelerator and rear class accelerator（Kicker）Electricity Source controller.

2. high-frequency synchronous system according to claim 1, which is characterized in that further include pilot controller, with the master control Device FPGA couplings processed, for the communication between master controller FPGA and the other equipment for being connected to pilot controller.

3. high-frequency synchronous system according to claim 2, which is characterized in that the pilot controller is configured in connection one Position machine is additionally operable to the parameter for issuing host computer and transmits for the signal of the master controller FPGA of acquisition to be sent to host computer To FPGA.

4. high-frequency synchronous system according to claim 1, which is characterized in that the master controller FPGA acquisitions meet signal Including：After capturing rear class synchrotron high frequency waveforms zero phase, by delay, capture window is opened, if in the period Prime synchrotron high frequency waveforms zero phase signal can be captured, and example trigger signal exists, then output meets signal.

5. a kind of high-frequency synchronous system, which is characterized in that including：

Master controller FPGA, is configured to the zero phase of the zero phase and rear class accelerator of input prime accelerator, and input example touches It signals, is additionally configured to export respectively after delay and meets signal to prime accelerator and rear class accelerator；

Pilot controller is coupled with the master controller, is additionally configured to one host computer of connection, be configured to make master controller FPGA with The host computer communication.

6. a kind of synchrotron equipment, it is characterised in that including：

Prime accelerator and rear class accelerator accelerate in the prime synchrotron beam completed group to draw, and injection rear class is same Walk accelerator；

Any high-frequency synchronous systems of claim 1-4.

7. a kind of synchrotron equipment, it is characterised in that including：

Prime accelerator, including built-in high frequency low level control field programmable gate array, add for determining and exporting prime The zero phase of fast device；

Rear class accelerator, including built-in high frequency low level control field programmable gate array, add for determining and exporting rear class Rear class accelerator injects after drawing in the zero phase of fast device, the beam group that the acceleration in the prime accelerator is completed；

High-frequency synchronous system described in claim 5.