CN207833929U - Offset voltage adaptive digital calibration type sense amplifier - Google Patents

Offset voltage adaptive digital calibration type sense amplifier Download PDF

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CN207833929U
CN207833929U CN201820411822.2U CN201820411822U CN207833929U CN 207833929 U CN207833929 U CN 207833929U CN 201820411822 U CN201820411822 U CN 201820411822U CN 207833929 U CN207833929 U CN 207833929U
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pmos transistor
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transistor
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彭春雨
孔令雨
卢文娟
王永俊
吴秀龙
蔺智挺
高珊
陈军宁
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Anhui University
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Abstract

本实用新型公开了一种失调电压自适应数字校准型灵敏放大器,是一种可以有效降低失调电压的灵敏放大器电路结构,该结构利用简单的外围电路实现灵敏放大器失调电压的校准补偿以及补偿状态锁存操作,达到了大幅度降低失调电压的目的;同时由于失调电压的降低,有效的提升了静态随机存储器读取电路的设计裕度,进而降低了单元读取时产生的功耗消耗,并提升了静态随机存储器的数据读取速度。

The utility model discloses an offset voltage self-adaptive digital calibration type sensitive amplifier, which is a sensitive amplifier circuit structure that can effectively reduce the offset voltage. The structure uses a simple peripheral circuit to realize the calibration compensation of the offset voltage of the sensitive amplifier and the compensation state lock The memory operation achieves the purpose of greatly reducing the offset voltage; at the same time, due to the reduction of the offset voltage, the design margin of the SRAM read circuit is effectively improved, thereby reducing the power consumption generated when the unit is read, and improving The data read speed of SRAM is improved.

Description

失调电压自适应数字校准型灵敏放大器Offset Voltage Adaptive Digital Calibration Sensitive Amplifier

技术领域technical field

本实用新型涉及集成电路设计领域,尤其涉及一种失调电压自适应数字校准型灵敏放大器。The utility model relates to the field of integrated circuit design, in particular to an offset voltage adaptive digital calibration type sensitive amplifier.

背景技术Background technique

近些年来集成电路行业的高速发展,静态随机存储器(Static Random AccessMemory,缩写为SRAM)高速低功耗的特性在电路设计中扮演越来越重要的成分,SRAM的读操作相对于写操作需要更多时间,为了提升SRAM的性能,在数据读出路径中通常采用灵敏放大器(Sense Amplifier,缩写为SA),在理想条件下,只需要输入微小的电压差,灵敏放大器就能反馈出逻辑上的“0”和“1”。但是,由于工艺参数的波动,使得如跨导、阈值电压等器件参数产生失配,对于SA而言,将会产生失调电压,进而引起小摆幅输入信号被灵敏放大器的错误放大。传统电压型SA电路的结构如图1所示;为了减小SA的失调电压,现存在以下几种技术:With the rapid development of the integrated circuit industry in recent years, the high-speed and low-power characteristics of Static Random Access Memory (SRAM) play an increasingly important role in circuit design. The read operation of SRAM requires more For a long time, in order to improve the performance of SRAM, a sense amplifier (Sense Amplifier, abbreviated as SA) is usually used in the data readout path. Under ideal conditions, only a small voltage difference needs to be input, and the sense amplifier can feedback the logic. "0" and "1". However, due to the fluctuation of process parameters, device parameters such as transconductance and threshold voltage are mismatched. For SA, an offset voltage will be generated, which will cause small swing input signals to be misamplified by the sense amplifier. The structure of the traditional voltage type SA circuit is shown in Figure 1; in order to reduce the offset voltage of SA, the following technologies exist:

(1)如图2所示是M.Khayatzadeh和F.Frustaci于2015年提出的一种Reconfigurable Sense Amplifier型电路,该设计方案是将传统电压型灵敏放大器拆分成两个并联的灵敏放大器组,同时保持芯片面积与传统电压型SA一致。相比于传统电压型SA,该结构有四种不同的组合,在选择最佳组合的条件下该结构具有更好的抗失调电压能力,但是该电路的最佳组合的逻辑判断较为复杂。(1) As shown in Figure 2, a Reconfigurable Sense Amplifier circuit proposed by M.Khayatzadeh and F.Frustaci in 2015, the design scheme is to split the traditional voltage-type sense amplifier into two parallel sense amplifier groups, At the same time, the chip area is kept consistent with the traditional voltage type SA. Compared with the traditional voltage type SA, this structure has four different combinations. Under the condition of selecting the best combination, the structure has better anti-offset voltage capability, but the logic judgment of the best combination of the circuit is more complicated.

(2)如图3所示为T.Song和S.M.Lee在2010年设计出的Robust Latch-Type型SA电路,该设计用于减小漏流和失调电压的影响,提升了SA的读取数据的精准性,但是该电路设计在失调电压方面减少效果甚微,同时延长了SA的工作时间,降低了SA的速度。(2) As shown in Figure 3, the Robust Latch-Type SA circuit designed by T.Song and S.M.Lee in 2010 is used to reduce the influence of leakage current and offset voltage, and improve the read data of SA Accuracy, but the circuit design has little effect on reducing the offset voltage, while prolonging the working time of SA and reducing the speed of SA.

实用新型内容Utility model content

本实用新型的目的是提供一种失调电压自适应数字校准型灵敏放大器,它是一种可以有效降低灵敏放大器失调电压,进而加快静态随机存储器读取速度和降低单元读取功耗的电路结构。The purpose of the utility model is to provide an offset voltage self-adaptive digital calibration type sensitive amplifier, which is a circuit structure that can effectively reduce the offset voltage of the sensitive amplifier, thereby speeding up the reading speed of the static random access memory and reducing the power consumption of unit reading.

本实用新型的目的是通过以下技术方案实现的:The purpose of this utility model is achieved by the following technical solutions:

一种失调电压自适应数字校准型灵敏放大器,包括:相互连接的灵敏放大器主体部分、校准锁存电路,以及参考电压生成电路;An offset voltage self-adaptive digital calibration type sensitive amplifier, comprising: a main part of the sensitive amplifier connected to each other, a calibration latch circuit, and a reference voltage generating circuit;

其中,所述校准锁存电路包括:十个PMOS晶体管、四个NMOS晶体管、一个或门以及八个反相器;十个PMOS晶体管依次记为P9~P18,四个NMOS晶体管依次记为N6~N9,八个反相器依次记为I1~I8,或门记为OR;其中:Wherein, the calibration latch circuit includes: ten PMOS transistors, four NMOS transistors, one OR gate and eight inverters; the ten PMOS transistors are sequentially marked as P9~P18, and the four NMOS transistors are sequentially marked as N6~ N9, the eight inverters are marked as I1~I8 in turn, and the OR gate is marked as OR; where:

PMOS晶体管P9源极与VDD连接;PMOS晶体管P10栅极与输出节点OUT连接;PMOS晶体管P10源极与PMOS晶体管P9漏极连接;The source of the PMOS transistor P9 is connected to VDD; the gate of the PMOS transistor P10 is connected to the output node OUT; the source of the PMOS transistor P10 is connected to the drain of the PMOS transistor P9;

PMOS晶体管P11栅极与校准信号CK连接;PMOS晶体管P11源极与PMOS晶体管P10漏极连接;PMOS晶体管P11漏极与反相器I1输出连接,反相器I1输出记为节点A;反相器I1输出与反相器I2输入连接;反相器I2输出与反相器I1输入连接,反相器I1输入记为节点AB;The gate of the PMOS transistor P11 is connected to the calibration signal CK; the source of the PMOS transistor P11 is connected to the drain of the PMOS transistor P10; the drain of the PMOS transistor P11 is connected to the output of the inverter I1, and the output of the inverter I1 is marked as node A; The output of I1 is connected to the input of inverter I2; the output of inverter I2 is connected to the input of inverter I1, and the input of inverter I1 is marked as node AB;

NMOS晶体管N6栅极与重置信号RSET连接;NMOS晶体管N6漏极与PMOS晶体管P11漏极连接;NMOS晶体管N6源极与GND连接;The gate of the NMOS transistor N6 is connected to the reset signal RSET; the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P11; the source of the NMOS transistor N6 is connected to GND;

PMOS晶体管P12源极与VDD连接;PMOS晶体管P13栅极与输出节点OUTB连接;PMOS晶体管P13源极与PMOS晶体管P12漏极连接;The source of the PMOS transistor P12 is connected to VDD; the gate of the PMOS transistor P13 is connected to the output node OUTB; the source of the PMOS transistor P13 is connected to the drain of the PMOS transistor P12;

PMOS晶体管P14栅极与校准信号CK连接;PMOS晶体管P14源极与PMOS晶体管P13漏极连接;PMOS晶体管P14漏极与反相器I3输入连接,反相器I3输入记为节点B;反相器I3输出与反相器I4输入连接,反相器I4输入记为节点BB;反相器I4输出与反相器I3输入连接;The gate of the PMOS transistor P14 is connected to the calibration signal CK; the source of the PMOS transistor P14 is connected to the drain of the PMOS transistor P13; the drain of the PMOS transistor P14 is connected to the input of the inverter I3, and the input of the inverter I3 is marked as node B; The output of I3 is connected to the input of the inverter I4, and the input of the inverter I4 is marked as node BB; the output of the inverter I4 is connected to the input of the inverter I3;

NMOS晶体管N7栅极与重置信号RSET连接;NMOS晶体管N7漏极与PMOS晶体管P14漏极连接;NMOS晶体管N7源极与GND连接;The gate of the NMOS transistor N7 is connected to the reset signal RSET; the drain of the NMOS transistor N7 is connected to the drain of the PMOS transistor P14; the source of the NMOS transistor N7 is connected to GND;

PMOS晶体管P15源极与VDD连接;PMOS晶体管P15栅极与节点AB连接;PMOS晶体管P15漏极与PMOS晶体管P16源极连接;PMOS晶体管P16栅极和或门OR输出连接;PMOS晶体管P16漏极与反相器I5输出连接,反相器I5输出记为节点C;反相器I5输出与反相器I6输入连接;反相器I6输出与反相器I5输入连接反相器I5输入记为节点CB;节点C和或门OR输入连接;The source of the PMOS transistor P15 is connected to VDD; the gate of the PMOS transistor P15 is connected to the node AB; the drain of the PMOS transistor P15 is connected to the source of the PMOS transistor P16; the gate of the PMOS transistor P16 is connected to the OR output of the OR gate; the drain of the PMOS transistor P16 is connected to The output of inverter I5 is connected, and the output of inverter I5 is marked as node C; the output of inverter I5 is connected to the input of inverter I6; the output of inverter I6 is connected to the input of inverter I5, and the input of inverter I5 is marked as node CB; Node C is connected to the OR input of the OR gate;

NMOS晶体管N8栅极与重置信号RSET连接;NMOS晶体管N8漏极与PMOS晶体管P16漏极连接;NMOS晶体管N8源极与GND连接;The gate of the NMOS transistor N8 is connected to the reset signal RSET; the drain of the NMOS transistor N8 is connected to the drain of the PMOS transistor P16; the source of the NMOS transistor N8 is connected to GND;

PMOS晶体管P17源极与VDD连接;PMOS晶体管P17栅极与节点BB连接;PMOS晶体管P17漏极与PMOS晶体管P18源极连接;PMOS晶体管P18栅极和或门OR输出连接;PMOS晶体管P18漏极与反相器I7输入连接,反相器I7输入记为节点D;反相器I7输入与反相器I8输出连接;反相器I7输出与反相器I8输入连接,反相器I8输入记为DB;节点D和或门OR输入连接;NMOS晶体管N9栅极与重置信号RSET连接;NMOS晶体管N9漏极与PMOS晶体管P18漏极连接;NMOS晶体管N9源极与GND连接。The source of the PMOS transistor P17 is connected to VDD; the gate of the PMOS transistor P17 is connected to the node BB; the drain of the PMOS transistor P17 is connected to the source of the PMOS transistor P18; the gate of the PMOS transistor P18 is connected to the OR output of the OR gate; the drain of the PMOS transistor P18 is connected to The input of the inverter I7 is connected, and the input of the inverter I7 is marked as node D; the input of the inverter I7 is connected to the output of the inverter I8; the output of the inverter I7 is connected to the input of the inverter I8, and the input of the inverter I8 is marked as DB; the node D is connected to the OR input of the OR gate; the gate of the NMOS transistor N9 is connected to the reset signal RSET; the drain of the NMOS transistor N9 is connected to the drain of the PMOS transistor P18; the source of the NMOS transistor N9 is connected to GND.

由上述本实用新型提供的技术方案可以看出,本实用新型利用简单的外围电路实现SA失调电压校准补偿以及校准状态锁存操作,能够有效的降低SA的失调电压,改善了SRAM的读操作速度和功耗。It can be seen from the above-mentioned technical solution provided by the utility model that the utility model utilizes a simple peripheral circuit to realize SA offset voltage calibration compensation and calibration state latch operation, which can effectively reduce the SA offset voltage and improve the read operation speed of SRAM and power consumption.

附图说明Description of drawings

为了更清楚地说明本实用新型实施例的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本实用新型的一些实施例,对于本领域的普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他附图。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention , for those skilled in the art, other drawings can also be obtained based on these drawings without creative work.

图1为背景技术提供的传统电压型SA电路的结构示意图;Fig. 1 is the structural representation of the traditional voltage type SA circuit that background technology provides;

图2为背景技术提供的Reconfigurable SA电路的结构示意图;FIG. 2 is a schematic structural diagram of the Reconfigurable SA circuit provided by the background technology;

图3为背景技术提供的Robust Latch-Type SA电路的结构示意图;Fig. 3 is the structural representation of the Robust Latch-Type SA circuit that background technology provides;

图4为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器的结构示意图;Fig. 4 is a structural schematic diagram of an offset voltage self-adaptive digital calibration type sense amplifier provided by an embodiment of the present invention;

图5为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器校准前后波形仿真图;Fig. 5 is the waveform simulation diagram before and after calibration of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the present invention;

图6为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器传输门NMOS栅压与失调电压偏移量仿真关系图;FIG. 6 is a simulation relationship diagram between the offset voltage adaptive digital calibration type sense amplifier transmission gate NMOS grid voltage and the offset voltage offset provided by the embodiment of the present invention;

图7为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器校准技术流程图;Fig. 7 is a flow chart of the calibration technology of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the present invention;

图8为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器的校准锁存模块仿真状态图;Fig. 8 is the simulation state diagram of the calibration latch module of the offset voltage adaptive digital calibration type sense amplifier provided by the embodiment of the present invention;

图9为背景技术提供的传统电压型SA电路,Robust Latch-Type SA电路和本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器在cadence仿真软件下进行2500次蒙特卡洛仿真的失调电压统计图(仿真条件为:VDD:1.2V;Corner:FF、FS、SF、SS;Temperature:-40℃;25℃;25℃;125℃);Fig. 9 is the conventional voltage-type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model under the cadence simulation software for 2500 Monte Carlo simulations Statistical chart of offset voltage (simulation conditions: VDD: 1.2V; Corner: FF, FS, SF, SS; Temperature: -40°C; 25°C; 25°C; 125°C);

图10为背景技术提供的传统电压型SA电路,Robust Latch-Type SA电路和本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器失调电压柱状分布图(仿真条件为:VDD:1.2V;Corner:TT;Temperature:25℃)。Fig. 10 is the traditional voltage type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage adaptive digital calibration type sense amplifier offset voltage columnar distribution diagram provided by the embodiment of the utility model (simulation condition is: VDD: 1.2 V; Corner: TT; Temperature: 25°C).

具体实施方式Detailed ways

下面结合本实用新型实施例中的附图,对本实用新型实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本实用新型一部分实施例,而不是全部的实施例。基于本实用新型的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本实用新型的保护范围。The technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. . Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present utility model.

本实用新型实施例提供一种失调电压自适应数字校准型灵敏放大器,如图4所示,其主要包括:相互连接的灵敏放大器主体部分、校准锁存电路,以及参考电压生成电路;The embodiment of the utility model provides an offset voltage self-adaptive digital calibration type sensitive amplifier, as shown in Figure 4, which mainly includes: a main part of the sensitive amplifier connected to each other, a calibration latch circuit, and a reference voltage generating circuit;

其中,所述灵敏放大器主体部分实现信号的放大,如图4(a)所示,其包括:五个NMOS晶体管和八个PMOS晶体管,五个NMOS晶体管依次记为N1~N5,八个PMOS晶体管依次记为P1~P8;其中NMOS晶体管N1和PMOS晶体管P5构成一个反相器,NMOS晶体管N2和PMOS晶体管P6构成另一个反相器,这两个反相器形成交叉耦合结构;交叉耦合结构之间由两个NMOS和两个PMOS晶体管形成的传输门隔断;同时,还通过PMOS晶体管P1、PMOS晶体管P2对应的将灵敏放大器与BL、BLB隔离,通过PMOS晶体管P3与PMOS晶体管P4将灵敏放大器与VDD隔离开,通过NMOS晶体管N3将灵敏放大器与GND隔离开;其中:Wherein, the main part of the sensitive amplifier implements signal amplification, as shown in Figure 4(a), which includes: five NMOS transistors and eight PMOS transistors, the five NMOS transistors are sequentially marked as N1-N5, and the eight PMOS transistors They are recorded as P1~P8 in turn; NMOS transistor N1 and PMOS transistor P5 form an inverter, NMOS transistor N2 and PMOS transistor P6 form another inverter, and these two inverters form a cross-coupling structure; the cross-coupling structure The transmission gate formed by two NMOS and two PMOS transistors between them is isolated; at the same time, the sense amplifier is isolated from BL and BLB through PMOS transistor P1 and PMOS transistor P2 correspondingly, and the sense amplifier is separated from the sense amplifier through PMOS transistor P3 and PMOS transistor P4 VDD is isolated, and the sense amplifier is isolated from GND through NMOS transistor N3; where:

位线BL与PMOS晶体管P1的漏极连接;位线BLB与PMOS晶体管P2的漏极连接;使能信号SAE与PMOS晶体管P1的栅极以及PMOS晶体管P2的栅极连接;PMOS晶体管P1的源极与PMOS晶体管P5的漏极以及NMOS晶体管N1的漏极连接;PMOS晶体管P2的源极与PMOS晶体管P6的漏极以及NMOS晶体管N2的漏极连接;The bit line BL is connected to the drain of the PMOS transistor P1; the bit line BLB is connected to the drain of the PMOS transistor P2; the enable signal SAE is connected to the gate of the PMOS transistor P1 and the gate of the PMOS transistor P2; the source of the PMOS transistor P1 connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; the source of the PMOS transistor P2 is connected to the drain of the PMOS transistor P6 and the drain of the NMOS transistor N2;

预充信号PRE与PMOS晶体管P3的栅极以及PMOS晶体管P4的栅极连接;PMOS晶体管P3的漏极与PMOS晶体管P5的漏极以及NMOS晶体管N1的漏极连接;PMOS晶体管P4的漏极与PMOS晶体管P6的漏极以及NMOS晶体管N2的漏极连接;NMOS晶体管N3的漏极与NMOS晶体管N1的源极以及NMOS晶体管N2的源极连接;使能信号SAE与晶体管N3的栅极连接;The precharge signal PRE is connected to the gate of the PMOS transistor P3 and the gate of the PMOS transistor P4; the drain of the PMOS transistor P3 is connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; the drain of the PMOS transistor P4 is connected to the PMOS The drain of the transistor P6 is connected to the drain of the NMOS transistor N2; the drain of the NMOS transistor N3 is connected to the source of the NMOS transistor N1 and the source of the NMOS transistor N2; the enabling signal SAE is connected to the gate of the transistor N3;

传输门中NMOS晶体管N5的漏极与PMOS晶体管P6的栅极以及NMOS晶体管N2的栅极连接;传输门中PMOS晶体管P7的漏极和PMOS晶体管P6的栅极以及NMOS晶体管N2的栅极连接;传输门中NMOS晶体管N5的源极与PMOS晶体管P5的漏极以及NMOS晶体管N1的漏极连接;传输门中PMOS晶体管P7的源极与PMOS晶体管P5的漏极以及NMOS晶体管N1的漏极连接;传输门中NMOS晶体管N4的漏极与PMOS晶体管P5的栅极以及NMOS晶体管N1的栅极连接;传输门中PMOS晶体管P8的漏极和PMOS晶体管P5的栅极以及NMOS晶体管N1的栅极连接;传输门中NMOS晶体管N4的源极与PMOS晶体管P6的漏极以及NMOS晶体管N2的漏极连接;传输门中PMOS晶体管P8的源极与PMOS晶体管P6的漏极以及NMOS晶体管N2的漏极连接;The drain of the NMOS transistor N5 in the transmission gate is connected to the gate of the PMOS transistor P6 and the gate of the NMOS transistor N2; the drain of the PMOS transistor P7 in the transmission gate is connected to the gate of the PMOS transistor P6 and the gate of the NMOS transistor N2; The source of the NMOS transistor N5 in the transmission gate is connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; the source of the PMOS transistor P7 in the transmission gate is connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; The drain of the NMOS transistor N4 in the transmission gate is connected to the gate of the PMOS transistor P5 and the gate of the NMOS transistor N1; the drain of the PMOS transistor P8 in the transmission gate is connected to the gate of the PMOS transistor P5 and the gate of the NMOS transistor N1; The source of the NMOS transistor N4 in the transmission gate is connected to the drain of the PMOS transistor P6 and the drain of the NMOS transistor N2; the source of the PMOS transistor P8 in the transmission gate is connected to the drain of the PMOS transistor P6 and the drain of the NMOS transistor N2;

VDD与PMOS晶体管P3、P4、P5及P6的源极连接;GND与NMOS晶体管N3的源极以及PMOS晶体管P7与P8的栅极连接。VDD is connected to the sources of the PMOS transistors P3 , P4 , P5 and P6 ; GND is connected to the source of the NMOS transistor N3 and the gates of the PMOS transistors P7 and P8 .

本实用新型实施例中,NMOS晶体管N5的漏极与节点Q连接,NMOS晶体管N5的源极与输出节点OUT连接,NMOS晶体管N5的栅极与其控制电压信号VF连接;NMOS晶体管N4的漏极与节点QB连接,NMOS晶体管N4的源极与输出节点OUTB连接,NMOS晶体管N4的栅极与其控制电压信号VS连接,这样输出节点的电位变化就可以用VF和VS控制,有助于大幅度减少灵敏放大器的失调电压。In the embodiment of the present invention, the drain of the NMOS transistor N5 is connected to the node Q, the source of the NMOS transistor N5 is connected to the output node OUT, the gate of the NMOS transistor N5 is connected to the control voltage signal VF; the drain of the NMOS transistor N4 is connected to The node QB is connected, the source of the NMOS transistor N4 is connected to the output node OUTB, and the gate of the NMOS transistor N4 is connected to its control voltage signal VS, so that the potential change of the output node can be controlled by VF and VS, which helps to greatly reduce the sensitivity amplifier offset voltage.

如图4(b)所示,所述校准锁存电路包括:十个PMOS晶体管、四个NMOS晶体管、一个或门以及八个反相器;十个PMOS晶体管依次记为P9~P18,四个NMOS晶体管依次记为N6~N9,八个反相器依次记为I1~I8,或门记为OR;其中:As shown in Figure 4(b), the calibration latch circuit includes: ten PMOS transistors, four NMOS transistors, one OR gate and eight inverters; The NMOS transistors are marked as N6-N9 in turn, the eight inverters are marked as I1-I8 in turn, and the OR gate is marked as OR; where:

PMOS晶体管P9源极与VDD连接;PMOS晶体管P10栅极与输出节点OUT连接;PMOS晶体管P10源极与PMOS晶体管P9漏极连接;The source of the PMOS transistor P9 is connected to VDD; the gate of the PMOS transistor P10 is connected to the output node OUT; the source of the PMOS transistor P10 is connected to the drain of the PMOS transistor P9;

PMOS晶体管P11栅极与校准信号CK连接;PMOS晶体管P11源极与PMOS晶体管P10漏极连接;PMOS晶体管P11漏极与反相器I1输出连接,反相器I1输出记为节点A;反相器I1输出与反相器I2输入连接;反相器I2输出与反相器I1输入连接,反相器I1输入记为节点AB;The gate of the PMOS transistor P11 is connected to the calibration signal CK; the source of the PMOS transistor P11 is connected to the drain of the PMOS transistor P10; the drain of the PMOS transistor P11 is connected to the output of the inverter I1, and the output of the inverter I1 is marked as node A; The output of I1 is connected to the input of inverter I2; the output of inverter I2 is connected to the input of inverter I1, and the input of inverter I1 is marked as node AB;

NMOS晶体管N6栅极与重置信号RSET连接;NMOS晶体管N6漏极与PMOS晶体管P11漏极连接;NMOS晶体管N6源极与GND连接;The gate of the NMOS transistor N6 is connected to the reset signal RSET; the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P11; the source of the NMOS transistor N6 is connected to GND;

PMOS晶体管P12源极与VDD连接;PMOS晶体管P13栅极与输出节点OUTB连接;PMOS晶体管P13源极与PMOS晶体管P12漏极连接;The source of the PMOS transistor P12 is connected to VDD; the gate of the PMOS transistor P13 is connected to the output node OUTB; the source of the PMOS transistor P13 is connected to the drain of the PMOS transistor P12;

PMOS晶体管P14栅极与校准信号CK连接;PMOS晶体管P14源极与PMOS晶体管P13漏极连接;PMOS晶体管P14漏极与反相器I3输入连接,反相器I3输入记为节点B;反相器I3输出与反相器I4输入连接,反相器I4输入记为节点BB;反相器I4输出与反相器I3输入连接;The gate of the PMOS transistor P14 is connected to the calibration signal CK; the source of the PMOS transistor P14 is connected to the drain of the PMOS transistor P13; the drain of the PMOS transistor P14 is connected to the input of the inverter I3, and the input of the inverter I3 is marked as node B; The output of I3 is connected to the input of the inverter I4, and the input of the inverter I4 is marked as node BB; the output of the inverter I4 is connected to the input of the inverter I3;

NMOS晶体管N7栅极与重置信号RSET连接;NMOS晶体管N7漏极与PMOS晶体管P14漏极连接;NMOS晶体管N7源极与GND连接;The gate of the NMOS transistor N7 is connected to the reset signal RSET; the drain of the NMOS transistor N7 is connected to the drain of the PMOS transistor P14; the source of the NMOS transistor N7 is connected to GND;

PMOS晶体管P15源极与VDD连接;PMOS晶体管P15栅极与节点AB连接;PMOS晶体管P15漏极与PMOS晶体管P16源极连接;PMOS晶体管P16栅极和或门OR输出连接;PMOS晶体管P16漏极与反相器I5输出连接,反相器I5输出记为节点C;反相器I5输出与反相器I6输入连接;反相器I6输出与反相器I5输入连接反相器I5输入记为节点CB;节点C和或门OR输入连接;The source of the PMOS transistor P15 is connected to VDD; the gate of the PMOS transistor P15 is connected to the node AB; the drain of the PMOS transistor P15 is connected to the source of the PMOS transistor P16; the gate of the PMOS transistor P16 is connected to the OR output of the OR gate; the drain of the PMOS transistor P16 is connected to The output of inverter I5 is connected, and the output of inverter I5 is marked as node C; the output of inverter I5 is connected to the input of inverter I6; the output of inverter I6 is connected to the input of inverter I5, and the input of inverter I5 is marked as node CB; Node C is connected to the OR input of the OR gate;

NMOS晶体管N8栅极与重置信号RSET连接;NMOS晶体管N8漏极与PMOS晶体管P16漏极连接;NMOS晶体管N8源极与GND连接;The gate of the NMOS transistor N8 is connected to the reset signal RSET; the drain of the NMOS transistor N8 is connected to the drain of the PMOS transistor P16; the source of the NMOS transistor N8 is connected to GND;

PMOS晶体管P17源极与VDD连接;PMOS晶体管P17栅极与节点BB连接;PMOS晶体管P17漏极与PMOS晶体管P18源极连接;PMOS晶体管P18栅极和或门OR输出连接;PMOS晶体管P18漏极与反相器I7输入连接,反相器I7输入记为节点D;反相器I7输入与反相器I8输出连接;反相器I7输出与反相器I8输入连接,反相器I8输入记为DB;节点D和或门OR输入连接;NMOS晶体管N9栅极与重置信号RSET连接;NMOS晶体管N9漏极与PMOS晶体管P18漏极连接;NMOS晶体管N9源极与GND连接。The source of the PMOS transistor P17 is connected to VDD; the gate of the PMOS transistor P17 is connected to the node BB; the drain of the PMOS transistor P17 is connected to the source of the PMOS transistor P18; the gate of the PMOS transistor P18 is connected to the OR output of the OR gate; the drain of the PMOS transistor P18 is connected to The input of the inverter I7 is connected, and the input of the inverter I7 is marked as node D; the input of the inverter I7 is connected to the output of the inverter I8; the output of the inverter I7 is connected to the input of the inverter I8, and the input of the inverter I8 is marked as DB; the node D is connected to the OR input of the OR gate; the gate of the NMOS transistor N9 is connected to the reset signal RSET; the drain of the NMOS transistor N9 is connected to the drain of the PMOS transistor P18; the source of the NMOS transistor N9 is connected to GND.

如图4(c)所示,所述参考电压生成电路包括:一个NMOS晶体管、六个PMOS晶体管、三个电阻和一个与非门;一个NMOS晶体管记为N10,六个PMOS晶体管依次记为P19~P24,三个电阻记为R1~R3,一个与非门记为NAND;其中:As shown in Figure 4(c), the reference voltage generation circuit includes: an NMOS transistor, six PMOS transistors, three resistors and a NAND gate; one NMOS transistor is marked as N10, and the six PMOS transistors are marked as P19 in turn ~P24, three resistors are marked as R1~R3, and one NAND gate is marked as NAND; among them:

PMOS晶体管P19和P20的源极与VDD连接;PMOS晶体管P19栅极与节点C连接;The sources of PMOS transistors P19 and P20 are connected to VDD; the gate of PMOS transistor P19 is connected to node C;

MOS晶体管P20栅极与节点D连接;PMOS晶体管P22栅极与节点CB连接;PMOS晶体管P24栅极与节点DB连接;PMOS晶体管P19漏极与PMOS晶体管P22源极以及控制电压信号VF连接;PMOS晶体管P20漏极与PMOS晶体管P24源极以及控制电压信号VS连接;PMOS晶体管P22漏极和PMOS晶体管P24漏极与PMOS晶体管P21源极和PMOS晶体管P23源极连接;The gate of the MOS transistor P20 is connected to the node D; the gate of the PMOS transistor P22 is connected to the node CB; the gate of the PMOS transistor P24 is connected to the node DB; the drain of the PMOS transistor P19 is connected to the source of the PMOS transistor P22 and the control voltage signal VF; the PMOS transistor The drain of P20 is connected to the source of PMOS transistor P24 and the control voltage signal VS; the drain of PMOS transistor P22 and the drain of PMOS transistor P24 are connected to the source of PMOS transistor P21 and the source of PMOS transistor P23;

节点A和节点B与与非门NAND输入连接;与非门NAND输出与PMOS晶体管P21栅极和反相器I9输入连接;反相器I9输出与PMOS晶体管P23栅极连接;电阻R3上端与VDD连接;电阻R3下端与PMOS晶体管P21漏极和电阻R2上端连接;电阻R2下端与PMOS晶体管P23漏极和电阻R1上端连接;电阻R1下端与NMOS晶体管N10漏极连接,NMOS晶体管N10源极与GND连接;NMOS晶体管N10栅极与信号SAE连接。Nodes A and B are connected to the NAND input of the NAND gate; the NAND output of the NAND gate is connected to the gate of the PMOS transistor P21 and the input of the inverter I9; the output of the inverter I9 is connected to the gate of the PMOS transistor P23; the upper end of the resistor R3 is connected to VDD Connection; the lower end of resistor R3 is connected to the drain of PMOS transistor P21 and the upper end of resistor R2; the lower end of resistor R2 is connected to the drain of PMOS transistor P23 and the upper end of resistor R1; the lower end of resistor R1 is connected to the drain of NMOS transistor N10, and the source of NMOS transistor N10 is connected to GND connected; the gate of the NMOS transistor N10 is connected to the signal SAE.

具体的,本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器电路中,与传统的SA相比,设计在OUT和Q(OUTB和QB)之间增加了一个传输门。传输门的NMOS栅极电压是VF(VS),并且PMOS栅极电压总是接地的。该设计的目的是通过控制节点的放电速度减少因阈值电压差异产生的失调电压。与Robust Latch-Type SA结构(图3所示结构)相比,本实用新型用VF/VS代替BL/BLB,因此本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器可以使用数字校准技术实现失调电压大幅度减小的效果。Robust Latch-Type SA结构使用信号SAE而不是GND连接传输门中的PMOS的栅极,导致在失调校准时传输门的PMOS处于关断状态。由于NMOS传输高电平时存在阈值损失的问题,因此在SA工作时节点Q/QB不能充电到VDD。Specifically, in the offset voltage adaptive digital calibration type sense amplifier circuit provided by the embodiment of the utility model, compared with the traditional SA, a transmission gate is added between OUT and Q (OUTB and QB). The NMOS gate voltage of the transmission gate is VF(VS), and the PMOS gate voltage is always grounded. The purpose of this design is to reduce the offset voltage due to threshold voltage differences by controlling the discharge rate of the nodes. Compared with the Robust Latch-Type SA structure (structure shown in Figure 3), the utility model replaces BL/BLB with VF/VS, so the offset voltage adaptive digital calibration type sense amplifier provided by the embodiment of the utility model can use digital The calibration technique achieves the effect of greatly reducing the offset voltage. The Robust Latch-Type SA structure uses the signal SAE instead of GND to connect the gate of the PMOS in the transmission gate, causing the PMOS of the transmission gate to be in an off state during offset calibration. Due to the problem of threshold loss when NMOS transmits high level, node Q/QB cannot be charged to VDD when SA is working.

同时本实用新型利用了失调电压自适应数字校准型灵敏放大器的自适应数字校准技术只需要在SA正常工作前校准两个周期就不再需要任何操作。本实用新型的校准技术通过理论分析计算出最佳失调补偿量,并且数字化校准技术可以实现两次校准,效果更加明显。锁存技术能够保存校准过程,达到一次校准多次使用的效果。At the same time, the utility model utilizes the self-adaptive digital calibration technology of the offset voltage self-adaptive digital calibration type sensitive amplifier, and only needs to calibrate two cycles before the normal operation of the SA, and no operation is required. The calibration technology of the utility model calculates the optimal offset compensation amount through theoretical analysis, and the digital calibration technology can realize two calibrations, and the effect is more obvious. The latching technology can save the calibration process to achieve the effect of one calibration and multiple uses.

本实用新型实施提供的失调电压自适应数字校准型灵敏放大器在预充阶段,PRE信号为低电平,SAE信号也为低电平,PMOS晶体管P3和P4导通,存储节点OUT,OUTB和节点Q,QB都被预充到高电平;当预充阶段结束SA进入工作阶段时,PRE信号为高电平,SAE信号为高电平,PMOS晶体管P3和P4截止,电路停止预充,晶体管P1和P2截止,存储节点OUT/OUTB与BL/BLB隔断。由于BL和BLB在单元管放电路径的差异存在着电压差,这种差异同样会在OUT和OUTB上体现出来,SA的交叉耦合结构会放大这种电压差。值得一提的是这种电压差如果小于SA失调电压就会出现错误读取情况,因此常规的做法会在BL和BLB电压差异较大的时候SAE信号才变成高电平。本实用新型实施例提供的SA可以通过外围电路判断失调电压的正负性以及大致范围,改变VF或者VS电压的大小来控制传输门上通过NMOS的电流强度,最终效果是减小了因为NMOS晶体管N1和N2阈值不匹配导致的电压差,从而降低失调电压。相比较于传统电压型SA延长位线放电时间保证正确率的方法,本实用新型实施例提供的SA就可以减少位线放电时间,在功耗和速度方面得到改善。The offset voltage adaptive digital calibration type sensitive amplifier provided by the utility model is in the precharge stage, the PRE signal is low level, the SAE signal is also low level, the PMOS transistors P3 and P4 are turned on, and the storage nodes OUT, OUTB and node Both Q and QB are precharged to a high level; when the precharge phase ends and SA enters the working phase, the PRE signal is high, the SAE signal is high, the PMOS transistors P3 and P4 are cut off, the circuit stops precharging, and the transistor P1 and P2 are cut off, and storage nodes OUT/OUTB are isolated from BL/BLB. Because there is a voltage difference between BL and BLB in the cell tube discharge path, this difference will also be reflected on OUT and OUTB, and the cross-coupling structure of SA will amplify this voltage difference. It is worth mentioning that if this voltage difference is less than the SA offset voltage, there will be an error reading situation. Therefore, the conventional practice is to change the SAE signal to a high level when the voltage difference between BL and BLB is large. The SA provided by the embodiment of the utility model can judge the positive and negative of the offset voltage and the approximate range through the peripheral circuit, and change the magnitude of the VF or VS voltage to control the current intensity passing through the NMOS on the transmission gate. The voltage difference caused by the mismatch of N1 and N2 thresholds reduces the offset voltage. Compared with the method of extending the discharge time of the bit line to ensure accuracy in the traditional voltage-type SA, the SA provided by the embodiment of the utility model can reduce the discharge time of the bit line and improve power consumption and speed.

为了更加清晰地展现出本实用新型所提供的技术方案及所产生的技术效果,下面结合图5至图8,将介绍本实用新型实施例所提供的自适应校准锁存灵敏放大器电路的理论分析与仿真验证过程;结合图9、图10,将本实用新型实施例所提供的自适应校准锁存灵敏放大器电路的性能,与背景技术提供的传统电压型SA电路和Robust Latch-Type SA电路进行对比;其具体内容如下:In order to more clearly show the technical solution and the technical effects produced by the utility model, the following will introduce the theoretical analysis of the self-adaptive calibration latch sense amplifier circuit provided by the embodiment of the utility model in conjunction with Fig. 5 to Fig. 8 and simulation verification process; in conjunction with Fig. 9, Fig. 10, the performance of the self-adaptive calibration latch sense amplifier circuit provided by the embodiment of the utility model is carried out with the traditional voltage type SA circuit and the Robust Latch-Type SA circuit provided by the background technology Contrast; its specific content is as follows:

(1)如图5所示,为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器校准前后波形仿真图。其中的实线,即“(A)”类曲线对应校准后结果,此时VF连接参考电压,VS连接VDD;其中的虚线,即“(B)”类曲线对应校准前结果,此时VF和VS都连接VDD。仿真结果显示校准之后OUT和OUTB,Q和QB的电压差都显著的减小,其中校准前后失调电压分别是30mV和10mV。因此通过控制传输门NMOS的栅压可以达到降低失调电压的效果。(1) As shown in FIG. 5 , it is a waveform simulation diagram before and after calibration of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model. The solid line, that is, the "(A)" type curve corresponds to the result after calibration. At this time, VF is connected to the reference voltage, and VS is connected to VDD; the dotted line, that is, the "(B)" type curve corresponds to the result before calibration. At this time, VF and Both VS are connected to VDD. The simulation results show that the voltage difference between OUT and OUTB, Q and QB is significantly reduced after calibration, and the offset voltages before and after calibration are 30mV and 10mV respectively. Therefore, the effect of reducing the offset voltage can be achieved by controlling the gate voltage of the transmission gate NMOS.

(2)如图6所示,为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器中传输门NMOS栅压与失调电压偏移量仿真关系图。根据图5得出的控制传输门NMOS栅压可以降低失调电压的结论,图6验证了传输门NMOS栅压和失调电压偏移量之间的关系(VF电位变化,VS始终保持与VDD连接),可以发现仿真结果近乎为一条直线,因此我们得出NMOS栅极电压与失调电压偏移量为线性关系的结论。(2) As shown in FIG. 6 , it is a simulation relationship diagram of the transmission gate NMOS grid voltage and the offset voltage offset in the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model. According to the conclusion in Figure 5 that controlling the NMOS gate voltage of the transmission gate can reduce the offset voltage, Figure 6 verifies the relationship between the NMOS gate voltage of the transmission gate and the offset voltage offset (VF potential changes, VS is always connected to VDD) , it can be found that the simulation result is almost a straight line, so we conclude that the NMOS gate voltage and the offset voltage offset are linear.

(3)如图7所示,为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器校准流程图;结合图4(b)所示的本实用新型SA对应的校准锁存电路与图4(c)所示的本实用新型SA对应的参考电压生成电路,首先对电路进行预充放电,然后判断输出节点电位的高低,如果OUT为“0”则节点A、C电位升高,VF接入参考电压1;如果OUT为“1”则节点B、D电位升高,VS接入参考电压1。进入第二个校准周期后再对电路进行预充和无位线电压差的条件下放电,如果输出节点输出的数据与上一周期保持一致则校准结束;如果输出数据不保持一致则参考电压1替换成参考电压2与VF或者VS连接,校准结束。(3) As shown in Figure 7, the calibration flow chart of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model; in conjunction with the calibration latch circuit corresponding to the SA of the utility model shown in Figure 4 (b) The reference voltage generating circuit corresponding to the SA of the utility model shown in Fig. 4(c) first precharges and discharges the circuit, and then judges the level of the output node potential. If OUT is "0", the potentials of nodes A and C rise , VF is connected to reference voltage 1; if OUT is "1", the potentials of nodes B and D rise, and VS is connected to reference voltage 1. After entering the second calibration cycle, the circuit is precharged and discharged under the condition of no bit line voltage difference. If the data output by the output node is consistent with the previous cycle, the calibration ends; if the output data is not consistent, the reference voltage 1 Replace it with reference voltage 2 and connect it to VF or VS, and the calibration ends.

(4)如图8所示,为本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器校准锁存模块仿真状态图。图8展示了校准周期中存在的两种不同的情况,其中的图8(a)在第一个周期OUT输出结果为“0”,节点A、C升高VF接入参考电压1;第二个周期在接入参考电压1后,失调电压校准补偿出现了过补偿现象,OUT输出结果从上一周期的“0”变成了“1”,因此节点B电位升高VF接入参考电压2校准结束。其中的图8(b)在第一个周期OUT输出结果为“0”,节点A、C升高VF接入参考电压1;第二个周期在接入参考电压1后,失调电压校准补偿未出现过补偿现象,OUT输出结果与上一周期保持一致,节点B、D电位没有变化,VF继续保持与参考电压1的连接,校准结束。(4) As shown in FIG. 8 , it is a simulation state diagram of the calibration latch module of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model. Figure 8 shows two different situations in the calibration cycle, in which Figure 8(a) outputs "0" in the first cycle OUT, and nodes A and C increase VF to access the reference voltage 1; the second After the reference voltage 1 is connected in the first cycle, the offset voltage calibration compensation has an overcompensation phenomenon, and the output result of OUT changes from "0" in the previous cycle to "1", so the potential of node B rises and VF is connected to the reference voltage 2 Calibration is complete. In Figure 8(b), the OUT output result is "0" in the first cycle, and the nodes A and C increase VF to connect to the reference voltage 1; after the reference voltage 1 is connected to the second cycle, the offset voltage calibration compensation is not Overcompensation occurs, the OUT output is consistent with the previous cycle, the potentials of nodes B and D do not change, VF continues to be connected to the reference voltage 1, and the calibration ends.

(5)如图9所示,为背景技术提供的传统电压型SA电路,Robust Latch-Type SA电路和本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器在cadence仿真软件下进行2500次蒙特卡洛仿真的失调电压统计图;每一组中的三个柱状依次对应传统电压型SA、Robust Latch-Type SA与本实用新型实施例提供SA的仿真结果。通过图9的数据统计可以看出,Robust Latch-Type SA相比较于传统电压型SA有所改善,但是改善效果甚微。本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器相比较传统电压型SA和Robust Latch-Type SA在失调电压方面都有着大幅度的减小,即便在提升效果最差的SF工艺角下,相比较于传统电压型SA仍保持降低49.9%的效果,比较Robust Latch-Type SA降低35.8%。(5) As shown in Figure 9, the traditional voltage type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model are carried out under the cadence simulation software Statistical diagram of offset voltage for 2500 times of Monte Carlo simulation; three columns in each group correspond to traditional voltage-type SA, Robust Latch-Type SA and the simulation results of SA provided by the embodiment of the utility model. It can be seen from the data statistics in Figure 9 that the Robust Latch-Type SA has improved compared with the traditional voltage-type SA, but the improvement effect is very small. Compared with the traditional voltage type SA and the Robust Latch-Type SA, the offset voltage self-adaptive digital calibration type sensitive amplifier provided by the embodiment of the utility model has a large reduction in the offset voltage, even in the SF process with the worst lifting effect Under the angle, compared with the traditional voltage type SA, it still maintains the reduction effect of 49.9%, and compared with the Robust Latch-Type SA, the reduction is 35.8%.

(6)如图10所示,为背景技术提供的传统电压型SA电路,Robust Latch-Type SA电路和本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器失调电压柱状分布图。其中仿真条件为:(VDD:1.2V;Corner:TT;Temperature:25℃)。其中图10(a)为传统电压型SA失调电压仿真数据柱状图,均值μ为74.61uV,标准差σ为15.15mV,图10(b)为RobustLatch-Type SA失调电压仿真数据柱状图,可以看出相比较传统电压型SA柱状图分布更加密集,标准差σ下降到11.90mV,图10(c)是本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器失调电压仿真数据柱状图,柱状图密集程度大幅度提升,标准差σ更是降低到6.499mV。本实用新型实施例所提供的失调电压自适应数字校准型灵敏放大器相比较于传统电压型SA失调电压降低了57%,相比较于Robust Latch-Type SA失调电压降低了45.4%。(6) As shown in Figure 10, the traditional voltage type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage self-adaptive digital calibration type sense amplifier offset voltage columnar distribution diagram provided by the embodiment of the present invention. The simulation conditions are: (VDD: 1.2V; Corner: TT; Temperature: 25°C). Among them, Fig. 10(a) is the histogram of the simulation data of the traditional voltage-type SA offset voltage, the mean value μ is 74.61uV, and the standard deviation σ is 15.15mV. Fig. 10(b) is the histogram of the simulation data of the RobustLatch-Type SA offset voltage. You can see Compared with the traditional voltage-type SA histogram, the distribution is more dense, and the standard deviation σ drops to 11.90mV. Figure 10(c) is the histogram of the offset voltage self-adaptive digital calibration type sense amplifier offset voltage simulation data provided by the embodiment of the utility model , the density of the histogram is greatly increased, and the standard deviation σ is reduced to 6.499mV. Compared with the traditional voltage-type SA, the offset voltage of the offset voltage self-adaptive digital calibration type sensitive amplifier provided by the embodiment of the utility model is reduced by 57%, and compared with the Robust Latch-Type SA, the offset voltage is reduced by 45.4%.

综上所述,本实用新型提供的一种失调电压自适应数字校准型灵敏放大器,能够有效降低灵敏放大器SA的失调电压,该电路结构利用简单的外围电路实现灵敏放大器失调电压的校准补偿以及补偿状态锁存操作,达到了大幅度降低失调电压的目的;同时由于失调电压的降低,有效的提升了静态随机存储器读取电路的设计裕度,进而降低了单元读取时产生的功耗消耗,并提升了静态随机存储器的数据读取速度。In summary, the utility model provides an offset voltage self-adaptive digital calibration type sense amplifier, which can effectively reduce the offset voltage of the sense amplifier SA, and the circuit structure uses a simple peripheral circuit to realize calibration compensation and compensation of the offset voltage of the sense amplifier The state latch operation achieves the purpose of greatly reducing the offset voltage; at the same time, due to the reduction of the offset voltage, the design margin of the SRAM read circuit is effectively improved, thereby reducing the power consumption generated when the unit is read, And the data reading speed of the SRAM is improved.

以上所述,仅为本实用新型较佳的具体实施方式,但本实用新型的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本实用新型披露的技术范围内,可轻易想到的变化或替换,都应涵盖在本实用新型的保护范围之内。因此,本实用新型的保护范围应该以权利要求书的保护范围为准。The above is only a preferred embodiment of the utility model, but the scope of protection of the utility model is not limited thereto, and any person familiar with the technical field can easily think of All changes or replacements should fall within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be based on the protection scope of the claims.

Claims (3)

1. a kind of offset voltage adaptive digital calibration type sense amplifier, which is characterized in that including:The sensitive of interconnection is put Big device main part, calibration latch cicuit and reference voltage generating circuit;
Wherein, the calibration latch cicuit includes:Ten PMOS transistors, four NMOS transistors, one or and eight Phase inverter;Ten PMOS transistors are denoted as P9~P18 successively, and four NMOS transistors are denoted as N6~N9, eight phase inverters successively It is denoted as I1~I8 successively or door is denoted as OR;Wherein:
PMOS transistor P9 source electrodes are connect with VDD;PMOS transistor P10 grids are connect with output node OUT;PMOS transistor P10 source electrodes are connected with PMOS transistor P9 drain electrodes;
PMOS transistor P11 grids are connect with calibration signal CK;PMOS transistor P11 source electrodes connect with PMOS transistor P10 drain electrodes It connects;PMOS transistor P11 drain electrodes are connected with phase inverter I1 outputs, and phase inverter I1 outputs are denoted as node A;Phase inverter I1 output with it is anti- The I2 input connections of phase device;Phase inverter I2 outputs are connected with phase inverter I1 inputs, and phase inverter I1 inputs are denoted as node AB;
NMOS transistor N6 grids are connect with reset signal RSET;NMOS transistor N6 drain electrodes connect with PMOS transistor P11 drain electrodes It connects;NMOS transistor N6 source electrodes are connect with GND;
PMOS transistor P12 source electrodes are connect with VDD;PMOS transistor P13 grids are connect with output node OUTB;PMOS transistor P13 source electrodes are connected with PMOS transistor P12 drain electrodes;
PMOS transistor P14 grids are connect with calibration signal CK;PMOS transistor P14 source electrodes connect with PMOS transistor P13 drain electrodes It connects;PMOS transistor P14 drain electrodes are connected with phase inverter I3 inputs, and phase inverter I3 inputs are denoted as node B;Phase inverter I3 output with it is anti- The I4 input connections of phase device, phase inverter I4 inputs are denoted as node BB;Phase inverter I4 outputs are connected with phase inverter I3 inputs;
NMOS transistor N7 grids are connect with reset signal RSET;NMOS transistor N7 drain electrodes connect with PMOS transistor P14 drain electrodes It connects;NMOS transistor N7 source electrodes are connect with GND;
PMOS transistor P15 source electrodes are connect with VDD;PMOS transistor P15 grids are connect with node AB;PMOS transistor P15 leakages Pole is connect with PMOS transistor P16 source electrodes;PMOS transistor P16 grids and/or door OR output connections;PMOS transistor P16 drain electrodes It is connected with phase inverter I5 outputs, phase inverter I5 outputs are denoted as node C;Phase inverter I5 outputs are connected with phase inverter I6 inputs;Reverse phase Device I6 outputs are denoted as node CB with phase inverter I5 input connection phase inverter I5 inputs;Node C and/or door OR input connections;
NMOS transistor N8 grids are connect with reset signal RSET;NMOS transistor N8 drain electrodes connect with PMOS transistor P16 drain electrodes It connects;NMOS transistor N8 source electrodes are connect with GND;
PMOS transistor P17 source electrodes are connect with VDD;PMOS transistor P17 grids are connect with node BB;PMOS transistor P17 leakages Pole is connect with PMOS transistor P18 source electrodes;PMOS transistor P18 grids and/or door OR output connections;PMOS transistor P18 drain electrodes It is connected with phase inverter I7 inputs, phase inverter I7 inputs are denoted as node D;Phase inverter I7 inputs are connected with phase inverter I8 outputs;Reverse phase Device I7 outputs are connected with phase inverter I8 inputs, and phase inverter I8 inputs are denoted as DB;Node D and/or door OR input connections;NMOS crystal Pipe N9 grids are connect with reset signal RSET;NMOS transistor N9 drain electrodes are connected with PMOS transistor P18 drain electrodes;NMOS transistor N9 source electrodes are connect with GND.
2. a kind of offset voltage adaptive digital calibration type sense amplifier according to claim 1, which is characterized in that institute Stating sense amplifier main part includes:Five NMOS transistors and eight PMOS transistors, five NMOS transistors are remembered successively For N1~N5, eight PMOS transistors are denoted as P1~P8 successively;Wherein NMOS transistor N1 and PMOS transistor P5 constitute one Phase inverter, NMOS transistor N2 and PMOS transistor P6 constitute another phase inverter, the two phase inverters form cross-couplings knot Structure;Separated by the transmission gate that two NMOS and two PMOS transistors are formed between cross coupling structure;Meanwhile also passing through PMOS Transistor P1, PMOS transistor P2 are corresponding, and sense amplifier is isolated with BL, BLB, brilliant by PMOS transistor P3 and PMOS Body pipe P4 keeps apart sense amplifier and VDD, is kept apart sense amplifier and GND by NMOS transistor N3;Wherein:
Bit line BL is connect with the drain electrode of PMOS transistor P1;Bit line BLB is connect with the drain electrode of PMOS transistor P2;Enable signal SAE is connect with the grid of the grid of PMOS transistor P1 and PMOS transistor P2;The source electrode of PMOS transistor P1 is brilliant with PMOS The drain electrode of body pipe P5 and the drain electrode connection of NMOS transistor N1;The drain electrode of the source electrode and PMOS transistor P6 of PMOS transistor P2 And the drain electrode connection of NMOS transistor N2;
Preliminary filling signal PRE is connect with the grid of the grid of PMOS transistor P3 and PMOS transistor P4;PMOS transistor P3's Drain electrode is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1;The drain electrode of PMOS transistor P4 is brilliant with PMOS The drain electrode of body pipe P6 and the drain electrode connection of NMOS transistor N2;The source electrode of the drain electrode and NMOS transistor N1 of NMOS transistor N3 And the source electrode connection of NMOS transistor N2;Enable signal SAE is connect with the grid of transistor N3;
The drain electrode of NMOS transistor N5 is connect with the grid of the grid of PMOS transistor P6 and NMOS transistor N2 in transmission gate; The drain electrode of PMOS transistor P7 is connected with the grid of the grid of PMOS transistor P6 and NMOS transistor N2 in transmission gate;Transmission The source electrode of NMOS transistor N5 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1 in door;In transmission gate The source electrode of PMOS transistor P7 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1;NMOS in transmission gate The drain electrode of transistor N4 is connect with the grid of the grid of PMOS transistor P5 and NMOS transistor N1;PMOS crystal in transmission gate The drain electrode of pipe P8 is connected with the grid of the grid of PMOS transistor P5 and NMOS transistor N1;NMOS transistor N4 in transmission gate Source electrode connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2;The source of PMOS transistor P8 in transmission gate Pole is connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2;
VDD is connect with the source electrode of PMOS transistor P3, P4, P5 and P6;The source electrode and PMOS crystal of GND and NMOS transistor N3 The grid of pipe P7 and P8 connect;
The drain electrode of the NMOS transistor N5 is connect with node Q, and the source electrode of NMOS transistor N5 is connect with output node OUT, The grid of NMOS transistor N5 is connect with its control voltage signal VF;The drain electrode of NMOS transistor N4 is connect with node QB, NMOS The source electrode of transistor N4 is connect with output node OUTB, and the grid of NMOS transistor N4 is connect with its control voltage signal VS.
3. a kind of offset voltage adaptive digital calibration type sense amplifier according to claim 2, which is characterized in that institute Stating reference voltage generating circuit includes:One NMOS transistor, three resistance and a NAND gate and six PMOS transistors;One A NMOS transistor is denoted as N10, and six PMOS transistors are denoted as P19~P24 successively, and three resistance are denoted as R1~3, one with it is non- Door is denoted as NAND;Wherein:
The source electrode of PMOS transistor P19 and P20 are connect with VDD;PMOS transistor P19 grids are connect with node C;
MOS transistor P20 grids are connect with node D;PMOS transistor P22 grids are connect with node CB;PMOS transistor P24 grid Pole is connect with node DB;PMOS transistor P19 drain electrodes are connect with PMOS transistor P22 source electrodes and control voltage signal VF; PMOS transistor P20 drain electrodes are connect with PMOS transistor P24 source electrodes and control voltage signal VS;PMOS transistor P22 drain electrodes It is connect with PMOS transistor P24 drain electrodes with PMOS transistor P21 source electrodes and PMOS transistor P23 source electrodes;
Node A and node B is connected with NAND gate NAND inputs;NAND gate NAND outputs and PMOS transistor P21 grids and reverse phase Device I9 input connections;Phase inverter I9 outputs are connect with PMOS transistor P23 grids;The upper ends resistance R3 are connect with VDD;Under resistance R3 End is connect with PMOS transistor P21 drain electrodes and the upper ends resistance R2;On the lower ends resistance R2 and PMOS transistor P23 drain electrodes and resistance R1 End connection;The lower ends resistance R1 are connected with NMOS transistor N10 drain electrodes, and NMOS transistor N10 source electrodes are connect with GND;NMOS crystal Pipe N10 grids are connect with signal SAE.
CN201820411822.2U 2018-03-26 2018-03-26 Offset voltage adaptive digital calibration type sense amplifier Withdrawn - After Issue CN207833929U (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231100A (en) * 2018-03-26 2018-06-29 安徽大学 Offset voltage adaptive digital calibration type sense amplifier
CN111986719A (en) * 2020-09-10 2020-11-24 苏州兆芯半导体科技有限公司 Current determination method
CN112767975A (en) * 2021-02-10 2021-05-07 长鑫存储技术有限公司 Sense amplifier and control method thereof
CN113470705A (en) * 2020-03-30 2021-10-01 长鑫存储技术有限公司 Sense amplifier, memory and data reading method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231100A (en) * 2018-03-26 2018-06-29 安徽大学 Offset voltage adaptive digital calibration type sense amplifier
CN108231100B (en) * 2018-03-26 2023-09-19 安徽大学 Offset voltage adaptive digital calibration sense amplifier
CN113470705A (en) * 2020-03-30 2021-10-01 长鑫存储技术有限公司 Sense amplifier, memory and data reading method
CN113470705B (en) * 2020-03-30 2024-05-14 长鑫存储技术有限公司 Sense amplifier, memory and data reading method
CN111986719A (en) * 2020-09-10 2020-11-24 苏州兆芯半导体科技有限公司 Current determination method
CN111986719B (en) * 2020-09-10 2022-11-29 苏州兆芯半导体科技有限公司 Current determination method
CN112767975A (en) * 2021-02-10 2021-05-07 长鑫存储技术有限公司 Sense amplifier and control method thereof
CN112767975B (en) * 2021-02-10 2022-04-12 长鑫存储技术有限公司 Sense amplifier and control method thereof

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