CN207833929U - Offset voltage adaptive digital calibration type sense amplifier - Google Patents

Abstract

The utility model discloses an offset voltage self-adaptive digital calibration type sensitive amplifier, which is a sensitive amplifier circuit structure that can effectively reduce the offset voltage. The structure uses a simple peripheral circuit to realize the calibration compensation of the offset voltage of the sensitive amplifier and the compensation state lock The memory operation achieves the purpose of greatly reducing the offset voltage; at the same time, due to the reduction of the offset voltage, the design margin of the SRAM read circuit is effectively improved, thereby reducing the power consumption generated when the unit is read, and improving The data read speed of SRAM is improved.

Description

Offset Voltage Adaptive Digital Calibration Sensitive Amplifier

technical field

The utility model relates to the field of integrated circuit design, in particular to an offset voltage adaptive digital calibration type sensitive amplifier.

Background technique

With the rapid development of the integrated circuit industry in recent years, the high-speed and low-power characteristics of Static Random Access Memory (SRAM) play an increasingly important role in circuit design. The read operation of SRAM requires more For a long time, in order to improve the performance of SRAM, a sense amplifier (Sense Amplifier, abbreviated as SA) is usually used in the data readout path. Under ideal conditions, only a small voltage difference needs to be input, and the sense amplifier can feedback the logic. "0" and "1". However, due to the fluctuation of process parameters, device parameters such as transconductance and threshold voltage are mismatched. For SA, an offset voltage will be generated, which will cause small swing input signals to be misamplified by the sense amplifier. The structure of the traditional voltage type SA circuit is shown in Figure 1; in order to reduce the offset voltage of SA, the following technologies exist:

(1) As shown in Figure 2, a Reconfigurable Sense Amplifier circuit proposed by M.Khayatzadeh and F.Frustaci in 2015, the design scheme is to split the traditional voltage-type sense amplifier into two parallel sense amplifier groups, At the same time, the chip area is kept consistent with the traditional voltage type SA. Compared with the traditional voltage type SA, this structure has four different combinations. Under the condition of selecting the best combination, the structure has better anti-offset voltage capability, but the logic judgment of the best combination of the circuit is more complicated.

(2) As shown in Figure 3, the Robust Latch-Type SA circuit designed by T.Song and S.M.Lee in 2010 is used to reduce the influence of leakage current and offset voltage, and improve the read data of SA Accuracy, but the circuit design has little effect on reducing the offset voltage, while prolonging the working time of SA and reducing the speed of SA.

Utility model content

The purpose of the utility model is to provide an offset voltage self-adaptive digital calibration type sensitive amplifier, which is a circuit structure that can effectively reduce the offset voltage of the sensitive amplifier, thereby speeding up the reading speed of the static random access memory and reducing the power consumption of unit reading.

The purpose of this utility model is achieved by the following technical solutions:

An offset voltage self-adaptive digital calibration type sensitive amplifier, comprising: a main part of the sensitive amplifier connected to each other, a calibration latch circuit, and a reference voltage generating circuit;

Wherein, the calibration latch circuit includes: ten PMOS transistors, four NMOS transistors, one OR gate and eight inverters; the ten PMOS transistors are sequentially marked as P9～P18, and the four NMOS transistors are sequentially marked as N6～ N9, the eight inverters are marked as I1~I8 in turn, and the OR gate is marked as OR; where:

The source of the PMOS transistor P9 is connected to VDD; the gate of the PMOS transistor P10 is connected to the output node OUT; the source of the PMOS transistor P10 is connected to the drain of the PMOS transistor P9;

The gate of the PMOS transistor P11 is connected to the calibration signal CK; the source of the PMOS transistor P11 is connected to the drain of the PMOS transistor P10; the drain of the PMOS transistor P11 is connected to the output of the inverter I1, and the output of the inverter I1 is marked as node A; The output of I1 is connected to the input of inverter I2; the output of inverter I2 is connected to the input of inverter I1, and the input of inverter I1 is marked as node AB;

The gate of the NMOS transistor N6 is connected to the reset signal RSET; the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P11; the source of the NMOS transistor N6 is connected to GND;

The source of the PMOS transistor P12 is connected to VDD; the gate of the PMOS transistor P13 is connected to the output node OUTB; the source of the PMOS transistor P13 is connected to the drain of the PMOS transistor P12;

The gate of the PMOS transistor P14 is connected to the calibration signal CK; the source of the PMOS transistor P14 is connected to the drain of the PMOS transistor P13; the drain of the PMOS transistor P14 is connected to the input of the inverter I3, and the input of the inverter I3 is marked as node B; The output of I3 is connected to the input of the inverter I4, and the input of the inverter I4 is marked as node BB; the output of the inverter I4 is connected to the input of the inverter I3;

The gate of the NMOS transistor N7 is connected to the reset signal RSET; the drain of the NMOS transistor N7 is connected to the drain of the PMOS transistor P14; the source of the NMOS transistor N7 is connected to GND;

The source of the PMOS transistor P15 is connected to VDD; the gate of the PMOS transistor P15 is connected to the node AB; the drain of the PMOS transistor P15 is connected to the source of the PMOS transistor P16; the gate of the PMOS transistor P16 is connected to the OR output of the OR gate; the drain of the PMOS transistor P16 is connected to The output of inverter I5 is connected, and the output of inverter I5 is marked as node C; the output of inverter I5 is connected to the input of inverter I6; the output of inverter I6 is connected to the input of inverter I5, and the input of inverter I5 is marked as node CB; Node C is connected to the OR input of the OR gate;

The gate of the NMOS transistor N8 is connected to the reset signal RSET; the drain of the NMOS transistor N8 is connected to the drain of the PMOS transistor P16; the source of the NMOS transistor N8 is connected to GND;

The source of the PMOS transistor P17 is connected to VDD; the gate of the PMOS transistor P17 is connected to the node BB; the drain of the PMOS transistor P17 is connected to the source of the PMOS transistor P18; the gate of the PMOS transistor P18 is connected to the OR output of the OR gate; the drain of the PMOS transistor P18 is connected to The input of the inverter I7 is connected, and the input of the inverter I7 is marked as node D; the input of the inverter I7 is connected to the output of the inverter I8; the output of the inverter I7 is connected to the input of the inverter I8, and the input of the inverter I8 is marked as DB; the node D is connected to the OR input of the OR gate; the gate of the NMOS transistor N9 is connected to the reset signal RSET; the drain of the NMOS transistor N9 is connected to the drain of the PMOS transistor P18; the source of the NMOS transistor N9 is connected to GND.

It can be seen from the above-mentioned technical solution provided by the utility model that the utility model utilizes a simple peripheral circuit to realize SA offset voltage calibration compensation and calibration state latch operation, which can effectively reduce the SA offset voltage and improve the read operation speed of SRAM and power consumption.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention , for those skilled in the art, other drawings can also be obtained based on these drawings without creative work.

Fig. 1 is the structural representation of the traditional voltage type SA circuit that background technology provides;

FIG. 2 is a schematic structural diagram of the Reconfigurable SA circuit provided by the background technology;

Fig. 3 is the structural representation of the Robust Latch-Type SA circuit that background technology provides;

Fig. 4 is a structural schematic diagram of an offset voltage self-adaptive digital calibration type sense amplifier provided by an embodiment of the present invention;

Fig. 5 is the waveform simulation diagram before and after calibration of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the present invention;

FIG. 6 is a simulation relationship diagram between the offset voltage adaptive digital calibration type sense amplifier transmission gate NMOS grid voltage and the offset voltage offset provided by the embodiment of the present invention;

Fig. 7 is a flow chart of the calibration technology of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the present invention;

Fig. 8 is the simulation state diagram of the calibration latch module of the offset voltage adaptive digital calibration type sense amplifier provided by the embodiment of the present invention;

Fig. 9 is the conventional voltage-type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model under the cadence simulation software for 2500 Monte Carlo simulations Statistical chart of offset voltage (simulation conditions: VDD: 1.2V; Corner: FF, FS, SF, SS; Temperature: -40°C; 25°C; 25°C; 125°C);

Fig. 10 is the traditional voltage type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage adaptive digital calibration type sense amplifier offset voltage columnar distribution diagram provided by the embodiment of the utility model (simulation condition is: VDD: 1.2 V; Corner: TT; Temperature: 25°C).

Detailed ways

The technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. . Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present utility model.

The embodiment of the utility model provides an offset voltage self-adaptive digital calibration type sensitive amplifier, as shown in Figure 4, which mainly includes: a main part of the sensitive amplifier connected to each other, a calibration latch circuit, and a reference voltage generating circuit;

Wherein, the main part of the sensitive amplifier implements signal amplification, as shown in Figure 4(a), which includes: five NMOS transistors and eight PMOS transistors, the five NMOS transistors are sequentially marked as N1-N5, and the eight PMOS transistors They are recorded as P1～P8 in turn; NMOS transistor N1 and PMOS transistor P5 form an inverter, NMOS transistor N2 and PMOS transistor P6 form another inverter, and these two inverters form a cross-coupling structure; the cross-coupling structure The transmission gate formed by two NMOS and two PMOS transistors between them is isolated; at the same time, the sense amplifier is isolated from BL and BLB through PMOS transistor P1 and PMOS transistor P2 correspondingly, and the sense amplifier is separated from the sense amplifier through PMOS transistor P3 and PMOS transistor P4 VDD is isolated, and the sense amplifier is isolated from GND through NMOS transistor N3; where:

The bit line BL is connected to the drain of the PMOS transistor P1; the bit line BLB is connected to the drain of the PMOS transistor P2; the enable signal SAE is connected to the gate of the PMOS transistor P1 and the gate of the PMOS transistor P2; the source of the PMOS transistor P1 connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; the source of the PMOS transistor P2 is connected to the drain of the PMOS transistor P6 and the drain of the NMOS transistor N2;

The precharge signal PRE is connected to the gate of the PMOS transistor P3 and the gate of the PMOS transistor P4; the drain of the PMOS transistor P3 is connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; the drain of the PMOS transistor P4 is connected to the PMOS The drain of the transistor P6 is connected to the drain of the NMOS transistor N2; the drain of the NMOS transistor N3 is connected to the source of the NMOS transistor N1 and the source of the NMOS transistor N2; the enabling signal SAE is connected to the gate of the transistor N3;

The drain of the NMOS transistor N5 in the transmission gate is connected to the gate of the PMOS transistor P6 and the gate of the NMOS transistor N2; the drain of the PMOS transistor P7 in the transmission gate is connected to the gate of the PMOS transistor P6 and the gate of the NMOS transistor N2; The source of the NMOS transistor N5 in the transmission gate is connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; the source of the PMOS transistor P7 in the transmission gate is connected to the drain of the PMOS transistor P5 and the drain of the NMOS transistor N1; The drain of the NMOS transistor N4 in the transmission gate is connected to the gate of the PMOS transistor P5 and the gate of the NMOS transistor N1; the drain of the PMOS transistor P8 in the transmission gate is connected to the gate of the PMOS transistor P5 and the gate of the NMOS transistor N1; The source of the NMOS transistor N4 in the transmission gate is connected to the drain of the PMOS transistor P6 and the drain of the NMOS transistor N2; the source of the PMOS transistor P8 in the transmission gate is connected to the drain of the PMOS transistor P6 and the drain of the NMOS transistor N2;

VDD is connected to the sources of the PMOS transistors P3 , P4 , P5 and P6 ; GND is connected to the source of the NMOS transistor N3 and the gates of the PMOS transistors P7 and P8 .

In the embodiment of the present invention, the drain of the NMOS transistor N5 is connected to the node Q, the source of the NMOS transistor N5 is connected to the output node OUT, the gate of the NMOS transistor N5 is connected to the control voltage signal VF; the drain of the NMOS transistor N4 is connected to The node QB is connected, the source of the NMOS transistor N4 is connected to the output node OUTB, and the gate of the NMOS transistor N4 is connected to its control voltage signal VS, so that the potential change of the output node can be controlled by VF and VS, which helps to greatly reduce the sensitivity amplifier offset voltage.

As shown in Figure 4(b), the calibration latch circuit includes: ten PMOS transistors, four NMOS transistors, one OR gate and eight inverters; The NMOS transistors are marked as N6-N9 in turn, the eight inverters are marked as I1-I8 in turn, and the OR gate is marked as OR; where:

The source of the PMOS transistor P9 is connected to VDD; the gate of the PMOS transistor P10 is connected to the output node OUT; the source of the PMOS transistor P10 is connected to the drain of the PMOS transistor P9;

The gate of the PMOS transistor P11 is connected to the calibration signal CK; the source of the PMOS transistor P11 is connected to the drain of the PMOS transistor P10; the drain of the PMOS transistor P11 is connected to the output of the inverter I1, and the output of the inverter I1 is marked as node A; The output of I1 is connected to the input of inverter I2; the output of inverter I2 is connected to the input of inverter I1, and the input of inverter I1 is marked as node AB;

The gate of the NMOS transistor N6 is connected to the reset signal RSET; the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P11; the source of the NMOS transistor N6 is connected to GND;

The source of the PMOS transistor P12 is connected to VDD; the gate of the PMOS transistor P13 is connected to the output node OUTB; the source of the PMOS transistor P13 is connected to the drain of the PMOS transistor P12;

The gate of the PMOS transistor P14 is connected to the calibration signal CK; the source of the PMOS transistor P14 is connected to the drain of the PMOS transistor P13; the drain of the PMOS transistor P14 is connected to the input of the inverter I3, and the input of the inverter I3 is marked as node B; The output of I3 is connected to the input of the inverter I4, and the input of the inverter I4 is marked as node BB; the output of the inverter I4 is connected to the input of the inverter I3;

The gate of the NMOS transistor N7 is connected to the reset signal RSET; the drain of the NMOS transistor N7 is connected to the drain of the PMOS transistor P14; the source of the NMOS transistor N7 is connected to GND;

The source of the PMOS transistor P15 is connected to VDD; the gate of the PMOS transistor P15 is connected to the node AB; the drain of the PMOS transistor P15 is connected to the source of the PMOS transistor P16; the gate of the PMOS transistor P16 is connected to the OR output of the OR gate; the drain of the PMOS transistor P16 is connected to The output of inverter I5 is connected, and the output of inverter I5 is marked as node C; the output of inverter I5 is connected to the input of inverter I6; the output of inverter I6 is connected to the input of inverter I5, and the input of inverter I5 is marked as node CB; Node C is connected to the OR input of the OR gate;

The gate of the NMOS transistor N8 is connected to the reset signal RSET; the drain of the NMOS transistor N8 is connected to the drain of the PMOS transistor P16; the source of the NMOS transistor N8 is connected to GND;

The source of the PMOS transistor P17 is connected to VDD; the gate of the PMOS transistor P17 is connected to the node BB; the drain of the PMOS transistor P17 is connected to the source of the PMOS transistor P18; the gate of the PMOS transistor P18 is connected to the OR output of the OR gate; the drain of the PMOS transistor P18 is connected to The input of the inverter I7 is connected, and the input of the inverter I7 is marked as node D; the input of the inverter I7 is connected to the output of the inverter I8; the output of the inverter I7 is connected to the input of the inverter I8, and the input of the inverter I8 is marked as DB; the node D is connected to the OR input of the OR gate; the gate of the NMOS transistor N9 is connected to the reset signal RSET; the drain of the NMOS transistor N9 is connected to the drain of the PMOS transistor P18; the source of the NMOS transistor N9 is connected to GND.

As shown in Figure 4(c), the reference voltage generation circuit includes: an NMOS transistor, six PMOS transistors, three resistors and a NAND gate; one NMOS transistor is marked as N10, and the six PMOS transistors are marked as P19 in turn ~P24, three resistors are marked as R1~R3, and one NAND gate is marked as NAND; among them:

The sources of PMOS transistors P19 and P20 are connected to VDD; the gate of PMOS transistor P19 is connected to node C;

The gate of the MOS transistor P20 is connected to the node D; the gate of the PMOS transistor P22 is connected to the node CB; the gate of the PMOS transistor P24 is connected to the node DB; the drain of the PMOS transistor P19 is connected to the source of the PMOS transistor P22 and the control voltage signal VF; the PMOS transistor The drain of P20 is connected to the source of PMOS transistor P24 and the control voltage signal VS; the drain of PMOS transistor P22 and the drain of PMOS transistor P24 are connected to the source of PMOS transistor P21 and the source of PMOS transistor P23;

Nodes A and B are connected to the NAND input of the NAND gate; the NAND output of the NAND gate is connected to the gate of the PMOS transistor P21 and the input of the inverter I9; the output of the inverter I9 is connected to the gate of the PMOS transistor P23; the upper end of the resistor R3 is connected to VDD Connection; the lower end of resistor R3 is connected to the drain of PMOS transistor P21 and the upper end of resistor R2; the lower end of resistor R2 is connected to the drain of PMOS transistor P23 and the upper end of resistor R1; the lower end of resistor R1 is connected to the drain of NMOS transistor N10, and the source of NMOS transistor N10 is connected to GND connected; the gate of the NMOS transistor N10 is connected to the signal SAE.

Specifically, in the offset voltage adaptive digital calibration type sense amplifier circuit provided by the embodiment of the utility model, compared with the traditional SA, a transmission gate is added between OUT and Q (OUTB and QB). The NMOS gate voltage of the transmission gate is VF(VS), and the PMOS gate voltage is always grounded. The purpose of this design is to reduce the offset voltage due to threshold voltage differences by controlling the discharge rate of the nodes. Compared with the Robust Latch-Type SA structure (structure shown in Figure 3), the utility model replaces BL/BLB with VF/VS, so the offset voltage adaptive digital calibration type sense amplifier provided by the embodiment of the utility model can use digital The calibration technique achieves the effect of greatly reducing the offset voltage. The Robust Latch-Type SA structure uses the signal SAE instead of GND to connect the gate of the PMOS in the transmission gate, causing the PMOS of the transmission gate to be in an off state during offset calibration. Due to the problem of threshold loss when NMOS transmits high level, node Q/QB cannot be charged to VDD when SA is working.

At the same time, the utility model utilizes the self-adaptive digital calibration technology of the offset voltage self-adaptive digital calibration type sensitive amplifier, and only needs to calibrate two cycles before the normal operation of the SA, and no operation is required. The calibration technology of the utility model calculates the optimal offset compensation amount through theoretical analysis, and the digital calibration technology can realize two calibrations, and the effect is more obvious. The latching technology can save the calibration process to achieve the effect of one calibration and multiple uses.

The offset voltage adaptive digital calibration type sensitive amplifier provided by the utility model is in the precharge stage, the PRE signal is low level, the SAE signal is also low level, the PMOS transistors P3 and P4 are turned on, and the storage nodes OUT, OUTB and node Both Q and QB are precharged to a high level; when the precharge phase ends and SA enters the working phase, the PRE signal is high, the SAE signal is high, the PMOS transistors P3 and P4 are cut off, the circuit stops precharging, and the transistor P1 and P2 are cut off, and storage nodes OUT/OUTB are isolated from BL/BLB. Because there is a voltage difference between BL and BLB in the cell tube discharge path, this difference will also be reflected on OUT and OUTB, and the cross-coupling structure of SA will amplify this voltage difference. It is worth mentioning that if this voltage difference is less than the SA offset voltage, there will be an error reading situation. Therefore, the conventional practice is to change the SAE signal to a high level when the voltage difference between BL and BLB is large. The SA provided by the embodiment of the utility model can judge the positive and negative of the offset voltage and the approximate range through the peripheral circuit, and change the magnitude of the VF or VS voltage to control the current intensity passing through the NMOS on the transmission gate. The voltage difference caused by the mismatch of N1 and N2 thresholds reduces the offset voltage. Compared with the method of extending the discharge time of the bit line to ensure accuracy in the traditional voltage-type SA, the SA provided by the embodiment of the utility model can reduce the discharge time of the bit line and improve power consumption and speed.

In order to more clearly show the technical solution and the technical effects produced by the utility model, the following will introduce the theoretical analysis of the self-adaptive calibration latch sense amplifier circuit provided by the embodiment of the utility model in conjunction with Fig. 5 to Fig. 8 and simulation verification process; in conjunction with Fig. 9, Fig. 10, the performance of the self-adaptive calibration latch sense amplifier circuit provided by the embodiment of the utility model is carried out with the traditional voltage type SA circuit and the Robust Latch-Type SA circuit provided by the background technology Contrast; its specific content is as follows:

(1) As shown in FIG. 5 , it is a waveform simulation diagram before and after calibration of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model. The solid line, that is, the "(A)" type curve corresponds to the result after calibration. At this time, VF is connected to the reference voltage, and VS is connected to VDD; the dotted line, that is, the "(B)" type curve corresponds to the result before calibration. At this time, VF and Both VS are connected to VDD. The simulation results show that the voltage difference between OUT and OUTB, Q and QB is significantly reduced after calibration, and the offset voltages before and after calibration are 30mV and 10mV respectively. Therefore, the effect of reducing the offset voltage can be achieved by controlling the gate voltage of the transmission gate NMOS.

(2) As shown in FIG. 6 , it is a simulation relationship diagram of the transmission gate NMOS grid voltage and the offset voltage offset in the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model. According to the conclusion in Figure 5 that controlling the NMOS gate voltage of the transmission gate can reduce the offset voltage, Figure 6 verifies the relationship between the NMOS gate voltage of the transmission gate and the offset voltage offset (VF potential changes, VS is always connected to VDD) , it can be found that the simulation result is almost a straight line, so we conclude that the NMOS gate voltage and the offset voltage offset are linear.

(3) As shown in Figure 7, the calibration flow chart of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model; in conjunction with the calibration latch circuit corresponding to the SA of the utility model shown in Figure 4 (b) The reference voltage generating circuit corresponding to the SA of the utility model shown in Fig. 4(c) first precharges and discharges the circuit, and then judges the level of the output node potential. If OUT is "0", the potentials of nodes A and C rise , VF is connected to reference voltage 1; if OUT is "1", the potentials of nodes B and D rise, and VS is connected to reference voltage 1. After entering the second calibration cycle, the circuit is precharged and discharged under the condition of no bit line voltage difference. If the data output by the output node is consistent with the previous cycle, the calibration ends; if the output data is not consistent, the reference voltage 1 Replace it with reference voltage 2 and connect it to VF or VS, and the calibration ends.

(4) As shown in FIG. 8 , it is a simulation state diagram of the calibration latch module of the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model. Figure 8 shows two different situations in the calibration cycle, in which Figure 8(a) outputs "0" in the first cycle OUT, and nodes A and C increase VF to access the reference voltage 1; the second After the reference voltage 1 is connected in the first cycle, the offset voltage calibration compensation has an overcompensation phenomenon, and the output result of OUT changes from "0" in the previous cycle to "1", so the potential of node B rises and VF is connected to the reference voltage 2 Calibration is complete. In Figure 8(b), the OUT output result is "0" in the first cycle, and the nodes A and C increase VF to connect to the reference voltage 1; after the reference voltage 1 is connected to the second cycle, the offset voltage calibration compensation is not Overcompensation occurs, the OUT output is consistent with the previous cycle, the potentials of nodes B and D do not change, VF continues to be connected to the reference voltage 1, and the calibration ends.

(5) As shown in Figure 9, the traditional voltage type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage self-adaptive digital calibration type sense amplifier provided by the embodiment of the utility model are carried out under the cadence simulation software Statistical diagram of offset voltage for 2500 times of Monte Carlo simulation; three columns in each group correspond to traditional voltage-type SA, Robust Latch-Type SA and the simulation results of SA provided by the embodiment of the utility model. It can be seen from the data statistics in Figure 9 that the Robust Latch-Type SA has improved compared with the traditional voltage-type SA, but the improvement effect is very small. Compared with the traditional voltage type SA and the Robust Latch-Type SA, the offset voltage self-adaptive digital calibration type sensitive amplifier provided by the embodiment of the utility model has a large reduction in the offset voltage, even in the SF process with the worst lifting effect Under the angle, compared with the traditional voltage type SA, it still maintains the reduction effect of 49.9%, and compared with the Robust Latch-Type SA, the reduction is 35.8%.

(6) As shown in Figure 10, the traditional voltage type SA circuit provided by the background technology, the Robust Latch-Type SA circuit and the offset voltage self-adaptive digital calibration type sense amplifier offset voltage columnar distribution diagram provided by the embodiment of the present invention. The simulation conditions are: (VDD: 1.2V; Corner: TT; Temperature: 25°C). Among them, Fig. 10(a) is the histogram of the simulation data of the traditional voltage-type SA offset voltage, the mean value μ is 74.61uV, and the standard deviation σ is 15.15mV. Fig. 10(b) is the histogram of the simulation data of the RobustLatch-Type SA offset voltage. You can see Compared with the traditional voltage-type SA histogram, the distribution is more dense, and the standard deviation σ drops to 11.90mV. Figure 10(c) is the histogram of the offset voltage self-adaptive digital calibration type sense amplifier offset voltage simulation data provided by the embodiment of the utility model , the density of the histogram is greatly increased, and the standard deviation σ is reduced to 6.499mV. Compared with the traditional voltage-type SA, the offset voltage of the offset voltage self-adaptive digital calibration type sensitive amplifier provided by the embodiment of the utility model is reduced by 57%, and compared with the Robust Latch-Type SA, the offset voltage is reduced by 45.4%.

In summary, the utility model provides an offset voltage self-adaptive digital calibration type sense amplifier, which can effectively reduce the offset voltage of the sense amplifier SA, and the circuit structure uses a simple peripheral circuit to realize calibration compensation and compensation of the offset voltage of the sense amplifier The state latch operation achieves the purpose of greatly reducing the offset voltage; at the same time, due to the reduction of the offset voltage, the design margin of the SRAM read circuit is effectively improved, thereby reducing the power consumption generated when the unit is read, And the data reading speed of the SRAM is improved.

The above is only a preferred embodiment of the utility model, but the scope of protection of the utility model is not limited thereto, and any person familiar with the technical field can easily think of All changes or replacements should fall within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be based on the protection scope of the claims.

Claims (3)

1. a kind of offset voltage adaptive digital calibration type sense amplifier, which is characterized in that including：The sensitive of interconnection is put Big device main part, calibration latch cicuit and reference voltage generating circuit；

Wherein, the calibration latch cicuit includes：Ten PMOS transistors, four NMOS transistors, one or and eight Phase inverter；Ten PMOS transistors are denoted as P9~P18 successively, and four NMOS transistors are denoted as N6~N9, eight phase inverters successively It is denoted as I1~I8 successively or door is denoted as OR；Wherein：

PMOS transistor P9 source electrodes are connect with VDD；PMOS transistor P10 grids are connect with output node OUT；PMOS transistor P10 source electrodes are connected with PMOS transistor P9 drain electrodes；

PMOS transistor P11 grids are connect with calibration signal CK；PMOS transistor P11 source electrodes connect with PMOS transistor P10 drain electrodes It connects；PMOS transistor P11 drain electrodes are connected with phase inverter I1 outputs, and phase inverter I1 outputs are denoted as node A；Phase inverter I1 output with it is anti- The I2 input connections of phase device；Phase inverter I2 outputs are connected with phase inverter I1 inputs, and phase inverter I1 inputs are denoted as node AB；

NMOS transistor N6 grids are connect with reset signal RSET；NMOS transistor N6 drain electrodes connect with PMOS transistor P11 drain electrodes It connects；NMOS transistor N6 source electrodes are connect with GND；

PMOS transistor P12 source electrodes are connect with VDD；PMOS transistor P13 grids are connect with output node OUTB；PMOS transistor P13 source electrodes are connected with PMOS transistor P12 drain electrodes；

PMOS transistor P14 grids are connect with calibration signal CK；PMOS transistor P14 source electrodes connect with PMOS transistor P13 drain electrodes It connects；PMOS transistor P14 drain electrodes are connected with phase inverter I3 inputs, and phase inverter I3 inputs are denoted as node B；Phase inverter I3 output with it is anti- The I4 input connections of phase device, phase inverter I4 inputs are denoted as node BB；Phase inverter I4 outputs are connected with phase inverter I3 inputs；

NMOS transistor N7 grids are connect with reset signal RSET；NMOS transistor N7 drain electrodes connect with PMOS transistor P14 drain electrodes It connects；NMOS transistor N7 source electrodes are connect with GND；

PMOS transistor P15 source electrodes are connect with VDD；PMOS transistor P15 grids are connect with node AB；PMOS transistor P15 leakages Pole is connect with PMOS transistor P16 source electrodes；PMOS transistor P16 grids and/or door OR output connections；PMOS transistor P16 drain electrodes It is connected with phase inverter I5 outputs, phase inverter I5 outputs are denoted as node C；Phase inverter I5 outputs are connected with phase inverter I6 inputs；Reverse phase Device I6 outputs are denoted as node CB with phase inverter I5 input connection phase inverter I5 inputs；Node C and/or door OR input connections；

NMOS transistor N8 grids are connect with reset signal RSET；NMOS transistor N8 drain electrodes connect with PMOS transistor P16 drain electrodes It connects；NMOS transistor N8 source electrodes are connect with GND；

PMOS transistor P17 source electrodes are connect with VDD；PMOS transistor P17 grids are connect with node BB；PMOS transistor P17 leakages Pole is connect with PMOS transistor P18 source electrodes；PMOS transistor P18 grids and/or door OR output connections；PMOS transistor P18 drain electrodes It is connected with phase inverter I7 inputs, phase inverter I7 inputs are denoted as node D；Phase inverter I7 inputs are connected with phase inverter I8 outputs；Reverse phase Device I7 outputs are connected with phase inverter I8 inputs, and phase inverter I8 inputs are denoted as DB；Node D and/or door OR input connections；NMOS crystal Pipe N9 grids are connect with reset signal RSET；NMOS transistor N9 drain electrodes are connected with PMOS transistor P18 drain electrodes；NMOS transistor N9 source electrodes are connect with GND.

2. a kind of offset voltage adaptive digital calibration type sense amplifier according to claim 1, which is characterized in that institute Stating sense amplifier main part includes：Five NMOS transistors and eight PMOS transistors, five NMOS transistors are remembered successively For N1~N5, eight PMOS transistors are denoted as P1~P8 successively；Wherein NMOS transistor N1 and PMOS transistor P5 constitute one Phase inverter, NMOS transistor N2 and PMOS transistor P6 constitute another phase inverter, the two phase inverters form cross-couplings knot Structure；Separated by the transmission gate that two NMOS and two PMOS transistors are formed between cross coupling structure；Meanwhile also passing through PMOS Transistor P1, PMOS transistor P2 are corresponding, and sense amplifier is isolated with BL, BLB, brilliant by PMOS transistor P3 and PMOS Body pipe P4 keeps apart sense amplifier and VDD, is kept apart sense amplifier and GND by NMOS transistor N3；Wherein：

Bit line BL is connect with the drain electrode of PMOS transistor P1；Bit line BLB is connect with the drain electrode of PMOS transistor P2；Enable signal SAE is connect with the grid of the grid of PMOS transistor P1 and PMOS transistor P2；The source electrode of PMOS transistor P1 is brilliant with PMOS The drain electrode of body pipe P5 and the drain electrode connection of NMOS transistor N1；The drain electrode of the source electrode and PMOS transistor P6 of PMOS transistor P2 And the drain electrode connection of NMOS transistor N2；

Preliminary filling signal PRE is connect with the grid of the grid of PMOS transistor P3 and PMOS transistor P4；PMOS transistor P3's Drain electrode is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1；The drain electrode of PMOS transistor P4 is brilliant with PMOS The drain electrode of body pipe P6 and the drain electrode connection of NMOS transistor N2；The source electrode of the drain electrode and NMOS transistor N1 of NMOS transistor N3 And the source electrode connection of NMOS transistor N2；Enable signal SAE is connect with the grid of transistor N3；

The drain electrode of NMOS transistor N5 is connect with the grid of the grid of PMOS transistor P6 and NMOS transistor N2 in transmission gate； The drain electrode of PMOS transistor P7 is connected with the grid of the grid of PMOS transistor P6 and NMOS transistor N2 in transmission gate；Transmission The source electrode of NMOS transistor N5 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1 in door；In transmission gate The source electrode of PMOS transistor P7 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1；NMOS in transmission gate The drain electrode of transistor N4 is connect with the grid of the grid of PMOS transistor P5 and NMOS transistor N1；PMOS crystal in transmission gate The drain electrode of pipe P8 is connected with the grid of the grid of PMOS transistor P5 and NMOS transistor N1；NMOS transistor N4 in transmission gate Source electrode connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2；The source of PMOS transistor P8 in transmission gate Pole is connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2；

VDD is connect with the source electrode of PMOS transistor P3, P4, P5 and P6；The source electrode and PMOS crystal of GND and NMOS transistor N3 The grid of pipe P7 and P8 connect；

The drain electrode of the NMOS transistor N5 is connect with node Q, and the source electrode of NMOS transistor N5 is connect with output node OUT, The grid of NMOS transistor N5 is connect with its control voltage signal VF；The drain electrode of NMOS transistor N4 is connect with node QB, NMOS The source electrode of transistor N4 is connect with output node OUTB, and the grid of NMOS transistor N4 is connect with its control voltage signal VS.

3. a kind of offset voltage adaptive digital calibration type sense amplifier according to claim 2, which is characterized in that institute Stating reference voltage generating circuit includes：One NMOS transistor, three resistance and a NAND gate and six PMOS transistors；One A NMOS transistor is denoted as N10, and six PMOS transistors are denoted as P19~P24 successively, and three resistance are denoted as R1~3, one with it is non- Door is denoted as NAND；Wherein：

The source electrode of PMOS transistor P19 and P20 are connect with VDD；PMOS transistor P19 grids are connect with node C；

MOS transistor P20 grids are connect with node D；PMOS transistor P22 grids are connect with node CB；PMOS transistor P24 grid Pole is connect with node DB；PMOS transistor P19 drain electrodes are connect with PMOS transistor P22 source electrodes and control voltage signal VF； PMOS transistor P20 drain electrodes are connect with PMOS transistor P24 source electrodes and control voltage signal VS；PMOS transistor P22 drain electrodes It is connect with PMOS transistor P24 drain electrodes with PMOS transistor P21 source electrodes and PMOS transistor P23 source electrodes；

Node A and node B is connected with NAND gate NAND inputs；NAND gate NAND outputs and PMOS transistor P21 grids and reverse phase Device I9 input connections；Phase inverter I9 outputs are connect with PMOS transistor P23 grids；The upper ends resistance R3 are connect with VDD；Under resistance R3 End is connect with PMOS transistor P21 drain electrodes and the upper ends resistance R2；On the lower ends resistance R2 and PMOS transistor P23 drain electrodes and resistance R1 End connection；The lower ends resistance R1 are connected with NMOS transistor N10 drain electrodes, and NMOS transistor N10 source electrodes are connect with GND；NMOS crystal Pipe N10 grids are connect with signal SAE.