CN207833929U - Offset voltage adaptive digital calibration type sense amplifier - Google Patents
Offset voltage adaptive digital calibration type sense amplifier Download PDFInfo
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- CN207833929U CN207833929U CN201820411822.2U CN201820411822U CN207833929U CN 207833929 U CN207833929 U CN 207833929U CN 201820411822 U CN201820411822 U CN 201820411822U CN 207833929 U CN207833929 U CN 207833929U
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Abstract
The utility model discloses a kind of offset voltage adaptive digital calibration type sense amplifiers, it is a kind of sensitive amplifier circuit structure that can effectively reduce offset voltage, the structure realizes the compensation for calibrating errors and compensating coefficient latch operation of sense amplifier offset voltage using simple peripheral circuit, has achieved the purpose that offset voltage is greatly lowered；Simultaneously because the reduction of offset voltage, effectively improves the design margin of Static RAM reading circuit, the power consumption consumption generated when unit is read is thereby reduced, and improve the data reading speed of Static RAM.
Description
Technical field
The utility model is related to IC design field more particularly to a kind of spirits of offset voltage adaptive digital calibration type
Quick amplifier.
Background technology
The high speed development of integrated circuit industry in recent years, Static RAM (Static Random Access
Memory is abbreviated as SRAM) characteristic of high-speed low-power-consumption plays the part of more and more important ingredient, the reading behaviour of SRAM in circuit design
Make to need the more time relative to write operation, in order to promote the performance of SRAM, generally use is sensitive in data read-out path puts
Big device (Sense Amplifier, be abbreviated as SA), under ideal conditions, it is only necessary to input small voltage difference, sense amplifier
" 0 " and " 1 " in logic can be fed back.But due to the fluctuation of technological parameter so that such as mutual conductance, threshold voltage device
Parameter generates mismatch, for SA, it will generates offset voltage, and then causes small amplitude of oscillation input signal by sense amplifier
Mistake is amplified.The structure of conventional voltage type SA circuits is as shown in Figure 1；It is existing following several in order to reduce the offset voltage of SA
Technology：
(1) one kind that be M.Khayatzadeh and F.Frustaci as shown in Figure 2 proposed in 2015
Reconfigurable Sense Amplifier type circuits, the design scheme are to split into conventional voltage type sense amplifier
Two sense amplifier groups in parallel, while keeping chip area consistent with conventional voltage type SA.Compared to conventional voltage type SA,
There are four types of different combinations for the structure, and the structure has better anti-offset voltage ability under conditions of selecting optimal combination,
But the logic judgment of the optimal combination of the circuit is complex.
(2) it is illustrated in figure 3 the Robust Latch-Type types SA electricity that T.Song and S.M.Lee were designed in 2010
Road should improve the accuracy of the reading data of SA, but the circuit is set designed for the influence of reduction leakage current and offset voltage
Meter minimizing effect in terms of offset voltage is little, while extending the working time of SA, reduces the speed of SA.
Utility model content
The purpose of this utility model is to provide a kind of offset voltage adaptive digital calibration type sense amplifier, it is a kind of
Sense amplifier offset voltage can be effectively reduced, and then accelerates Static RAM reading speed and reduces unit reading work(
The circuit structure of consumption.
The purpose of this utility model is achieved through the following technical solutions：
A kind of offset voltage adaptive digital calibration type sense amplifier, including：The sense amplifier main body of interconnection
Partly, latch cicuit and reference voltage generating circuit are calibrated；
Wherein, the calibration latch cicuit includes：Ten PMOS transistors, four NMOS transistors, one or and
Eight phase inverters；Ten PMOS transistors are denoted as P9~P18 successively, and four NMOS transistors are denoted as N6~N9 successively, and eight anti-
Phase device is denoted as I1~I8 successively or door is denoted as OR；Wherein：
PMOS transistor P9 source electrodes are connect with VDD；PMOS transistor P10 grids are connect with output node OUT；PMOS crystal
Pipe P10 source electrodes are connected with PMOS transistor P9 drain electrodes；
PMOS transistor P11 grids are connect with calibration signal CK；PMOS transistor P11 source electrodes are leaked with PMOS transistor P10
Pole connects；PMOS transistor P11 drain electrodes are connected with phase inverter I1 outputs, and phase inverter I1 outputs are denoted as node A；Phase inverter I1 outputs
It is connected with phase inverter I2 inputs；Phase inverter I2 outputs are connected with phase inverter I1 inputs, and phase inverter I1 inputs are denoted as node AB；
NMOS transistor N6 grids are connect with reset signal RSET；NMOS transistor N6 drain electrodes are leaked with PMOS transistor P11
Pole connects；NMOS transistor N6 source electrodes are connect with GND；
PMOS transistor P12 source electrodes are connect with VDD；PMOS transistor P13 grids are connect with output node OUTB；PMOS is brilliant
Body pipe P13 source electrodes are connected with PMOS transistor P12 drain electrodes；
PMOS transistor P14 grids are connect with calibration signal CK；PMOS transistor P14 source electrodes are leaked with PMOS transistor P13
Pole connects；PMOS transistor P14 drain electrodes are connected with phase inverter I3 inputs, and phase inverter I3 inputs are denoted as node B；Phase inverter I3 outputs
It is connected with phase inverter I4 inputs, phase inverter I4 inputs are denoted as node BB；Phase inverter I4 outputs are connected with phase inverter I3 inputs；
NMOS transistor N7 grids are connect with reset signal RSET；NMOS transistor N7 drain electrodes are leaked with PMOS transistor P14
Pole connects；NMOS transistor N7 source electrodes are connect with GND；
PMOS transistor P15 source electrodes are connect with VDD；PMOS transistor P15 grids are connect with node AB；PMOS transistor
P15 drain electrodes are connect with PMOS transistor P16 source electrodes；PMOS transistor P16 grids and/or door OR output connections；PMOS transistor
P16 drains to be connected with phase inverter I5 outputs, and phase inverter I5 outputs are denoted as node C；Phase inverter I5 outputs connect with phase inverter I6 inputs
It connects；Phase inverter I6 outputs are denoted as node CB with phase inverter I5 input connection phase inverter I5 inputs；Node C and/or door OR inputs connect
It connects；
NMOS transistor N8 grids are connect with reset signal RSET；NMOS transistor N8 drain electrodes are leaked with PMOS transistor P16
Pole connects；NMOS transistor N8 source electrodes are connect with GND；
PMOS transistor P17 source electrodes are connect with VDD；PMOS transistor P17 grids are connect with node BB；PMOS transistor
P17 drain electrodes are connect with PMOS transistor P18 source electrodes；PMOS transistor P18 grids and/or door OR output connections；PMOS transistor
P18 drains to be connected with phase inverter I7 inputs, and phase inverter I7 inputs are denoted as node D；Phase inverter I7 inputs connect with phase inverter I8 outputs
It connects；Phase inverter I7 outputs are connected with phase inverter I8 inputs, and phase inverter I8 inputs are denoted as DB；Node D and/or door OR input connections；
NMOS transistor N9 grids are connect with reset signal RSET；NMOS transistor N9 drain electrodes are connected with PMOS transistor P18 drain electrodes；
NMOS transistor N9 source electrodes are connect with GND.
The utility model is real using simple peripheral circuit it can be seen from above-mentioned technical solution provided by the utility model
Existing SA offset voltage calibrations compensation and align mode latch operation, can effectively reduce the offset voltage of SA, improve
The read operation speed and power consumption of SRAM.
Description of the drawings
It is required in being described below to embodiment in order to illustrate more clearly of the technical solution of the utility model embodiment
The attached drawing used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the utility model
Example, for those of ordinary skill in the art for, without creative efforts, can also be according to these attached drawings
Obtain other accompanying drawings.
Fig. 1 is the structural schematic diagram for the conventional voltage type SA circuits that background technology provides；
Fig. 2 is the structural schematic diagram for the Reconfigurable SA circuits that background technology provides；
Fig. 3 is the structural schematic diagram for the Robust Latch-Type SA circuits that background technology provides；
The structure for the offset voltage adaptive digital calibration type sense amplifier that Fig. 4 is provided by the utility model embodiment
Schematic diagram；
Before the offset voltage adaptive digital calibration type sense amplifier calibration that Fig. 5 is provided by the utility model embodiment
Waveform analogous diagram afterwards；
The offset voltage adaptive digital calibration type sense amplifier transmission gate that Fig. 6 is provided by the utility model embodiment
NMOS grid voltages emulate relational graph with offset voltage offset；
Fig. 7 calibrates skill by the offset voltage adaptive digital calibration type sense amplifier that the utility model embodiment provides
Art flow chart；
The calibration for the offset voltage adaptive digital calibration type sense amplifier that Fig. 8 is provided by the utility model embodiment
Latch module simulation status figure；
Fig. 9 is the conventional voltage type SA circuits that background technology provides, Robust Latch-Type SA circuits and this practicality
The offset voltage adaptive digital calibration type sense amplifier that new embodiment is provided carries out under cadence simulation softwares
(simulated conditions are the offset voltage statistical chart of 2500 Monte Carlo simulations：VDD：1.2V；Corner：FF、FS、SF、SS；
Temperature：-40℃；25℃；25℃；125℃)；
Figure 10 is the conventional voltage type SA circuits that background technology provides, Robust Latch-Type SA circuits and this practicality
Offset voltage adaptive digital calibration type sense amplifier offset voltage column distribution map (the emulation item that new embodiment is provided
Part is：VDD：1.2V；Corner：TT；Temperature：25℃).
Specific implementation mode
With reference to the attached drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out clear
Chu is fully described by, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole realities
Apply example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
The every other embodiment obtained, belongs to the scope of protection of the utility model.
The utility model embodiment provides a kind of offset voltage adaptive digital calibration type sense amplifier, as shown in figure 4,
It includes mainly：Sense amplifier main part, calibration latch cicuit and the reference voltage generating circuit of interconnection；
Wherein, the sense amplifier main part realizes the amplification of signal, as shown in Fig. 4 (a) comprising：Five
NMOS transistor and eight PMOS transistors, five NMOS transistors are denoted as N1~N5 successively, and eight PMOS transistors are remembered successively
For P1~P8；Wherein NMOS transistor N1 and PMOS transistor P5 constitute a phase inverter, NMOS transistor N2 and PMOS crystal
Pipe P6 constitutes another phase inverter, the two phase inverters form cross coupling structure；By two NMOS between cross coupling structure
The transmission gate partition formed with two PMOS transistors；Meanwhile it also being incited somebody to action by the way that PMOS transistor P1, PMOS transistor P2 are corresponding
Sense amplifier is isolated with BL, BLB, is kept apart sense amplifier and VDD by PMOS transistor P3 and PMOS transistor P4,
Sense amplifier and GND are kept apart by NMOS transistor N3；Wherein：
Bit line BL is connect with the drain electrode of PMOS transistor P1；Bit line BLB is connect with the drain electrode of PMOS transistor P2；Enabled letter
Number SAE is connect with the grid of the grid of PMOS transistor P1 and PMOS transistor P2；The source electrode and PMOS of PMOS transistor P1
The drain electrode of transistor P5 and the drain electrode connection of NMOS transistor N1；The leakage of the source electrode and PMOS transistor P6 of PMOS transistor P2
The drain electrode of pole and NMOS transistor N2 connect；
Preliminary filling signal PRE is connect with the grid of the grid of PMOS transistor P3 and PMOS transistor P4；PMOS transistor
The drain electrode of P3 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1；The drain electrode of PMOS transistor P4 with
The drain electrode of PMOS transistor P6 and the drain electrode connection of NMOS transistor N2；The drain electrode of NMOS transistor N3 and NMOS transistor N1
Source electrode and NMOS transistor N2 source electrode connection；Enable signal SAE is connect with the grid of transistor N3；
The drain electrode of NMOS transistor N5 and the grid of PMOS transistor P6 and the grid of NMOS transistor N2 in transmission gate
Connection；The grid of the grid and NMOS transistor N2 of the drain electrode of PMOS transistor P7 and PMOS transistor P6 connects in transmission gate
It connects；The source electrode of NMOS transistor N5 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1 in transmission gate；
The source electrode of PMOS transistor P7 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1 in transmission gate；Transmission
The drain electrode of NMOS transistor N4 is connect with the grid of the grid of PMOS transistor P5 and NMOS transistor N1 in door；In transmission gate
The drain electrode of PMOS transistor P8 is connected with the grid of the grid of PMOS transistor P5 and NMOS transistor N1；NMOS in transmission gate
The source electrode of transistor N4 is connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2；PMOS crystal in transmission gate
The source electrode of pipe P8 is connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2；
VDD is connect with the source electrode of PMOS transistor P3, P4, P5 and P6；The source electrode and PMOS of GND and NMOS transistor N3
The grid of transistor P7 and P8 connect.
In the utility model embodiment, the drain electrode of NMOS transistor N5 is connect with node Q, the source electrode of NMOS transistor N5 with
Output node OUT connections, the grid of NMOS transistor N5 are connect with its control voltage signal VF；The drain electrode of NMOS transistor N4 with
Node QB connections, the source electrode of NMOS transistor N4 are connect with output node OUTB, and the grid of NMOS transistor N4 controls electricity with it
Press signal VS connections, the potential change of such output node VF and VS can be used to control, help that sensitive put is greatly reduced
The offset voltage of big device.
As shown in Fig. 4 (b), the calibration latch cicuit includes：Ten PMOS transistors, four NMOS transistors, one
Or door and eight phase inverters；Ten PMOS transistors are denoted as P9~P18 successively, four NMOS transistors be denoted as successively N6~
N9, eight phase inverters are denoted as I1~I8 successively or door is denoted as OR；Wherein：
PMOS transistor P9 source electrodes are connect with VDD；PMOS transistor P10 grids are connect with output node OUT；PMOS crystal
Pipe P10 source electrodes are connected with PMOS transistor P9 drain electrodes；
PMOS transistor P11 grids are connect with calibration signal CK；PMOS transistor P11 source electrodes are leaked with PMOS transistor P10
Pole connects；PMOS transistor P11 drain electrodes are connected with phase inverter I1 outputs, and phase inverter I1 outputs are denoted as node A；Phase inverter I1 outputs
It is connected with phase inverter I2 inputs；Phase inverter I2 outputs are connected with phase inverter I1 inputs, and phase inverter I1 inputs are denoted as node AB；
NMOS transistor N6 grids are connect with reset signal RSET；NMOS transistor N6 drain electrodes are leaked with PMOS transistor P11
Pole connects；NMOS transistor N6 source electrodes are connect with GND；
PMOS transistor P12 source electrodes are connect with VDD；PMOS transistor P13 grids are connect with output node OUTB；PMOS is brilliant
Body pipe P13 source electrodes are connected with PMOS transistor P12 drain electrodes；
PMOS transistor P14 grids are connect with calibration signal CK；PMOS transistor P14 source electrodes are leaked with PMOS transistor P13
Pole connects；PMOS transistor P14 drain electrodes are connected with phase inverter I3 inputs, and phase inverter I3 inputs are denoted as node B；Phase inverter I3 outputs
It is connected with phase inverter I4 inputs, phase inverter I4 inputs are denoted as node BB；Phase inverter I4 outputs are connected with phase inverter I3 inputs；
NMOS transistor N7 grids are connect with reset signal RSET；NMOS transistor N7 drain electrodes are leaked with PMOS transistor P14
Pole connects；NMOS transistor N7 source electrodes are connect with GND；
PMOS transistor P15 source electrodes are connect with VDD；PMOS transistor P15 grids are connect with node AB；PMOS transistor
P15 drain electrodes are connect with PMOS transistor P16 source electrodes；PMOS transistor P16 grids and/or door OR output connections；PMOS transistor
P16 drains to be connected with phase inverter I5 outputs, and phase inverter I5 outputs are denoted as node C；Phase inverter I5 outputs connect with phase inverter I6 inputs
It connects；Phase inverter I6 outputs are denoted as node CB with phase inverter I5 input connection phase inverter I5 inputs；Node C and/or door OR inputs connect
It connects；
NMOS transistor N8 grids are connect with reset signal RSET；NMOS transistor N8 drain electrodes are leaked with PMOS transistor P16
Pole connects；NMOS transistor N8 source electrodes are connect with GND；
PMOS transistor P17 source electrodes are connect with VDD；PMOS transistor P17 grids are connect with node BB；PMOS transistor
P17 drain electrodes are connect with PMOS transistor P18 source electrodes；PMOS transistor P18 grids and/or door OR output connections；PMOS transistor
P18 drains to be connected with phase inverter I7 inputs, and phase inverter I7 inputs are denoted as node D；Phase inverter I7 inputs connect with phase inverter I8 outputs
It connects；Phase inverter I7 outputs are connected with phase inverter I8 inputs, and phase inverter I8 inputs are denoted as DB；Node D and/or door OR input connections；
NMOS transistor N9 grids are connect with reset signal RSET；NMOS transistor N9 drain electrodes are connected with PMOS transistor P18 drain electrodes；
NMOS transistor N9 source electrodes are connect with GND.
As shown in Fig. 4 (c), the reference voltage generating circuit includes：One NMOS transistor, six PMOS transistors,
Three resistance and a NAND gate；One NMOS transistor is denoted as N10, and six PMOS transistors are denoted as P19~P24 successively, and three
A resistance is denoted as R1~R3, and a NAND gate is denoted as NAND；Wherein：
The source electrode of PMOS transistor P19 and P20 are connect with VDD；PMOS transistor P19 grids are connect with node C；
MOS transistor P20 grids are connect with node D；PMOS transistor P22 grids are connect with node CB；PMOS transistor
P24 grids are connect with node DB；PMOS transistor P19 drain electrodes connect with PMOS transistor P22 source electrodes and control voltage signal VF
It connects；PMOS transistor P20 drain electrodes are connect with PMOS transistor P24 source electrodes and control voltage signal VS；PMOS transistor P22 leakages
Pole and PMOS transistor P24 drain electrodes are connect with PMOS transistor P21 source electrodes and PMOS transistor P23 source electrodes；
Node A and node B is connected with NAND gate NAND inputs；NAND gate NAND output and PMOS transistor P21 grids and
Phase inverter I9 input connections；Phase inverter I9 outputs are connect with PMOS transistor P23 grids；The upper ends resistance R3 are connect with VDD；Resistance
The lower ends R3 are connect with PMOS transistor P21 drain electrodes and the upper ends resistance R2；The lower ends resistance R2 and PMOS transistor P23 drain electrodes and resistance
The upper ends R1 connect；The lower ends resistance R1 are connected with NMOS transistor N10 drain electrodes, and NMOS transistor N10 source electrodes are connect with GND；NMOS
Transistor N10 grids are connect with signal SAE.
Specifically, the offset voltage adaptive digital calibration type sensitive amplifier circuit that the utility model embodiment is provided
In, compared with traditional SA, design increases a transmission gate between OUT and Q (OUTB and QB).The NMOS gate of transmission gate
Voltage is VF (VS), and PMOS grid voltages are always grounded.The purpose of the design is the velocity of discharge by control node
Reduce the offset voltage generated by threshold voltage difference.Compared with Robust Latch-Type SA structures (structure shown in Fig. 3),
The utility model replaces BL/BLB, therefore the offset voltage adaptive digital school that the utility model embodiment is provided with VF/VS
Pseudotype sense amplifier can use the effect that digital calibration techniques realize that offset voltage significantly reduces.Robust Latch-
Type SA structures use signal SAE rather than the grid of the PMOS in GND connection transmission gates, cause to transmit in mistuning calibration function
The PMOS of door is off state.Due to there is threshold value loss when NMOS transmits high level, work the time in SA
Point Q/QB cannot be charged to VDD.
The adaptive digital school of offset voltage adaptive digital calibration type sense amplifier is utilized in the utility model simultaneously
Quasi- technology only needs be no longer needed for any operation two periods of calibration before SA is worked normally.The collimation technique of the utility model
Go out best offset compensation amount by theoretical analysis and calculation, and digital calibration technology may be implemented to calibrate twice, effect is more
Obviously.Latch technique can preserve calibration process, reach the nonexpondable effect of primary calibration.
The offset voltage adaptive digital calibration type sense amplifier that the utility model is implemented to provide is in charging stage, PRE
Signal is low level, and SAE signal is also low level, and PMOS transistor P3 and P4 are connected, memory node OUT, OUTB and node Q,
QB is charged to high level in advance；When charging stage, which terminates SA, enters working stage, PRE signals are high level, and SAE signal is height
Level, PMOS transistor P3 and P4 cut-off, circuit stop preliminary filling, transistor P1 and P2 cut-off, memory node OUT/OUTB and BL/
BLB separates.Due to BL and BLB unit pipes discharge path difference there is voltage difference, this species diversity equally can in OUT and
It is embodied on OUTB, the cross coupling structure of SA can amplify this voltage difference.It is worth mentioning that if this voltage difference is small
It just will appear mistake in SA offset voltages and read situation, therefore conventional way can be when BL and BLB voltage differences be larger
SAE signal just becomes high level.The SA that the utility model embodiment provides can judge offset voltage just by peripheral circuit
Negativity and approximate range, the size for changing VF VS voltages carry out the current strength on controlling transmission door by NMOS, finally
Effect is reduced because NMOS transistor N1 and N2 threshold value mismatches caused voltage difference, to reduce offset voltage.It compares
Extend the method that bitline discharge time ensures accuracy compared with conventional voltage type SA, the SA that the utility model embodiment provides can
To reduce bitline discharge time, improved in terms of power consumption and speed.
In order to more clearly from show technical solution provided by the utility model and generated technique effect, below
In conjunction with Fig. 5 to Fig. 8, the theory for the adaptive calibration latch sensitive amplifier circuit that the utility model embodiment is provided will be introduced
Analysis and simulating, verifying process；In conjunction with Fig. 9, Figure 10, the adaptive calibration that the utility model embodiment is provided latches sensitive
The performance of amplifier circuit, with background technology provide conventional voltage type SA circuits and Robust Latch-Type SA circuits into
Row comparison；Its particular content is as follows：
(1) as shown in figure 5, the offset voltage adaptive digital calibration type provided by the utility model embodiment is sensitive puts
The big front and back wave simulation figure of device calibration.As a result, VF connections at this time refer to after the correspondence calibration of solid line therein, i.e. " (A) " class curve
Voltage, VS connections VDD；It is preceding as a result, VF and VS connect VDD at this time that dotted line therein, i.e. " (B) " class curve correspond to calibration.It is imitative
The voltage difference of OUT and OUTB, Q and QB all significantly reduce after true result display calibration, offset voltage point before and after alignment
It is not 30mV and 10mV.Therefore can achieve the effect that reduce offset voltage by the grid voltage of controlling transmission door NMOS.
(2) as shown in fig. 6, the offset voltage adaptive digital calibration type provided by the utility model embodiment is sensitive puts
Transmission gate NMOS grid voltages emulate relational graph with offset voltage offset in big device.The controlling transmission door NMOS grid obtained according to Fig. 5
Pressure can reduce the conclusion of offset voltage, and Fig. 6 demonstrates the relationship (VF between transmission gate NMOS grid voltages and offset voltage offset
Potential change, VS is remained to be connect with VDD), it can be found that simulation result is almost straight line, therefore we obtain NMOS
Grid voltage and the conclusion that offset voltage offset is linear relationship.
(3) as shown in fig. 7, the offset voltage adaptive digital calibration type provided by the utility model embodiment is sensitive puts
Big device calibrates flow chart；The corresponding calibration latch cicuits of the utility model SA in conjunction with shown in Fig. 4 (b) and sheet shown in Fig. 4 (c)
The corresponding reference voltage generating circuits of utility model SA carry out pre- charge and discharge to circuit first, then judge output node current potential
Height, if OUT be " 0 " if node A, C current potential increase, VF access reference voltage 1；Node B, D electricity if OUT is " 1 "
Position increases, and VS accesses reference voltage 1.Preliminary filling and item without bit-line voltage difference are carried out to circuit again after into second calibration cycle
It discharges under part, calibrates and terminate if the data of output node output were consistent with a upper period；If output data is not protected
It holds consistent then reference voltage 1 and is substituted for reference voltage 2 and connect with VF or VS, calibration terminates.
(4) as shown in figure 8, the offset voltage adaptive digital calibration type provided by the utility model embodiment is sensitive puts
Big device calibrates latch module simulation status figure.Fig. 8 illustrates two different situations present in calibration cycle, Fig. 8 therein
(a) it is " 0 " in a cycle OUT output results, node A, C increase VF and access reference voltage 1；Second period is joined in access
After examining voltage 1, there is overcompensation phenomenon in offset voltage calibration compensation, and OUT outputs result became from " 0 " in a upper period
" 1 ", therefore node B current potentials increase the VF access calibrations of reference voltage 2 and terminate.Fig. 8 (b) therein exports in a cycle OUT
As a result it is " 0 " that node A, C increase VF and access reference voltage 1；Second period is after accessing reference voltage 1, offset voltage calibration
Compensation does not occur overcompensation phenomenon, and OUT outputs result was consistent with a upper period, and node B, D current potential does not change, and VF continues
The connection with reference voltage 1, calibration is kept to terminate.
(5) as shown in figure 9, for the conventional voltage type SA circuits that background technology provides, Robust Latch-Type SA electricity
The offset voltage adaptive digital calibration type sense amplifier that road and the utility model embodiment are provided emulates soft in cadence
The offset voltage statistical chart of 2500 Monte Carlo simulations is carried out under part；Three columns in each group are corresponding in turn to conventional voltage
Type SA, Robust Latch-Type SA provide the simulation result of SA with the utility model embodiment.Pass through the data statistics of Fig. 9
It makes moderate progress as can be seen that Robust Latch-Type SA are compared to conventional voltage type SA, but improvement is little.This
The offset voltage adaptive digital calibration type sense amplifier that utility model embodiment is provided compare conventional voltage type SA and
Robust Latch-Type SA are suffered from terms of offset voltage significantly to be reduced, even if promoting the worst SF works of effect
Under skill angle, it is compared to the effect that conventional voltage type SA still keeps reducing by 49.9%, compares Robust Latch-Type SA drops
Low 35.8%.
(6) as shown in Figure 10, the conventional voltage type SA circuits provided for background technology, Robust Latch-Type SA electricity
The offset voltage adaptive digital calibration type sense amplifier offset voltage column that road and the utility model embodiment are provided point
Butut.Wherein simulated conditions are：(VDD：1.2V；Corner：TT；Temperature：25℃).Wherein Figure 10 (a) is tradition electricity
Die mould SA offset voltages emulate data histograms, and mean μ 74.61uV, standard deviation sigma 15.15mV, Figure 10 (b) are Robust
Latch-Type SA offset voltages emulate data histograms, it can be seen that the conventional voltage that compares type SA block diagrams are distributed more
Intensive, standard deviation sigma drops to 11.90mV, and Figure 10 (c) is the offset voltage adaptive digital that the utility model embodiment is provided
Calibration type sense amplifier offset voltage emulates data histograms, and block diagram dense degree is significantly promoted, and standard deviation sigma is even more to drop
As low as 6.499mV.The offset voltage adaptive digital calibration type sense amplifier that the utility model embodiment is provided compares
57% is reduced in conventional voltage type SA offset voltages, being compared to Robust Latch-Type SA offset voltages reduces
45.4%.
In conclusion a kind of offset voltage adaptive digital calibration type sense amplifier provided by the utility model, it can
The offset voltage of sense amplifier SA is effectively reduced, which realizes that sense amplifier is lacked of proper care using simple peripheral circuit
The compensation for calibrating errors and compensating coefficient latch operation of voltage, have achieved the purpose that offset voltage is greatly lowered；Simultaneously because losing
The reduction for adjusting voltage, effectively improves the design margin of Static RAM reading circuit, thereby reduces unit reading
When the power consumption consumption that generates, and improve the data reading speed of Static RAM.
The preferable specific implementation mode of the above, only the utility model, but the scope of protection of the utility model is not
It is confined to this, any one skilled in the art can readily occur in the technical scope that the utility model discloses
Change or replacement, should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model should
Subject to the scope of protection of the claims.
Claims (3)
1. a kind of offset voltage adaptive digital calibration type sense amplifier, which is characterized in that including：The sensitive of interconnection is put
Big device main part, calibration latch cicuit and reference voltage generating circuit；
Wherein, the calibration latch cicuit includes：Ten PMOS transistors, four NMOS transistors, one or and eight
Phase inverter；Ten PMOS transistors are denoted as P9~P18 successively, and four NMOS transistors are denoted as N6~N9, eight phase inverters successively
It is denoted as I1~I8 successively or door is denoted as OR；Wherein：
PMOS transistor P9 source electrodes are connect with VDD；PMOS transistor P10 grids are connect with output node OUT；PMOS transistor
P10 source electrodes are connected with PMOS transistor P9 drain electrodes；
PMOS transistor P11 grids are connect with calibration signal CK；PMOS transistor P11 source electrodes connect with PMOS transistor P10 drain electrodes
It connects；PMOS transistor P11 drain electrodes are connected with phase inverter I1 outputs, and phase inverter I1 outputs are denoted as node A；Phase inverter I1 output with it is anti-
The I2 input connections of phase device；Phase inverter I2 outputs are connected with phase inverter I1 inputs, and phase inverter I1 inputs are denoted as node AB；
NMOS transistor N6 grids are connect with reset signal RSET；NMOS transistor N6 drain electrodes connect with PMOS transistor P11 drain electrodes
It connects；NMOS transistor N6 source electrodes are connect with GND；
PMOS transistor P12 source electrodes are connect with VDD；PMOS transistor P13 grids are connect with output node OUTB；PMOS transistor
P13 source electrodes are connected with PMOS transistor P12 drain electrodes；
PMOS transistor P14 grids are connect with calibration signal CK；PMOS transistor P14 source electrodes connect with PMOS transistor P13 drain electrodes
It connects；PMOS transistor P14 drain electrodes are connected with phase inverter I3 inputs, and phase inverter I3 inputs are denoted as node B；Phase inverter I3 output with it is anti-
The I4 input connections of phase device, phase inverter I4 inputs are denoted as node BB；Phase inverter I4 outputs are connected with phase inverter I3 inputs；
NMOS transistor N7 grids are connect with reset signal RSET；NMOS transistor N7 drain electrodes connect with PMOS transistor P14 drain electrodes
It connects；NMOS transistor N7 source electrodes are connect with GND；
PMOS transistor P15 source electrodes are connect with VDD；PMOS transistor P15 grids are connect with node AB；PMOS transistor P15 leakages
Pole is connect with PMOS transistor P16 source electrodes；PMOS transistor P16 grids and/or door OR output connections；PMOS transistor P16 drain electrodes
It is connected with phase inverter I5 outputs, phase inverter I5 outputs are denoted as node C；Phase inverter I5 outputs are connected with phase inverter I6 inputs；Reverse phase
Device I6 outputs are denoted as node CB with phase inverter I5 input connection phase inverter I5 inputs；Node C and/or door OR input connections；
NMOS transistor N8 grids are connect with reset signal RSET；NMOS transistor N8 drain electrodes connect with PMOS transistor P16 drain electrodes
It connects；NMOS transistor N8 source electrodes are connect with GND；
PMOS transistor P17 source electrodes are connect with VDD；PMOS transistor P17 grids are connect with node BB；PMOS transistor P17 leakages
Pole is connect with PMOS transistor P18 source electrodes；PMOS transistor P18 grids and/or door OR output connections；PMOS transistor P18 drain electrodes
It is connected with phase inverter I7 inputs, phase inverter I7 inputs are denoted as node D；Phase inverter I7 inputs are connected with phase inverter I8 outputs；Reverse phase
Device I7 outputs are connected with phase inverter I8 inputs, and phase inverter I8 inputs are denoted as DB；Node D and/or door OR input connections；NMOS crystal
Pipe N9 grids are connect with reset signal RSET；NMOS transistor N9 drain electrodes are connected with PMOS transistor P18 drain electrodes；NMOS transistor
N9 source electrodes are connect with GND.
2. a kind of offset voltage adaptive digital calibration type sense amplifier according to claim 1, which is characterized in that institute
Stating sense amplifier main part includes：Five NMOS transistors and eight PMOS transistors, five NMOS transistors are remembered successively
For N1~N5, eight PMOS transistors are denoted as P1~P8 successively；Wherein NMOS transistor N1 and PMOS transistor P5 constitute one
Phase inverter, NMOS transistor N2 and PMOS transistor P6 constitute another phase inverter, the two phase inverters form cross-couplings knot
Structure；Separated by the transmission gate that two NMOS and two PMOS transistors are formed between cross coupling structure；Meanwhile also passing through PMOS
Transistor P1, PMOS transistor P2 are corresponding, and sense amplifier is isolated with BL, BLB, brilliant by PMOS transistor P3 and PMOS
Body pipe P4 keeps apart sense amplifier and VDD, is kept apart sense amplifier and GND by NMOS transistor N3；Wherein：
Bit line BL is connect with the drain electrode of PMOS transistor P1；Bit line BLB is connect with the drain electrode of PMOS transistor P2；Enable signal
SAE is connect with the grid of the grid of PMOS transistor P1 and PMOS transistor P2；The source electrode of PMOS transistor P1 is brilliant with PMOS
The drain electrode of body pipe P5 and the drain electrode connection of NMOS transistor N1；The drain electrode of the source electrode and PMOS transistor P6 of PMOS transistor P2
And the drain electrode connection of NMOS transistor N2；
Preliminary filling signal PRE is connect with the grid of the grid of PMOS transistor P3 and PMOS transistor P4；PMOS transistor P3's
Drain electrode is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1；The drain electrode of PMOS transistor P4 is brilliant with PMOS
The drain electrode of body pipe P6 and the drain electrode connection of NMOS transistor N2；The source electrode of the drain electrode and NMOS transistor N1 of NMOS transistor N3
And the source electrode connection of NMOS transistor N2；Enable signal SAE is connect with the grid of transistor N3；
The drain electrode of NMOS transistor N5 is connect with the grid of the grid of PMOS transistor P6 and NMOS transistor N2 in transmission gate；
The drain electrode of PMOS transistor P7 is connected with the grid of the grid of PMOS transistor P6 and NMOS transistor N2 in transmission gate；Transmission
The source electrode of NMOS transistor N5 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1 in door；In transmission gate
The source electrode of PMOS transistor P7 is connect with the drain electrode of PMOS transistor P5 and the drain electrode of NMOS transistor N1；NMOS in transmission gate
The drain electrode of transistor N4 is connect with the grid of the grid of PMOS transistor P5 and NMOS transistor N1；PMOS crystal in transmission gate
The drain electrode of pipe P8 is connected with the grid of the grid of PMOS transistor P5 and NMOS transistor N1；NMOS transistor N4 in transmission gate
Source electrode connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2；The source of PMOS transistor P8 in transmission gate
Pole is connect with the drain electrode of PMOS transistor P6 and the drain electrode of NMOS transistor N2；
VDD is connect with the source electrode of PMOS transistor P3, P4, P5 and P6；The source electrode and PMOS crystal of GND and NMOS transistor N3
The grid of pipe P7 and P8 connect；
The drain electrode of the NMOS transistor N5 is connect with node Q, and the source electrode of NMOS transistor N5 is connect with output node OUT,
The grid of NMOS transistor N5 is connect with its control voltage signal VF；The drain electrode of NMOS transistor N4 is connect with node QB, NMOS
The source electrode of transistor N4 is connect with output node OUTB, and the grid of NMOS transistor N4 is connect with its control voltage signal VS.
3. a kind of offset voltage adaptive digital calibration type sense amplifier according to claim 2, which is characterized in that institute
Stating reference voltage generating circuit includes：One NMOS transistor, three resistance and a NAND gate and six PMOS transistors；One
A NMOS transistor is denoted as N10, and six PMOS transistors are denoted as P19~P24 successively, and three resistance are denoted as R1~3, one with it is non-
Door is denoted as NAND；Wherein：
The source electrode of PMOS transistor P19 and P20 are connect with VDD；PMOS transistor P19 grids are connect with node C；
MOS transistor P20 grids are connect with node D；PMOS transistor P22 grids are connect with node CB；PMOS transistor P24 grid
Pole is connect with node DB；PMOS transistor P19 drain electrodes are connect with PMOS transistor P22 source electrodes and control voltage signal VF；
PMOS transistor P20 drain electrodes are connect with PMOS transistor P24 source electrodes and control voltage signal VS；PMOS transistor P22 drain electrodes
It is connect with PMOS transistor P24 drain electrodes with PMOS transistor P21 source electrodes and PMOS transistor P23 source electrodes；
Node A and node B is connected with NAND gate NAND inputs；NAND gate NAND outputs and PMOS transistor P21 grids and reverse phase
Device I9 input connections；Phase inverter I9 outputs are connect with PMOS transistor P23 grids；The upper ends resistance R3 are connect with VDD；Under resistance R3
End is connect with PMOS transistor P21 drain electrodes and the upper ends resistance R2；On the lower ends resistance R2 and PMOS transistor P23 drain electrodes and resistance R1
End connection；The lower ends resistance R1 are connected with NMOS transistor N10 drain electrodes, and NMOS transistor N10 source electrodes are connect with GND；NMOS crystal
Pipe N10 grids are connect with signal SAE.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820411822.2U CN207833929U (en) | 2018-03-26 | 2018-03-26 | Offset voltage adaptive digital calibration type sense amplifier |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820411822.2U CN207833929U (en) | 2018-03-26 | 2018-03-26 | Offset voltage adaptive digital calibration type sense amplifier |
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| CN207833929U true CN207833929U (en) | 2018-09-07 |
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| CN201820411822.2U Withdrawn - After Issue CN207833929U (en) | 2018-03-26 | 2018-03-26 | Offset voltage adaptive digital calibration type sense amplifier |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231100A (en) * | 2018-03-26 | 2018-06-29 | 安徽大学 | Offset voltage adaptive digital calibration type sense amplifier |
| CN111986719A (en) * | 2020-09-10 | 2020-11-24 | 苏州兆芯半导体科技有限公司 | Current determination method |
| CN112767975A (en) * | 2021-02-10 | 2021-05-07 | 长鑫存储技术有限公司 | Sense amplifier and control method thereof |
| CN113470705A (en) * | 2020-03-30 | 2021-10-01 | 长鑫存储技术有限公司 | Sense amplifier, memory and data reading method |
-
2018
- 2018-03-26 CN CN201820411822.2U patent/CN207833929U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231100A (en) * | 2018-03-26 | 2018-06-29 | 安徽大学 | Offset voltage adaptive digital calibration type sense amplifier |
| CN108231100B (en) * | 2018-03-26 | 2023-09-19 | 安徽大学 | Offset voltage self-adaptive digital calibration type sense amplifier |
| CN113470705A (en) * | 2020-03-30 | 2021-10-01 | 长鑫存储技术有限公司 | Sense amplifier, memory and data reading method |
| CN113470705B (en) * | 2020-03-30 | 2024-05-14 | 长鑫存储技术有限公司 | Sense amplifier, memory and data reading method |
| CN111986719A (en) * | 2020-09-10 | 2020-11-24 | 苏州兆芯半导体科技有限公司 | Current determination method |
| CN111986719B (en) * | 2020-09-10 | 2022-11-29 | 苏州兆芯半导体科技有限公司 | Current determination method |
| CN112767975A (en) * | 2021-02-10 | 2021-05-07 | 长鑫存储技术有限公司 | Sense amplifier and control method thereof |
| CN112767975B (en) * | 2021-02-10 | 2022-04-12 | 长鑫存储技术有限公司 | Sense amplifier and control method thereof |
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