CN207766239U - A kind of MCU hardware reset circuits and BMS systems - Google Patents
A kind of MCU hardware reset circuits and BMS systems Download PDFInfo
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- CN207766239U CN207766239U CN201721888339.5U CN201721888339U CN207766239U CN 207766239 U CN207766239 U CN 207766239U CN 201721888339 U CN201721888339 U CN 201721888339U CN 207766239 U CN207766239 U CN 207766239U
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- mcu
- reset
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- 230000005611 electricity Effects 0.000 claims description 10
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Abstract
The utility model belongs to electronic circuit technology field, provides a kind of MCU hardware reset circuits and BMS systems, circuit include：First switch unit, the first switch unit access charging signals and export the first drive signal in its output end；Second switch unit, the second switch unit access first drive signal and export the second drive signal in its output end；Be delayed adjustment unit, and the delay adjustment unit adjusts second drive signal into line delay；And third switch unit, the third switch unit access the second drive signal after delay adjustment and in the reset pins of its output end output reset signal to the MCU, and the MCU is made to reset.Three switch units are subject to the reset signal of pulse according to the charging signals detected to the reset pin of MCU, to realize charging forced resetting；Wherein, delay adjustment unit can also be adjusted the burst length, to realize pulse reset.
Description
Technical field
The utility model belongs to electronic circuit technology field more particularly to a kind of MCU hardware reset circuits and BMS systems.
Background technology
Currently, traditional MCU (Micro Control Unit, micro-control unit) reset circuit includes：Using inside
Watchdog reset and using internal watchdog resets both modes, wherein defective；
Using the defect of internal watchdog resets：Under complicated or strongly disturbing operating mode, internal house dog is possible to failure,
It after single chip microcomputer halt, cannot reset, cause BMS (Battery Management System, battery management system)
System permanent paralysis；
The defect resetted using outer watchdog：Outer watchdog IC (Integrated Circuit, integrated circuit) work
Power consumption is needed, the low-power consumption requirement of BMS systems is unsatisfactory for, because BMS needs to enter suspend mode, therefore full-time cannot feed dog, therefore
When suspend mode, house dog does not work, from defect.
Therefore, exist in traditional MCU reset circuits and be easy failure, MCU reset issues cannot be made by be easy to causeing.
Utility model content
The purpose of this utility model is to provide a kind of MCU hardware reset circuits and BMS systems, it is intended to solve traditional
Exist in MCU reset circuits and be easy failure, MCU reset issues cannot be made by be easy to causeing.
A kind of MCU hardware reset circuits, including：
First switch unit, input termination charging port, the first switch unit access charging signals and in its outputs
The first drive signal of end output；
Second switch unit, input terminal are connect with the output end of the first switch unit, and the second switch unit connects
Enter first drive signal and exports the second drive signal in its output end；
Be delayed adjustment unit, is connect with the output end of the second switch unit, and the delay adjustment unit is to described the
Two driving signal is adjusted into line delay；And
Third switch unit, connect with the delay adjustment unit and the connection of the reset pin of MCU, the third switch are single
Member accesses the second drive signal after delay adjustment and in its output end output reset signal to the reset pin of the MCU, makes
The MCU resets.
Further, the first switch unit includes first resistor, second resistance, the first capacitance and the first triode,
Wherein：
First triode is NPN type triode, and the base stage of first triode connects one end of the first resistor,
The other end of the first resistor terminates the charging port as the input of the first switch unit, passes through second electricity
Resistance ground connection, first capacitance is in parallel with the second resistance, the emitter ground connection of first triode, the one or three pole
Output end of the collector of pipe as the first switch unit.
Further, the second switch unit includes 3rd resistor, the 4th resistance, the 5th resistance and the second triode,
Wherein：
Second triode is PNP type triode, and the base stage of second triode connects one end of the 3rd resistor,
Input terminal of the other end of the 3rd resistor as the second switch unit, the base stage of second triode also pass through institute
The emitter that the 4th resistance connects second triode is stated, the emitter of second triode meets institute by the 5th resistance
State the reset pin of MCU, the output end of the collector of second triode as the second switch unit.
Further, the delay adjustment unit includes the 6th resistance and the second capacitance, and the 6th resistance is connected to institute
It states between the output end of second switch unit and the input terminal of the third switch unit, second capacitance and the 6th electricity
Resistance is in parallel.
Further, the third switch unit includes the 7th resistance, the 8th resistance, third transistor and third capacitance,
Wherein：
The third transistor NPN type triode, the base stage of the third transistor meet one end of the 7th resistance, institute
Input terminal of the other end of the 7th resistance as the third switch unit is stated, the base stage of the third transistor is also by described
The collector of 8th resistance eutral grounding, the emitter ground connection of the third transistor, the third transistor passes through third electricity
Hold ground connection, and the collector of the third transistor draws as the reset of the output termination MCU of the third switch unit
Foot.
In addition, a kind of BMS systems are additionally provided, including MCU and above-mentioned MCU hardware reset circuits.
Above-mentioned MCU hardware reset circuits are filled by detecting external charging signal, three switch units according to what is detected
Electric signal is subject to the reset signal of pulse to the reset pin of MCU, to realize charging forced resetting；Wherein, delay adjustment is single
Member can also be adjusted the burst length, to realize pulse reset.
Description of the drawings
Fig. 1 is the MCU hardware reset circuit exemplary circuit schematic diagrams that the utility model preferred embodiment provides.
Specific implementation mode
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
Fig. 1 shows a kind of MCU hardware for the BMS systems that can be used for having MCU 150 of the utility model preferred embodiment
Reset circuit；Certainly, which can be used for other electronic equipments.
MCU hardware reset circuits include first switch unit 110, second switch unit 120,130 and of delay adjustment unit
Third switch unit 140.
The input of first switch unit 110 terminates charging port C+, and first switch unit 110 accesses charging signals and the
The output end of one switch unit 110 exports the first drive signal.
The input terminal of second switch unit 120 is connect with the output end of first switch unit 110, second switch unit 120
It accesses the first drive signal and exports the second drive signal in the output end of second switch unit 120；
Delay adjustment unit 130 is connect with the output end of second switch unit 120, and delay adjustment unit 130 drives to second
Dynamic signal is adjusted into line delay.
Third switch unit 140 connect with delay adjustment unit 130 and the reset pin of MCU connects, third switch unit
140 the second drive signals accessed after delay adjustment simultaneously draw in the reset of its output end output reset signal REST to MCU 200
Foot N_RST makes MCU 200 reset.
Specifically, first switch unit 110 includes first resistor R1, second resistance R2, the first capacitance C1 and the one or three pole
Pipe Q1.
First triode Q1 is NPN type triode, and the base stage of the first triode Q1 connects one end of first resistor R1, the first electricity
The other end for hindering R1 terminates charging port C+ as the input of first switch unit 110, is grounded by second resistance R2, the first electricity
Appearance C1 is in parallel with second resistance R2, and the emitter ground connection of the first triode Q1, the collector of the first triode Q1 is opened as first
Close the output end of unit 110.
Second switch unit 120 includes 3rd resistor R3, the 4th resistance R4, the 5th resistance R5 and the second triode Q2.
Second triode Q2 is PNP type triode, and the base stage of the second triode Q2 connects one end of 3rd resistor R3, third electricity
Input terminal of the other end of R3 as second switch unit 120 is hindered, the base stage of the second triode Q2 is also connect by the 4th resistance R4
The emitter of the emitter of second triode Q2, the second triode Q2 meets the reset pin N_ of MCU 200 by the 5th resistance R5
Output end of the collector of RST, the second triode Q2 as second switch unit 120.
The adjustment unit 130 that is delayed includes the 6th resistance R6 and the second capacitance C2, and the 6th resistance R6 is connected to second switch list
Between the output end and the input terminal of third switch unit 140 of member 120, the second capacitance C2 is in parallel with the 6th resistance R6.
Further, third switch unit 140 includes the 7th resistance R7, the 8th resistance R8, third transistor Q3 and third
Capacitance C3, wherein：
Third transistor Q3NPN type triodes, the base stage of third transistor Q3 connect one end of the 7th resistance R7, the 7th resistance
The base stage of input terminal of the other end of R7 as third switch unit 140, third transistor Q3 is also grounded by the 8th resistance R8,
The emitter of third transistor Q3 is grounded, and the collector of third transistor Q3 is grounded by third capacitance C3, and third transistor
Reset pin N_RST of the collector of Q3 as the output termination MCU 200 of third switch unit 140.
After crash state occurs for MCU 200 (such as microcontroller), inputted when detecting that charging port C+ has to charge, triode
Q1, Q2, Q3 are both turned on, and 200 ports reseting port N_RST MCU is made to become low level, to make MCU 200 reset；By right
The capacitance-resistance value of 6th resistance R6 and the second capacitance C2 are matched, and are adjusted to the burst length, to realize pulse reset.
Above-mentioned 200 hardware reset circuits of MCU are by detecting external charging signal, and three switch units are according to detecting
Charging signals be subject to the reset signal REST of pulse to the reset pin N_RST of MCU 200, to realize that it is multiple that charging is forced
Position；Wherein, delay adjustment unit 130 can also be adjusted the burst length, to realize pulse reset.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
All any modification, equivalent and improvement etc., should be included in the utility model made by within the spirit and principle of utility model
Protection domain within.
Claims (6)
1. a kind of MCU hardware reset circuits, which is characterized in that including：
First switch unit, input termination charging port, the first switch unit access charging signals are simultaneously defeated in its output end
Go out the first drive signal；
Second switch unit, input terminal are connect with the output end of the first switch unit, and the second switch unit accesses institute
It states the first drive signal and exports the second drive signal in its output end；
Be delayed adjustment unit, is connect with the output end of the second switch unit, and the delay adjustment unit drives to described second
Dynamic signal is adjusted into line delay；And
Third switch unit is connect with the reset pin of the delay adjustment unit and the MCU, and the third switch unit connects
Enter the second drive signal after delay adjustment and in the reset pin of its output end output reset signal to the MCU, makes described
MCU resets.
2. MCU hardware reset circuits as described in claim 1, which is characterized in that the first switch unit includes the first electricity
Resistance, second resistance, the first capacitance and the first triode, wherein：
First triode is NPN type triode, and the base stage of first triode connects one end of the first resistor, described
The other end of first resistor terminates the charging port, the base of first triode as the input of the first switch unit
Pole is also grounded by the second resistance, and first capacitance is in parallel with the second resistance, the transmitting of first triode
Pole is grounded, the output end of the collector of first triode as the first switch unit.
3. MCU hardware reset circuits as described in claim 1, which is characterized in that the second switch unit includes third electricity
Resistance, the 4th resistance, the 5th resistance and the second triode, wherein：
Second triode is PNP type triode, and the base stage of second triode connects one end of the 3rd resistor, described
The base stage of input terminal of the other end of 3rd resistor as the second switch unit, second triode also passes through described
Four resistance connect the emitter of second triode, and the emitter of second triode is connect described by the 5th resistance
The reset pin of MCU, the output end of the collector of second triode as the second switch unit.
4. MCU hardware reset circuits as described in claim 1, which is characterized in that the delay adjustment unit includes the 6th electricity
Resistance and the second capacitance, the 6th resistance be connected to the second switch unit output end and the third switch unit it is defeated
Between entering end, second capacitance and the 6th resistor coupled in parallel.
5. MCU hardware reset circuits as described in claim 1, which is characterized in that the third switch unit includes the 7th electricity
Resistance, the 8th resistance, third transistor and third capacitance, wherein：
The third transistor NPN type triode, the base stage of the third transistor connect one end of the 7th resistance, and described
Input terminal of the other end of seven resistance as the third switch unit, the base stage of the third transistor also pass through the described 8th
Resistance eutral grounding, the emitter ground connection of the third transistor, the collector of the third transistor are connect by the third capacitance
Ground, and the collector of the third transistor terminates the reset pin of the MCU as the output of the third switch unit.
6. a kind of BMS systems, including MCU, which is characterized in that further include that MCU hardware described in any one of claim 1 to 5 is multiple
Position circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721888339.5U CN207766239U (en) | 2017-12-28 | 2017-12-28 | A kind of MCU hardware reset circuits and BMS systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721888339.5U CN207766239U (en) | 2017-12-28 | 2017-12-28 | A kind of MCU hardware reset circuits and BMS systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207766239U true CN207766239U (en) | 2018-08-24 |
Family
ID=63185692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721888339.5U Expired - Fee Related CN207766239U (en) | 2017-12-28 | 2017-12-28 | A kind of MCU hardware reset circuits and BMS systems |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207766239U (en) |
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2017
- 2017-12-28 CN CN201721888339.5U patent/CN207766239U/en not_active Expired - Fee Related
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Granted publication date: 20180824 |
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| CF01 | Termination of patent right due to non-payment of annual fee |