CN207717163U - A kind of detection of gas flow rate circuit based on FPGA - Google Patents

Abstract

The utility model discloses a kind of detection of gas flow rate circuit based on FPGA, it includes FPGA processing units, the first ultrasonic probe S1, the second ultrasonic probe S2, the first ultrasonic wave transmitting the second ultrasonic wave of driving unit transmitting driving unit, the first ultrasonic wave receiving unit and the second ultrasonic wave receiving unit；The input terminal of first ultrasonic wave transmitting driving unit is connected with the delivery outlet of CPU core, and the output end of the first ultrasonic wave transmitting driving unit is connected with the first ultrasonic probe S1；First ultrasonic probe S1 is also connected with the input port of the first ultrasonic wave receiving unit, and the output end of the first ultrasonic wave receiving unit is connected with the input port of CPU core, and the signal of the first ultrasonic wave receiving unit receives opening end and is connected with the delivery outlet of CPU core；The counting Enable Pin EN0 of first counter T0 is connected with the delivery outlet of CPU core.The advantage that the utility model design is simple, control is flexible, high certainty of measurement and debugging difficulty are low.

Description

A kind of detection of gas flow rate circuit based on FPGA

Technical field

It is specifically a kind of using FPGA as the gas of central processing unit the utility model is related to a kind of detection of gas flow rate circuit Flow sensing circuit belongs to sensing and detection technique field.

Background technology

Detection of gas flow rate device, because any barrier member is not arranged for instrument circulation passage, belongs to as electromagnetic flowmeter Without hindrance flowmeter；Detection of gas flow rate device is usually that principle realizes measurement with " time difference method "：It is being flowed using ultrasonic signal The difference in downstream propagation times and adverse current propagation time seeks flow velocity in body, and then acquires flow.Therefore it is designed in physical circuit When usually require setting two ultrasonic probes, one be placed in measure pipeline upstream one be placed in downstream, utilize hardware circuit Controlled quentity controlled variable ultrasonic probe " to penetrating "：Ultrasonic signal is sent out from upstream probe, and downstream probe receives, by hardware circuit Timing unit (timer conter of such as microcontroller) measure the time that this ultrasonic wave travels to downstream from upstream, that is to say ultrasound Wave downstream propagation times；Similarly, downstream probe transmitting, upstream probe receive, and the adverse current propagation time are measured, when according to downstream propagation Between and time difference in adverse current propagation time fluid velocity can be found out according to fluid mechanics principle, and then find out flow.

To sum up, the key of ultrasonic flow rate measurement amount flow is：It is sent out using hardware circuit control ultrasonic probe Ultrasonic signal is penetrated, and starts timing, timing unit is immediately controlled after other side's ultrasonic wave receives ultrasonic signal and stops meter When to obtain the accurate propagation time.This just needs the control of hardware circuits which process device flexible, and has high speed timer counter list Member is to improve the precision and stability of measurement.Hardware configuration used by the measuring ultrasonic wave flow of mainstream includes at present：Monolithic Two kinds of machine and FPGA.

It measures by core of microcontroller, since microcontroller is in terms of logical operation, intelligent control, has preferable special Property, therefore system hardware and software design is all relatively simple, debugging is easy, but since microcontroller functional reliability is low, in some cases The reset of moment will also result in serious consequence, therefore systematic survey stability is not high, and the timer counter list inside microcontroller Member counting rate compared with the counting unit in this pure digi-tal integrated circuits of FPGA is slower, this would sit idle for the measuring precision It improves.Using FPGA, although core realizes the system measured because having invoked high-speed counting unit so that measuring essence in order to control Degree is high, and system job stability is high, but FPGA underactions in terms of intelligent control, this results in FPGA internal logics Design complexities are high.

There is also a kind of designs shared using two kinds of processors of FPGA and microcontroller, microcontroller to complete intelligence in existing counting It can control, FPGA completes high-speed counting, but makes system design complicated due to the use of two pieces of processors, in addition two pieces of processors It is responsible for different control and measurement task, therefore needs to realize that good data transfer and cooperation, debugging difficulty increase between them Add, and the logic function that this design does not make full use of FPGA powerful yet.

Utility model content

For deficiencies of the prior art, the purpose of this utility model is：There is provided that a kind of circuit design is simple, control It makes flexible, high certainty of measurement and debugging difficulty is low based on FPGA gas flow observation circuits.

To achieve the goals above, the utility model uses technical solution below.

A kind of detection of gas flow rate circuit based on FPGA, it is characterised in that：It includes FPGA processing units, the first ultrasound Wave probe S1, the second ultrasonic probe S2, the first ultrasonic wave transmitting the second ultrasonic wave of driving unit transmitting driving unit, the first surpass Acoustic receiver unit and the second ultrasonic wave receiving unit；

The FPGA processing units are mainly by CPU core, random access memory ram, read only memory ROM, the first counter T0 With the second counter T1 compositions；The first counter T0, which has, counts Enable Pin EN0；The second counter T1, which has, to be counted Enable Pin EN1；

The first ultrasonic probe S1 and the second ultrasonic probe S2 is transmitting-receiving integrated ultrasonic probe；

The ultrasonic wave transmitting driving unit is mainly made of transformer and driving triode；The output end of the transformer Emit the output end of driving unit for ultrasonic wave, the input terminal of transformer is connected with the collector of driving triode, the drive The base stage of dynamic triode is the input terminal that ultrasonic wave emits driving unit；

The ultrasonic wave receiving unit is mainly by analog switch, signal amplification circuit, signal filter circuit, comparator group At；First input/output terminal I01 of analog switch is the input port of the ultrasonic wave receiving unit, the second input of analog switch Output end I02 ground connection, analog switch select end A to receive opening end, analog switch for the signal of the ultrasonic wave receiving unit Common end be connected with the input terminal of signal amplification circuit, the output end of signal amplification circuit and the input terminal phase of filter circuit Connection, the output end of filter circuit and the input terminal of comparator connect, and the output end of comparator is the defeated of ultrasonic wave receiving unit Outlet；

The input terminal of the first ultrasonic wave transmitting driving unit is connected with the delivery outlet of the CPU core, the first ultrasound The output end of wave transmitting driving unit is connected with the first ultrasonic probe S1；First ultrasonic probe S1 is also with described The input port of one ultrasonic wave receiving unit is connected, and the output end of the first ultrasonic wave receiving unit is defeated with the CPU core Entrance is connected, and the signal of the first ultrasonic wave receiving unit receives opening end and is connected with the delivery outlet of CPU core；Described The counting Enable Pin EN0 of one counter T0 is connected with the delivery outlet of CPU core；

The input terminal of the second ultrasonic wave transmitting driving unit is connected with the delivery outlet of the CPU core, the second ultrasound The output end of wave transmitting driving unit is connected with the second ultrasonic probe S1；Second ultrasonic probe S2 is also with described The input port of two ultrasonic wave receiving units is connected, and the output end of the second ultrasonic wave receiving unit is defeated with the CPU core Entrance is connected, and the signal of the second ultrasonic wave receiving unit receives opening end and is connected with the delivery outlet of CPU core；Described The counting Enable Pin EN1 of two counter T1 is connected with the delivery outlet of CPU core.

Further, the analog switch is CD4051 chips.

Compared with prior art, the utility model has the following advantages that：The utility model integration realization list on fpga chip The basic unit module CPU core of piece machine, and high-speed counting unit is provided with for realizing the ultrasonic transmission time in FPGA Measurement, therefore will originally need two pieces of processor chips realize function be integrated in one piece of processing chip, simplify system Circuit structure, control is flexible, is conducive to system debug；In the present invention, the CPU due to being realized by soft core method of calling The core speed of service is better than common 51 microcontroller, and the counting rate for the high-speed counter being integrated in FPGA is also significantly better than independent meter Number device chips and microcontroller built in counter unit, therefore the utility model have the advantages that operating rate soon, high certainty of measurement； Since used ultrasonic probe is transmitting-receiving integrated probe in the utility model, probe was both sent out with transmitting and ultrasonic wave It penetrates driving unit connection also to connect with ultrasonic wave receiving unit, in order to avoid the train of signal between transmitter unit and receiving unit It disturbs, the utility model is provided with analog switch in ultrasonic wave receiving unit, and signal is realized by numerically controlled mode Gating or shutdown avoid the crosstalk (cannot receive ultrasonic wave simultaneously while a probe transmitting ultrasonic wave) between signal, Therefore the utility model also has the advantages that flexibly and effectively avoid signal cross-talk.

Description of the drawings

Fig. 1 is the utility model circuit structure diagram；

The positions Fig. 2 the utility model median filter element circuit structure chart；

Fig. 3 is ultrasonic probe installation position schematic diagram in the utility model.

Specific implementation mode

The utility model is described in further detail with reference to the accompanying drawings and detailed description.

A kind of detection of gas flow rate circuit based on FPGA of the utility model, it is by two ultrasonic probes and control electricity Road forms.First ultrasonic probe S1 and the second ultrasonic probe S2 is transmitting-receiving integrated ultrasonic probe；

For control circuit using fpga chip as processing unit, the particular circuit configurations of control circuit are as follows：

One, central processing unit structure

FPGA processing units are mainly by CPU core (51 core), random access memory ram, read only memory ROM, the first counter T0 and the second counter T1 compositions；First counter T0, which has, counts Enable Pin EN0；Second counter T1, which has, counts Enable Pin EN1。

Here for the internal structure of FPGA processing units further elucidated above, make technology explanation：Microcontroller sexual valence It is widely used than the advantages that high, control is flexible, it is low but there is also the speeds of service, extend phase outside the limited needs of internal resource The defects of closing resource will be integrated in the CPU core inside microcontroller, storage originally with the development of EDA technologies and microelectronic technique Device even peripheral circuit, which is integrated into large scale digital chip as FPGA, to be had become reality and obtains being applied to universal.Example 51 core of microcontroller, which is such as integrated in operation on fpga chip, can greatly improve the speed of service, compensate for the defect of 51 high speeds, The function of 51 microcontrollers, such as the timer conter of offer more capacity, higher counting rate can also be greatly provided simultaneously Unit replaces the timer conter of common 51 microcontroller.

Be in brief can on fpga chip integration realization microcontroller basic unit module, and the speed of service is excellent In common 51 microcontroller, this will not only improve system operating rate, measurement accuracy, and due to by the function of former singlechip chip It is integrated in fpga chip so that circuit structure is simplified.

In specific implementation, CPU core (51 core), random access memory ram, read only memory ROM, the first counter T0 and The form realization that the macroelement module of technology maturation is called may be used in two counter T1.It is to be noted that macroelement module Calling is a kind of soft core method of calling.

Two, ultrasonic wave emits driving unit

Ultrasonic wave transmitting driving unit is mainly made of transformer and driving triode；The output end of transformer is ultrasonic wave Emit the output end of driving unit, the input terminal of transformer is connected with the collector of driving triode, drives the base of triode The extremely input terminal of ultrasonic wave transmitting driving unit.Wherein driving triode is NPN triode, and transformer is step-up transformer.

Three, ultrasonic wave receiving unit

Ultrasonic wave receiving unit is mainly made of analog switch, signal amplification circuit, signal filter circuit, comparator；Mould First input/output terminal I01 of quasi- switch is the input port of the ultrasonic wave receiving unit, the second input and output of analog switch Hold I02 ground connection, analog switch that end A is selected to receive opening end, the public affairs of analog switch for the signal of the ultrasonic wave receiving unit End is connected with the input terminal of signal amplification circuit altogether, and the output end of signal amplification circuit is connected with the input terminal of filter circuit It connects, the output end of filter circuit and the input terminal of comparator connect, and the output end of comparator is the output of ultrasonic wave receiving unit End.Wherein, analog switch is that the above analog switch in two channels realizes that signal amplification circuit is realized by instrument amplifier, signal filter Wave circuit is common bandpass filter, and comparator is realized by amplifier.For example, analog switch uses CD4051 chips, signal amplification Circuit is realized that signal filter circuit is that the common bandpass filter realized using amplifier (is such as schemed by instrument amplifier AD623 chips Shown in 2).

The non-the utility model improvements of concrete structure of the above circuit, can be no longer superfluous herein using existing mature technology It states.

Four, physical circuit connection relation

The input terminal of first ultrasonic wave transmitting driving unit is connected with the delivery outlet of CPU core, and (this is to pass through FPGA certainly What the pin of chip was realized, the point connection of following CPU core and other circuit modules is realized by the pin of fpga chip, Explaination is not repeated below), the output end of the first ultrasonic wave transmitting driving unit is connected with the first ultrasonic probe S1；First Ultrasonic probe S1 is also connected with the input port of the first ultrasonic wave receiving unit, the output end of the first ultrasonic wave receiving unit with The input port of CPU core is connected, and the signal of the first ultrasonic wave receiving unit receives opening end and is connected with the delivery outlet of CPU core； The counting Enable Pin EN0 of first counter T0 is connected with the delivery outlet of CPU core.

The input terminal of second ultrasonic wave transmitting driving unit is connected with the delivery outlet of CPU core, and the transmitting of the second ultrasonic wave is driven The output end of moving cell is connected with the second ultrasonic probe S1；Second ultrasonic probe S2 also with the second ultrasonic wave receiving unit Input port be connected, the output end of the second ultrasonic wave receiving unit is connected with the input port of CPU core, the second ultrasonic wave receive The signal of unit receives opening end and is connected with the delivery outlet of CPU core；The counting Enable Pin EN1 and CPU core of second counter T1 Delivery outlet be connected.

Five, utility model works principle

Realizing the basic principle measured is：It can be according to stream according to the time difference in downstream propagation times and adverse current propagation time Mechanic principle finds out fluid velocity, and then finds out flow.As shown in figure 3, the first ultrasonic probe S1 setting is in upstream, second Ultrasonic probe S2 is arranged in downstream.

There is following data relationship according to principles of fluid mechanics：

Wherein, TB is the adverse current propagation time, and TA is downstream propagation times, and Q is the instantaneous flow of fluid, and K is hydrodynamics Correction factor (the amendment system between line average speed of the fluid on ultrasonic wave propagation path and the section average speed of fluid Number, can determine coarse value according to fluid mechanics principle), D is the internal diameter (diameter) of fluid line, and τ is that ultrasonic wave is visited in ultrasonic wave Propagation time in head and control circuit, θ are fluid flow direction and ultrasonic wave to the angle between penetrating direction.Find out fluid After instantaneous flow Q, take integral that can obtain the integrated flux in the period within certain period it.It is fluid stream above The basic fluid mechanics principle of measurement, it is described above in order to make operation principle explaination understand that spy does, but the utility model is simultaneously This ripe measurement method is not improved, therefore is not elaborated further here.

As long as by above-mentioned basic principle it is found that detecting that the adverse current of ultrasonic wave in a fluid is propagated by circuit of measurement and control Time TB and downstream propagation times TA can then obtain the instantaneous flow and integrated flux of fluid.It introduces and how to detect in detail below Adverse current the propagation time TB and downstream propagation times TA of ultrasonic wave in a fluid.

The measurement process of downstream propagation times TA is：CPU core is completed at the same time following operation.

1, CPU core emits driving unit transmission enabling signal (high-frequency pulse voltage letter by delivery outlet to the first ultrasonic wave Number), which becomes high-frequency and high-voltage electric pulse after being boosted again by step-up transformer after the first transistor Q1 amplifications becomes drive The high pressure activation signal of dynamic ultrasonic probe.Driving pulse voltage is added in probe both ends, and according to piezoelectric effect, piezo-electric crystal is swashed Hair, the first ultrasonic probe S1 launch ultrasonic wave.

2, while CPU core drives the first ultrasonic probe S1, CPU core is also connect by its delivery outlet to the first ultrasonic wave The signal for receiving unit receives opening end and sends a control signal and chooses the second input/output terminal I02 of analog switch, make its with The common end of analog switch is connected to, and ultrasonic signal cannot be introduced into the first ultrasonic wave receiving unit so as to avoid the string of signal It disturbs；

3, while closing the first ultrasonic wave receiving unit, CPU core is also received by its delivery outlet to the second ultrasonic wave The signal of unit receives opening end and sends the first input/output terminal I01 that a control signal chooses analog switch, makes itself and mould The common end connection of quasi- switch, the ultrasonic signal that the second ultrasonic probe S2 is received is (from the first ultrasonic probe S1 hairs The ultrasonic signal penetrated) get enter into the second ultrasonic wave receiving unit.

4, CPU core is also sent one and counted by its delivery outlet to the counting Enable Pin EN0 of the first counter T0 starts letter Number (high level) so that the first counter T0 is started counting up, and the first counter T0 is counted to counting pulse, due to counting arteries and veins The period for rushing signal is fixed, therefore can then obtain gate time by count value.

When the second ultrasonic wave receiving unit receives electric signal (the second ultrasonic probe of the second ultrasonic probe S2 outputs The ultrasonic signal received is converted to electric signal by S2), and the electric signal is amplified, is filtered and by it in a threshold value Voltage is compared, and comparator output high level (has indicated the second ultrasonic probe S2 if signal amplitude is more than threshold voltage It is received to the ultrasonic signal sent from the first ultrasonic probe S1) output signal of comparator is sent to the input of CPU core Mouthful, the input port of CPU core receives enabled to the counting of the first counter T0 by its delivery outlet after the comparator output signal EN0 is held to send a count stop signal (low level), the first counter T0 stops count value after counting and preserved, according to meter Numerical value can obtain counting the time it takes, this period is since the first ultrasonic probe S1 transmitting ultrasonic signals Until the second ultrasonic probe S2 receives the ultrasonic signal sent from the first ultrasonic probe S1, therefore according to first The count value of counter T0 can obtain downstream propagation times TA.

Similarly, the measuring principle and the measuring principle of downstream propagation times TA of adverse current propagation time TB is consistent, here It repeats no more.

In the case where measuring adverse current propagation time TB and downstream propagation times TA, just according to aforesaid fluid mechanics principle Data on flows can be obtained.

It is the operation principle that the utility model measures flow above, it can be seen that wherein use hydromechanical principle And method, but the process for obtaining above-mentioned various parameters is to rely on circuit connecting relation and phase interworking between each circuit module Close realization.

Finally illustrate, above example is merely intended for describing the technical solutions of the present application, but not for limiting the present application, although ginseng The utility model is described in detail according to preferred embodiment, it will be understood by those of ordinary skill in the art that, it can be to this The technical solution of utility model is modified or replaced equivalently, without departing from the objective and model of technical solutions of the utility model It encloses, should all cover in the right of the utility model.

Claims (2)

1. a kind of detection of gas flow rate circuit based on FPGA, it is characterised in that：It includes FPGA processing units, the first ultrasonic wave Probe S1, the second ultrasonic probe S2, the first ultrasonic wave transmitting the second ultrasonic wave of driving unit transmitting driving unit, the first ultrasound Wave receiving unit and the second ultrasonic wave receiving unit；

The FPGA processing units are mainly by CPU core, random access memory ram, read only memory ROM, the first counter T0 and Two counter T1 compositions；The first counter T0, which has, counts Enable Pin EN0；The second counter T1, which has to count, to be enabled Hold EN1；

The first ultrasonic probe S1 and the second ultrasonic probe S2 is transmitting-receiving integrated ultrasonic probe；

The ultrasonic wave transmitting driving unit is mainly made of transformer and driving triode；The output end of the transformer is super Sound wave emits the output end of driving unit, and the input terminal of transformer is connected with the collector of driving triode, the driving three The base stage of pole pipe is the input terminal that ultrasonic wave emits driving unit；

The ultrasonic wave receiving unit is mainly made of analog switch, signal amplification circuit, signal filter circuit, comparator；Mould First input/output terminal I01 of quasi- switch is the input port of the ultrasonic wave receiving unit, the second input and output of analog switch Hold I02 ground connection, analog switch that end A is selected to receive opening end, the public affairs of analog switch for the signal of the ultrasonic wave receiving unit End is connected with the input terminal of signal amplification circuit altogether, and the output end of signal amplification circuit is connected with the input terminal of filter circuit It connects, the output end of filter circuit and the input terminal of comparator connect, and the output end of comparator is the output of ultrasonic wave receiving unit End；

The input terminal of the first ultrasonic wave transmitting driving unit is connected with the delivery outlet of the CPU core, the first ultrasonic wave hair The output end for penetrating driving unit is connected with the first ultrasonic probe S1；First ultrasonic probe S1 also the first surpasses with described The input port of acoustic receiver unit is connected, the input port of the output end and the CPU core of the first ultrasonic wave receiving unit It is connected, the signal of the first ultrasonic wave receiving unit receives opening end and is connected with the delivery outlet of CPU core；First meter The counting Enable Pin EN0 of number device T0 is connected with the delivery outlet of CPU core；

The input terminal of the second ultrasonic wave transmitting driving unit is connected with the delivery outlet of the CPU core, the second ultrasonic wave hair The output end for penetrating driving unit is connected with the second ultrasonic probe S1；Second ultrasonic probe S2 also the second surpasses with described The input port of acoustic receiver unit is connected, the input port of the output end and the CPU core of the second ultrasonic wave receiving unit It is connected, the signal of the second ultrasonic wave receiving unit receives opening end and is connected with the delivery outlet of CPU core；Second meter The counting Enable Pin EN1 of number device T1 is connected with the delivery outlet of CPU core.

2. a kind of detection of gas flow rate circuit based on FPGA according to claim 1, it is characterised in that：The simulation is opened It is CD4051 chips to close.